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Physical Design STA Frontend Design DFT Verification CMOS Basics Linux
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ATPG Basic Tool Flow
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May 25, 2020
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ATPG Basic Tool Flow
The below figure shows the basic process flow for the ATPG tool.
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Physical Design STA Frontend Design DFT Verification CMOS Basics Linux
ATPG Basic Tool Flow
1. Invoke Tessent Shell using the “tessent -shell” command. Set the context to “patterns -scan
set_context command, which allows you to access ATPG functionality.
2. The ATPG tool requires a gate-level design netlist and a DFT library.
3. After reading the library and netlist, the tool goes into setup mode.
4. After performing all the desired setup you can exit setup mode which triggers a number of operations.
first attempt to exit setup mode, the tool creates a flattened design model.
5. After design flattening, the ATPG tool performs extensive analysis on the design to learn behavior
useful for intelligent decision making in later processes, such as fault simulation and ATPG.
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6. In next step tool begins design rules checking(DRC).
7. After
Physical Design
the design STA
passes Frontend the
rules checking, Design DFTanalysis
tool enters Verification CMOS
mode, where you Basics Linux
can perform sim
pattern set for the design.
8. At this step you may want to create patterns. You can also perform some additional setup steps, suc
the fault list.You can then run ATPG on the fault list. During the ATPG run, the tool also performs fault s
verify that the generated patterns detect the targeted faults.
9. After generating a test set with the ATPG tool, you should apply timing information to the patterns an
design and patterns before handing them off to the vendor.
ATPG Tool Inputs and Outputs
ATPG Tool Inputs and Outputs
The ATPG tool uses multiple inputs to produce test patterns, a fault list, and ATPG information files.
ATPG Process
The objective of ATPG is to create a set of patterns that achieves a given test coverage, where test cov
total percentage of testable faults the pattern set actually detects.
ATPG consists of two main steps:
1) generating patterns
2) performing fault simulation to determine which faults the patterns detect.
Mentor Graphics ATPG tools automate these two steps into a single operation or ATPG process.
The two most typical methods for pattern generation are random pattern test generation and determin
test generation.
Random Pattern Test Generation
The ATPG tool uses random pattern test generation when it produces a number of random
patterns and identifies only those patterns that detect faults.
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Deterministic Pattern Test Generation
The ATPG
Physical
toolDesign STA
uses deterministicFrontend Design
test pattern DFTwhenVerification
generation it creates a testCMOS Basics
pattern Linux
intended to de
fault. The procedure is to pick a fault from the fault list, create a pattern to detect the fault, fault simulate
and check to make sure the pattern detects the fault.
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