Integrated Circuits

ECE481
Fall 2021
M3: Digital IC Design
Lecture 4
VHDL TestBench
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

D. Khalil ECE481 – M3 Lecture 4 1

VHDL Testbench
• It is a VHDL model containing:
– Device under test (DUT)
– Stimulus Generation
– Result Checking
• Must be complete: Test all cases automatically.
• Uses VHDL statements: Wait, Report, and Assert
• Can simulate: RTL, gate-level netlist, and extracted layout

Extracted Result
Stimulus DUT
Checking
Generation
(Assertions)

Testbench

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 The REPORT statement
• REPORT string [SEVERITY type];

• This statement simply prints out the specified string to the Transcript
window (at the bottom of the screen).
• Strings are represented in double quotes.

• Example:
REPORT “Start of test case 1”;
– Prints the string “Start of test case 1” to the Transcript (without
quotes) with the simulation time.

• The severity argument merely allows you to specify whether what you
are reporting is a NOTE, WARNING, ERROR, or FAILURE.

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The ASSERT Statement

• ASSERT condition [REPORT string] [SEVERITY type];

• The core of our testbenches.

• It allows us
– to test that values match what we expect them to be, and
– if they are NOT (the condition is false), displays a report statement,
– and finally gives the user an ERROR or WARNING.

• Assertions are composed using input and output signals of a given

“Circuit”.
• Circuits are treated as black boxes.
• Verification should not depend on internal implementations.
• All functionality aspects should be covered.

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 Testbench Steps
1. Declare and Instantiate the DUT
2. Declare all input and output signals and initialize them
3. Process (1) – Periodic Signals (clock)
– Generate periodic signals, e.g. clock, …
4. Process (2) – Apply input patterns
– Assign values to circuit inputs.
– Add a WAIT statement to wait to "propagate" the input values.
• For combinational logic, wait for the delay of the logic.
• For sequential logic, we should wait for the clock period.
– Check outputs against expected result using assertions.

Result
Stimulus DUT
Checking
Generation
(Assertions)

Testbench

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Example : Add-Accumulate Design

• The circuit has 4 input signals: a, b, sel, ck (total 10 bits)

and two output signals: sum (4 bits), carry (1bit).
• Behavior :
– If (sel == 0) sum <= a + b
Otherwise sum <= regout + b
– At ck +ve edge regout <= sum

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 Add-Accumulate Entity
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity addaccu is
-- input/output ports
port (
a : in std_logic_vector ( 3 downto 0 ) ;
b : in std_logic_vector ( 3 downto 0 ) ;
sel : in std_logic ;
ck : in std_logic ;
sum : inout std_logic_vector ( 3 downto 0 ) ;
carry : out std_logic
)
end addaccu ;

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Add-Accumulate Architecture
Architecture data_flow of addaccu is
signal mux_out : std_logic_vector ( 3 downto 0 ) ;
signal reg_out : std_logic_vector ( 3 downto 0 ) ;
signal s_temp : std_logic_vector (4 downto 0) := "00000";
begin
mux_out <= a when sel='0' else reg_out;
s_temp <= ('0' & b) + ('0' & mux_out); -- All must have the same # of bits
sum <= s_temp(3 downto 0);
carry <= s_temp(4);
process ( ck ) -- Register
begin
if ( ck'event and ck ='1' ) then
reg_out <= sum;
end if;
end process;
end data_flow;

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 Add-Accumulate Testbench
Must develop a test strategy and test plan
• List design features to test (addition and accumulation)
• Specify detailed test cases for each feature with good coverage
• Design testbench(es) Tested
Sel a b
Delay Expected Expected
feature (ns) (sum) (carry)
0 2 0
1 3 0
For example, will create 2 testbenches: 2 4 0
+ 3 5 0
TB1: Addition testbench 4
5
6
7
0
0
6 8 0
7 9 0
2
8 10 0
9 11 0
Adder 0 50
10 12 0
11 13 0
12 14 0
13 15 0
14 0 1
15 1 1
10 5 15 0
12 2 14 0
1 14 15 0
15 10 9 1

Random
testing
D. Khalil ECE481 – M3 Lecture 4 9

Add-Accumulate TB1 Entity

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.NUMERIC_STD.all;

-- Entity declaration for your testbench. Don't declare any ports.

ENTITY testbench IS
END ENTITY testbench;

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 Add-Accumulate TB1 Architecture
ARCHITECTURE test_addaccu OF testbench IS

-- Component Declaration for the Device Under Test (DUT)

COMPONENT addaccu IS
-- Just copy and paste the input and output ports of your module as such.
port (
a : in std_logic_vector ( 3 downto 0 ) ;
b : in std_logic_vector ( 3 downto 0 ) ;
sel : in std_logic ;
ck : in std_logic ;
sum : inout std_logic_vector ( 3 downto 0 ) ;
carry : out std_logic
);
END COMPONENT addaccu;

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Add-Accumulate TB1 Architecture

-- Declare input signals and initialize them
SIGNAL sel : std_logic := '0';
SIGNAL clock : std_logic := '0';
SIGNAL a : std_logic_vector (3 downto 0) := X"0";
SIGNAL b : std_logic_vector (3 downto 0) := X"0";

-- Declare output signals and initialize them

SIGNAL sum : std_logic_vector (3 downto 0) := X"0";
SIGNAL carry : std_logic := '0’;

-- Constants
constant delay_time: time := 50 ns;

BEGIN
-- Instantiate the Device Under Test (DUT)
dut: addaccu PORT MAP (a, b, sel, clock, sum, carry);
FOR dut: addaccu USE ENTITY WORK.addaccu (data_flow);

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 Add-Accumulate TB1 Architecture
stim_proc: PROCESS IS

PROCEDURE check_add( constant in1 : in positive;

constant in2 : in positive) is
-- Input is +ve integer to facilitate applying input values
BEGIN
-- Assign values to circuit inputs.
a <= std_logic_vector(to_unsigned(in1, a'length));
b <= std_logic_vector(to_unsigned(in2, b'length));
-- Wait for some time for the simulator to "propagate" their values.
wait for delay_time;
-- Check output against expected result.
Assert sum = a + b Report "S not equal to A+B"
Severity Error;
END PROCEDURE check_add;

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Add-Accumulate TB1 Architecture

BEGIN
sel <= '0'; -- sel held at '0'
clock <= '0'; -- clock held at '0'
Report "---- case 1: 'a' held at 2, Loop on all values of 'b' ";
for i In 0 to 15 loop -- Don’t have to declare i
check_add(2, i);
end loop;
Report "---- End of case 1 -------------";

Report "---- case 2: Some Random testing of 'a' and 'b' ";
check_add(10,5);
check_add(12,2);
check_add(1,14);
check_add(15,10);
Report "---- End of case 2 -------------";

WAIT; -- don't repeat above test vectors

END PROCESS stim_proc;

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 Add-Accumulate TB1 Results
Case 1 Case 2

a b sum carry
0 2 0
• Compare with test strategy expected output 1
2
3
4
0
0
3 5 0
4 6 0
5 7 0
6 8 0
7 9 0
2
8 10 0
9 11 0
10 12 0
11 13 0
12 14 0
13 15 0
14 0 1
15 1 1
10 5 15 0
12 2 14 0
1 14 15 0
15 10 9 1
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Add-Accumulate Testbench
Tested CL Delay Exp. Exp.
Sel A b regout
The second testbench is: feature K
1
(ns)
0
(sum)
0
(carry)
0
0
0 0 0 0
TB2: Accumulation testbench 1 0 1 0
1
0 0 1 0
1 1 3 0
2
0 1 3 0
1 3 6 0
3
0 + 3 6 0
Same testbench structure 4
1 6 10 0
0 6 10 0
Add clock process 5
1
0
10
10
15
15
0
0
Modify stimulus process 6
1
0
15
15
5
5
1
1
1 5 12 0
7
Accum 0 5 12 0
1 0 25
ulator 1 12 4 1
8
0 12 4 1
1 4 13 0
9
0 4 13 0
1 13 7 1
10
0 13 7 1
1 7 2 1
11
0 7 2 1
1 2 14 0
12
0 2 14 0
1 14 11 1
13
0 14 11 1
1 11 9 1
14
0 11 9 1
1 9 8 1
15
0 9 8 1
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 Add-Accumulate TB2 Architecture
-- Clock process definitions( clock with 50% duty cycle )

clk_process :process
begin
clock <= '1’;
s_last <= sum; -- Save the current value of 'sum’ for assertion
wait for clk_period/2;
clock <= '0';
wait for clk_period/2;
end process;

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Example : “addaccu” TB2 Architecture 2

Report "case 2: Sequential path - Loop on all values of 'b' ";
-- Assign values to circuit inputs.
a <= X"0";
for i In 0 to 15 loop
if i=0 then
b <= X"0";
else
b <= b + 1;
end if;
wait for clk_period;
if i > 0 then -- Check output against expected
Assert sum = b + s_last
Report "Sum not equal to B + Older Sum"
Severity Error;
end if;
end loop;
Report "---- End of case 2 -------------";

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 Example : “addaccu” TB2 Results

• Compare with test strategy expected output

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