VHDL

Working with clock in VHDL

Ing. Michal Lucki, PhD., CTU in Prague, FEE, Dept. of

Telecommunication
4 bit mux case with a clock signal
This multiplexer has got 4 data inputs (a, b, c, d), an address Anytime different than the rising edge, the multiplexer is inactive
vector s (1 downto 0), a clock, and the output f. and the output is not being updated until the next rising edge.
The output value is updated based on the address and the In case the clock is too slow and the same input is updated
input value, when a rising edge of the clock is detected. multiple times during one clock period, some data would be lost.

If a rising
case is embedded in edge, then
if-elsif transfer the
First you end case, values
then you and if
Clock defined as a
standard logic variable

The multiplexer addresses the output (f) to take the value

from one of the four inputs (a, b, c, d) based on a 2-bit
address vector (s) that can take 00, 01, 10, 11.
Ing. Michal Lucki, PhD., CTU in Prague, FEE,
Dept. of Telecommunication
Testbench
clock will be periodic
half period is 0 the
other half is 1 rising
edge can be observed

some simulators work with "wait"

ghdl doesnt stop the run so we end it
Clock period definitions manually after 200 ns
Signals are created

I don't want the clock and

data change at the same
clock belongs to time, I delay by 3 ns
standard logic it
exhibits transitions checking if data is
between 0 and 1 taken from input a

checking again if data

is taken from input a

checking if data is
Ing. Michal Lucki, PhD., CTU in Prague, FEE,
taken from input b
Dept. of Telecommunication
Waveforms (timing diagram)

Address 00 Address 01 Address 10 Address 11 Address 00

f copied 2x from f copied 2x from f copied 2x from f copied 3x from again
a at the rising b at the rising c at the rising d at the rising
edge edge edge edge

Ing. Michal Lucki, PhD., CTU in Prague, FEE,

Dept. of Telecommunication
 D-type flip-flop in VHDL To reset to the initial state, let us introduce the clear
functionality:

The D-flip-flop keeps the value in memory (q) until the

next rising edge of the clock when the memory is
updated.
The entity includes clock, clear, data input D and
complementary outputs q and not_q (related to each
other) that represent the memory
clr clears immediatelly
(asynchronously) without
waiting for the rising edge
of clk

clear and clock are if rising edge of clock is

standard logic inputs that detected it check data on D
can be 0 or 1 like other and updates q and noq
inputs
q and noq are
complementary outputs
that are updated at the
Ing. Michal Lucki, PhD., CTU in Prague, FEE, same time
Dept. of Telecommunication
Testbench before 3 ns the
outputs will be
uninitialized

we check if D is
copied to q at the
nearest rising edge of
clock

we update is to get 1 at q
half of the clock because later we want to
period it is 0 another test the clear function
half it is 1 we can
observe the rising
edge

we end it
manually after
200 ns

Ing. Michal Lucki, PhD., CTU in Prague, FEE,

Dept. of Telecommunication
Waveforms (timing diagram)

Q copied from D
Q copied from D Q copied from D Q copied from D Q cleared immediatelly
at the rising edge
at the rising edge at the rising edge at the rising edge (asynchronously)

For more details, please, see the lab files

Ing. Michal Lucki, PhD., CTU in Prague, FEE,

Dept. of Telecommunication
Thank you for your attention