PERIME OBJECTIVE:- To verify various Logic gates. QUTCOME:: To get familiarized with pin configuration of different types of 744 series TTL Ics. Apparatus Required:- Bread board , IC-7400 (NAND Gate ) , IC-7402 (NOR Gate ) , IC-7404 (NOT Gate ) , IC-7408 (AND Gate ) , IC-7432 (OR Gate ) , IC-7486 (EX- OR Gate ) Connecting wires ,etc. THEORY::- Logic gate is a circuit with one output and two or more input channels. An output signal occurs only for certain combination of input signals. Logic circuits are used to perform various computer functions. NAND GATE (7400):- The term NAND is a contraction of expression NOT-AND- '\ NAND gate therefore is an AND gate followed by an inverter. It is defined as whenever all the input is high then output must be low otherwise output is high. Schematic symbol of 2 -INPUT NAND gate is shown below. Mathematically it is expressed as y =A.B Truth table of 2- INPUT NAND gates is shown in table. Tay : AND D—AUi wo Lat See Tag ip ip op ip ip op oN L 1C-7400 ‘Vhe output is high when either of inputs A or B is high, or if neither is high. In other words, it is normally high, going low only if both A and B are high,NOR GATE (7402) :; The NOR gate is an improved logic element used for implementing decision making logic function. The term NOR is a contraction of expression NOT-OR .The NOR gate isessentially a circuit containing the logic function of an OR gate and an inverter. It is defined as whenever all the inputs are low then output must be high otherwise output is low. Schematic symbol of 2- input NOR gate is shown below. yee nen le: _P ip ip op ip ip Gna Pip “ip oP ip Ip’ ond ‘The output is high only when neither A nor B is high. That is, it is normally high but any kind of zero input will take it low. NOT GATE (7404):- The Simplest from of logic circuit is the INVERTER or NOT gate, It can have one input and one output terminal. It is defined as, when ever input is high then output is low and the vice-versa, or we can say that the inverter is a logic clement whose output state is always opposite of its input state. Schematic Symbol is shown. + 0 Output - | Cutout | ' | LTT ip ©P GnaAND GATE (7408) It can have two oF more input and a single output . Its defined as therwise output is low. Logic when all the inputs are high then output must be high ot expression for the AND gate is AB. A mechanical analogy and Schematic Symbol is shown. ’ The output is high only eee =) | Lol [rel re when both inputs A and B are high ‘ip| ipl oP ip! ipl op Gnd Soa ao OR GATE (7432) : It can have two or mote input and a single output It is defined as whenever any one or all the inputs are high then output must be high otherwise Jow. A mechanical analogy and Schematic Symbol is shown. ip ip © ip | op can c]\y jrlomla TTT 6] {7 [ono | | ip ip °P ip ip oP EX-OR GATE (7486) := The EX- OR gate operation is widely used in digital eireut It is not a basic operation and can be performed using the basic gates ~ é ND, OR,and NOTor universal gates NAND or NOR. It is similar to the basic OR gates except that the Output is low, when both the inputs are high(1)or low (0). The output of the gate is high (1) when any one input is high (1). The standard symbol is below. THoomoo w Exclusive-OR gate A De em mor a | _ Output a2 [Boma ofo] o ‘fi Bs ez. ote t ip| IPE oP) tpl ip) P| Gna ast PROCEDURE:- 1. Make the connections as shown in the figure. 2. Connect Pin No-7 to GND. 3. Connect Pin No-14 to Vee. RESULT: - . Truth table of various logic function (OR, NOR, NOT, AND, NAND, EX-OR GATE) are verified. PRECAUTIONS: 1) All Connections should be according to circuit diagram. 2) All Connections should be right and tight. 3) Reading should be taken carefully. 4) Switch off Power supply after completing the Experiment.EXPERIMENT NO.2 OBJECTIVE: - Implementing HALF ADDER, FULL ADDER using basic logis gates. QUTCOME:- To be able to understand and verify the concepts of Adder using IC. APPARATUS REQUIRED: - Bread Board, IC 7408, IC 7486, IC 7432, Connesting wire etc. THEORY:- Adder circuit is a combinational digital circuit that is used for adding two numbers. A typical adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as the output. Typically adders are realized for adding binary numbers but they can be also realized for adding other formats like BCD (binary coded decimal, XS-3 ete. Besides addition, adder circuits can be used for a lot of other applications in digital electronics like address decoding, table index calculation etc. Adder circuits are of two types: Half adder ad Full adder. Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other is the carry bit, C. The Boolean functions describing the half-adder are: S =A @B C=AB Full-Adder: The half-adder does not take the carry bit fium its previous stage into account. This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder. The Boolean functions describing the full-adder are: S=(xAy)ACin C=xy+Cin(x Ay) diagram: HALF ADDER CIRCUIT DIAGRAM:TRUTH TABLE [ INPUTS | OUTPUTS | AlB|s|lec Lo fololo [ofala]o 1 folio Lt fife Tr] BOOLEAN EXPRESSIONS: S=A@B CHA B Full adder circuit diagram: FULL ADDER CIRCUIT DIAGRAM ;FULL ADDER TRUTH TABLE INPUTS | | OUTPUTS cin | os c -lolele | rle]-)-lojololel>| -lojo|-/o/-|=|e +|-l-lo - BOOLEAN EXPRESSIONS: S=A®BOC C=AB+BCin+A Cin 7408 YY14] [ts] [re] [at] [ro] [9] fs ND PROCEDURE: 1, Make the connections as shown in the figure. 2. Connect Pin No- 8 to GND. 3. Connect Pin No-16 to Vec. RESUL ‘The observation table of half and full adder is verified. PRECAUTIO! All Connections should be according to circuit diagram, All Connections should be right and tight, Reading should be taken carefully. Switch off Power supply afier completing the experimentEXPERIMENT NO.3 OBJECTIVE: - Implementing HALF SUBTRACTOR, FULL SUBTRACTOR using basic logic ¥ gates. QUTCOME:- To be able to understand and verify the concepts of Subtractor using IC. APPARATUS REQUIRED: - Bread Board, IC 7404, IC 7486, IC 7408, IC 7432 Connecting wire ete, THEORY : Half subtractor and full subtractor: “In digital electronics, half subtractor and full subtraetor are one of the most important combinational circuit used. Half subtractor and full subtractor are basically electronic devices or we can say logical circuits which performs subtraction of two binary digits In this article, we are going to discuss half subtractor and full subtractor theory and also discuss the terms like half subtractor and full subtractur boolean expression, half subtractor and full subtractor circuit diagram etc. Half subtractor As like addition operation of 2 binary digits, which produces SUM and CARRY, the subtraction of 2 binary digits also produces two outputs which are termed asdifference and borrow. The simplest Possible subtraction of 2-bit binary digits consists of four possible operations, they are 0-0, Oc 1- Gand 1-17 The operations 0-0, 1-0 and 1-1 produces a subtraction of I-bit output whereas, the “maining operation 0-1 produces a 2-bit output. They are referred asdifference and borrow bit respectively. This borrow bit is used for subtraction of the next higher pair bit So, we can define half subtractor as a combinational circuit which is capale of performing subtraction of 2-bit binary digits is known as a half subtractor. Here, the binary digit from which the other digit is subtracted is called minuend and the binary digit which is to be subtracted is known as the subtrahend Half subtractor truth table and circuit diagram Half subtractor truth table[ "Inputs | (Outputs “x jy | o 7 0 o 0 0 ’ 0 1 16 e: 1 o 1 0 1 1 0 a) In the above truth table of half subtractor, the two input variables X and Y represents minuend and subtrahend respectively. The two output functions difference andborrow are termed as D and B respectively. Using the truth table of half subtractor, we can design he half subtractor circuit diagram as below. Half subtractor circuit diagram : [Ty The half subtractor boolean expressions are : + D=(XY+XY)=X@OY + B=X’Y Fuil Subtractor Half subtractor boolean expression : When there is a situation where the minuend and subtrahend number contains more significant bit, then the borrow bit which is obtained from the subtraction of 2-bit binary digits is subtracted from the next higher order pair of bits. In such situation, the subtraction involves the operation of 3 bits. Such situation of subtraction can’t handle by a simple half subtractor? So, combining two half subtractor we can form another combinational circuit which can perform this type of operation This circuit is known as the full subtractor.So we can define full subtractor as a combinational circuit which takes three inputs and produces two outputs difference and borrow. Below is the truth table of the full subtractor, we have used three input variables X, Y and Z which refers to the term minuend, subtrahend and borrow bit ference and borrow are named as D and B respectively. y respectively. The two outputs Full subtractor truth table Inputs Outputs x Y z ° 8 0 0 0 ° 0 0 | 1 1 t o | 4 ° 1 } o | oa 1 ° 1 a 1 o | o | 4 ° 1 | 0 1 o 0 a fo ° o 0 a 1 1 1 Full subtractor circuit diagram : The construction of full subtractor circuit diagram involves two half subtractor joined by an OR gate as shown in the above circuit diagram of the full subtractor. The two borrow bits generated by two separate half subtractor are fed to the OR gate which produces the find borrow bit, The final difference bit is the combination of the difference output of the first half adder’ and the next higher order pair of bitsFull subtractor bootean expression The full subtractor bootean expressions are 9 QOYZ 4 YZ + x2 + xvZ) =x @YOZ * OVZ+ XYZ + XYZ + XVZ)= XV @ 2) +YZ ~ PROCEDURE |. Make the connections as shown in the figure. 2. Connect Pin No- 8 to GND, 3. Connect Pin No-16 to Vee. The observation table of half and full subtractor is verified, PRECAUTION: |. All Connections should be according to circuit diagram. 2. All Connections should be right and tight Reading should be taken carefully. 4. Switch off Power supply after completing the experiment.EXPERIMENT NO. 4 OBJECTIVE : Implementing binary- to-gray , gray to binary code conversion. OUTCOME : To be able to understand and verify the concepts of conversion using Digital board DBO6.. APPARATUS REQUIRED: - Bread Board, ICs- 7486, Connecting wire, Power supply etc. THEORY:- The gray code is a non weighted code, The successive gray code differs in one bit position only that means itis a unit distance code. Its also referred as cyclic code Binary code is the simplest form of computer code or programming data, It is represented entirely by a binary system of digits consisting of a string of consecutive zeros and ones, Logic diagram & Truth Table : (Logic | = +SV & Logic 0= GND)ps Jez , [1 [Bo [Decimal |@s_joz_ |¢1__ | 60 0 |o 0 0 0 o |o0 0 0 o jo 0 1 1 o jo 0 1 o jo 1 0 2 o jo 1 1 o |o 1 1 3 o jo 1 0 o |1 0 o 4 o 4 1 ° o |1 o 1 5s ‘jo ff 1 1 o |4 1 0 6 Oneld 0 1 o |1 1 1 7 o jf 0 ° 8 1 |o 0 0 8 1/4 0 o 3 1 |o 0 1 9 1 |4 0 1 |10 1 |o 1 0 10 4 if 1 1 j "1 1 |o 1 1 “ 1 fa 1 ° | 12 1 1 0 0 12 1 0 4 0 13 1 1 0 1 13 1 0 4 1 14 1 [i 41 oO 14 1 Oo o 41 15 1 \4 1 1 18 1 |o o 0 Binary code Gray code Table 1 Table 2 Procedure : 1. Connect +5 V and ground to their indicated position on DBO6 experiment board from external DC power supply or from DC power block of Digital Lab ST2611 Connect inputs BO, BI, B2, B3 as per truth table 2to binary to gray eode converter as shown in fig. Switch ON the power supply. 4, Observe output GO, G1, G2, G3 on multimeter or on LED Display of Di ST2611 5. Repeat above step for remaining inputs and prove truth table Lab6. Repeat above steps for gray to binary code converter and prove truth table.(Refer fig, 2 & table 2,1) , Result : The observation of conversion is verified. Precautions: 1. All connection should be according to circuit diagram. : 2. All connections should be right and tight. 3. Switch off power supply when done.PERIM) NO.5 OBJECTIVE: - Implementing 3x8 line DECODER. QUTCOME: - To be able to understand and verify the concepts of de-coding using IC 74138. APPARATUS REQUIRED: - Bread Board, ICs- 74138, Connecting wire etc. THEORY:- 3:8 DECODER:- A decoder is a combinational circuit that converts binary information from n line to a maximum of 2" unique output lines . The name decoder is also used in conjunction with some code converters such as a BCD to seven segment decoder. The block diagram of a decoder is shown in the figure. Decoder |_» ne 2c fae oC emg 2% Pin Configuration OF 1C 74138A va | aa} fle) ge} vec 5v 7 a a 1 */b—- : Ga 3 _ ew fe] 7 vec Sv a | IC 74138 USED AS A DECODER Decoder outputFUNCTION TaBLE:- When used as a Decoder:- é Input lines Enable lines out Put lines Cc B /A |G1 |G2A |G2B]/Yo |Y |Y |Y |Y PROCEDUR! 1. Make the connections as shown in the figure, 2. Connect Pin No- 8 to GND. 3. Connect Pin No-16 to Vee. RESULT: - The observation table of decoder and encoder are verified. PRECAUTION:- 1, All Connections should be according to circuit diagram. . All Connections should be right and tight. Reading should be taken carefully. Switch off Power supply after completing the experiment.EXPERIMENT NO.6 Implementating 8x3 line ENCODER. OBJECTIV! QUTCOME:- To be able to understand and verify the concepts of ending using IC 74147. APPARATUS REQUIRED; - Bread Board, ICs- 74147, Connecting wire etc. ‘THEORY:- ENCODER:- A decoder is a combinational circuit that converts binary information from 2" fine to a maximum of n unique output lines. Encoder do reverse operation to that of Decoder. It is used in the transmitter circuit. yo) T 1 24n inputs 1 Ageneral 28nton ENCODER Mn) Block diagram of Encoder Octal Inputs DI D2 D3 D4 DS D6 D7 v2 Binary Y1 Outputs vo Logical diagram of EncoderIC-74147 of Encoder FUNCTION TABLE:- OBSERVATION TABLE FOR ENCODER:- 2 3 4 5 6 7\A2 At AD|GS EO Xx XX XX XX X|H H HH LH HHH HHH HH H HIH ee 1 (eee ue Xe eee ae eee ae Lx XX X LHHAH|L HH LX X X L HHH HH LX X LHHHH HIH LH LX L HH HHH H\H H tL tL HHH HHH 4H Lx XX xX X LH HEL HPROCEDURE: 1. Make the connections as shown in the figure. 2. Connect Pin No- 8 to GND. 3. Connect Pin No-16 to Vee. RESULT: - The observation table of encoder is verified. PRECAUTION: 1. All Connections should be according to circuit diagram. N All Connections should be right and tight. we Reading should be taken carefully. 4. Switch off Power supply after completing the experiment.EXPERIMENT NO.7 OBJECTIVE:- Implementing 4x1 and 8x1 multiplexers. QUTCOME:- Should be able to understand multiplexers. APPARATUS REQUIRED: - Three input AND Gate & Four input OR Gate Connecting wire and trainer kit etc. THEORY: What is a multiplexer? It quite often happens, inthe design of large-scale digital systems, that a single line is required to carry two or more different digital signals. Of course, only one signal at a time can be placed on the one line. What is required is a device that will allow us to select, at different instants, the signal we wish to place on this common line. Such a circuit is referred to as a Multiplexer. ‘A multiplexer performs the function of selecting the input on any one of 'n' input lines and feeding this input to one output line. Multiplexers are used as one method of reducing the number of integrated circuit packages required by @ particular circuit design. This in tun reduces the cost of the system. ‘Assume that we have four lines, C0, C1, C2 and C3, which are to be multiplexed ona single line, Output (f). The four input lines are also known as the Data Inputs. Since there are four inputs, we will need two additional inputs to the multiplexer, known as the Select Inputs, to select which of the C inputs is to appear at the output. Call these select lines A and B. The gate implementation of a 4-line to I-line multiplexer is shown below:‘The cire! mbol for the above multiplexer and truth table ¥ [Inputs output aa 0 Oe Dats ct Inpus - £tL— oupu 0 ‘jar fel C2 c3 A B 1 0 (C2 T 1 |C3 Select Irputs Table for 4X1 Mux 4X1 Mux PROCEDURE:- 1. Make the connections as shown in the figure. 2. Connect Pin No- 7 to GND. 3. Connect Pin No-14 to Vcc. RESULT: - The observation table of 4X1 Multiplexer is verified PRECAUTION:- 1. All Connections should be according to circuit diagram. . All Connections should be right and tight. Reading should be taken carefully. wv Switch off Power supply after completing the Experiment.EXPERIM BALK OBJECTIVE: - Implementing 1x4 and 1x8 DEMULTIPLEXERS. J QUTCOME::- To be able to understand and verify the functioning of Demultiplexer. |PPARATUS REQUIRED; - Bread Board, ICs- 74138, Connecting wire ete: THEORY:- 1:8 DMUX:- Dmux means one into many. Dmux isa logic circuit with one input and many outpu. By applying contol signal we can steer the input signal to one of the lines Given figure illustrates that circyit has one input signal, m control signal and n output signal. control signal ipa signal Demulti- rutpet sgt plexer Block Diagram of Demultiplexervec 8 | GNo yo [1s}-——~ —{4 | Gan va [aa — IC pts | BF vz [8 GND ; vs fe} P| = ys | }—— * — SELECT LINE IC 74138 USED AS DMULTIPLEXERwhen used as a Demultiplexer:- vp Selection lines Output lines Gl c BIA oy Olean kV 2a | pV ea) lovin |v One NTT, 1 0 0 fo oft fi 1 fr fi fi fi 1 0 o ft rt fo fi 1 ft fi fi fi 1 0 1 fo 1 [i fo yf ff fi fi I 0 1 |i 1 ft fi o fF ft ft fi 1 I 0 fo r fi ft r fo fr ft fi Fi T 0 fi rf ft i fi fo fi ft T 1 1 {0 r fi ft uf rofo ft i T r i rofr ft lS Paro _ _ feria lIpROCEDURE:- : 1, Make the connections as shown in the figure. 2, Connect Pin No- 8 to GND, 3, Connect Pin No-16 to Vee, RESULT: - The observation table of Demultiplexer are verified, PRECAUTION:- 1. All Connections should be according to circuit diagram. ._ All Connections should be right and tight. . Reading should be taken carefully. nm 9 fs) . Switch off Power supply after completing the experiment.EXPERIMENT NO. 9 OBJECTIVE: - To verify excitation tables 0! various flip flops. OUTCOME:- Should be able to understand various flip flops . s APPARATUS REQUIRED: - Digital Trainer Kit, ICs, (7400, 7404, 7410) & Connecting wire. THEORY: - A Flip flop is a bistable electronic circuit that has two stable state, That is , its output is either +5V(logic 1) or OV(logic 0) .A Flip Flop can be referred as memory device since its output will remain unchanged until its input is not changed. It is used to store one binary digit. RS- FLIP FLOP:- A R-S Flip Flop is one that has two inputs R & S and two outputs Q & Q. An R-S Flip Flop can be constructed using NOR gates or NAND gates. Figure shows R-S Flip Flop constructed using four NAND gates. CIRCUIT DIAGRAM:- ‘ [— S [Oo Da SO R-S FLIP-FLOPTRUTH TABLE [ CLK s R Q (tH) 0 x x NO CHANGE 1 0 0 NO CHANGE 1 0 1 or 1 1 0 1 1 1 1 FORBIDDEN D- FLIP FLOP: - To avoid the forbidden case that occur in R-S Flip Flop, when R=S=I,D Flip Flop is implemented. In the D Flip Flop, there is only one input D as show in figure .We can transmit the value of D at the output of the Flip Flop when CLK is high. CIRCUIT DIAGRAM (> Ds = OBSERVATION TABLE - D FLIP -FLOP D Qgtt) x NO CHANGE < 1 0 [ 0 =© eeceeecevevve joe Lo bdo ebos LK FLIP FLOP; - Setting R=S=1 with a R-S Flip Flop Q and Q’ will set to the same logic level. This is an illegal conditions .The J-K Flip Flop accounts for this illegal input. It is used to build counter, The values of J and K determine what a J-K Flip Flop does on the next clock edge. When both are low, the Flip Flop retains its last state. When J is low and K is high, the Flip Flop resets. When J is high and K is low, the Flip Flop sets. When both are high the Flip flop toggles. In this last mode, the J-K Flip Flop can be used as a frequency divider. PIN CONFIGURATION OF 7410:- f14] [13] fra) fio) fh 2] fel EES > [Fete trsecngut wane one ; ; - 17 eIGIGIGI te CIRCUIT DIAGRAM:- a cLK re a OBSERVATION TABLE:- J.K - FLIP-FLOP {LK J K Q (tH) 0 x x NO CHANGE 1 0 . NO CHANGE 1 0 | 0 1 I 0 1 I> EL FLOP: - The T- Flip Flop is known as Toggle Flip flop. The T Flip flop is 4 ‘ification of the JK Flip flop by connecting both inputs J and K together. Figure e logic diagram of T flip flop ,logic symbol and truth table of T Flip flop is When T=0, both AND gates are disabled and hence there is nO change in put. When T=1(J=K=1) output toggles. ‘Toggles means that the output the previous state is 1 otherwise output is 1 when the previous st ment of the previous output. m0! shows th shown. revious oul 4ls0 tate is 0. So <0 when ie output is @ comple Circuit Diagram a e@ oe o {| OBSERVATION TABLE:- T - FLIP -FLOP | Preset State Flip flop Input. Next State [Qn T 0 fo 0 et I ey 0 a I PROCEDURE 1, Make the connections as shown in the figure. 2. Connect Pin No-7 to GND. 3. Connect Pin No-14 to Vee.RESULT: ~ The observation tables of various flip-flops are verified. pRECAUTIONS:- * 1) All Connections s 2) All Connections should be right and tight. 3) Reading should be taken carefully. ch off Power supply after completing the Expe should be according to circuit diagram. 4) Swit riment.OBJECTIVE: Design of a 4-bit Arithmetic Logic Unit. QUTCOM) j) To understand the working of the ALU. i) To study and to implement the ALU APPARATUS REC QUIRED: IC 74181 LEDs Power Supply, CRO, Multimeter THEORY: ‘ALU stands for the arithmetic and logical unit and is one of the important unit in almost all the calculating machine these days be it with the hand-held mobile, or computers. All the computational work in the system are carried out by this unit. The typical ALU sizes are : 4-bit ALU : ALU that processes two 4-bit numbers. 8-bit ALU : ALU that processes two 8-bit numbers. Still in the latest systems ALU sizes are 16, 32, 64-bit etc. Figure-1 shows the block diagram of a typical ALUOutput | Arithmetic Unit. |-—/—&> Mode Bit | Decoder a Logical Unit = |—4—p- + 4 Output Function Select Figure-1: Block Diagram of ALU 1x2 | In figure-1, the 1x2 selector on the left is as a mode selector to select one of the two units ie. either the arithmetic unit or the logical unit. The function select lines are then used to select one of the many functions of arithmetic or the logical type. MSI package for ALU:- IC 74181 a 4-bit Arithmetic and logical unit: AL 81 AZ B2 AB 26 20 3 G Cned P AeB FS 18wweewr~e ~ + Ay BO B AzB S@€@ we ews es = x ait we a y Fy Is Internal Architecture of ALU IC 74181 Cheaeee ee ee puNCTION TABLE OF ALU 74181: rhe function table of IC 74181 ALU is given in figure-- Meced depending on the Biven in figure-S. It shows the functions Cn i ad 83-80 lines. , M=1 Mx=0 M e934? CIN=1 _CIN™0 4 A+1 0 ° ' ° AIR AIB +1 e Al 0 Oo tt ae Aue ° i 0 : A+ AB A+AB41 ° o (A)B) + AB (A1B) + AB +1 o 1 2 0 Bae oO 1 1 1 AB-1 “n 1 0 0 0} FB A+AB A+AB41 1 oO 0 1 DB A+B eae ae (AB) + AB (AjB)+ AB+1 1 o 1 1 B AB-1 ae ' roe 2eA 2eA+l eee tc (AB)+ A (ALB) + ASD Tot 1 0] AB (AB)+ A (AIB)+ A+) ror obo Ant ba IMPLEMENTATION: LEDs are connected at the input A and B lines and the select lines to indicate the value of the inputs A and B. The LEDs at the select lines are used to specify the function of the ALU. The LEDs at the output are used to test and verify the output. ‘The whole implementation is shown in figure isPRECAUTION : i) Keep the datasheet of IC 74181 ready. ii) Insert the IC on the Breadboard. iii) Make connections as shown in figure-6 iv) Verify the connections VERIFICATION: The above circuit when connected to power supply gives correct result as per the function table.