t i

ko
CHAPTER Four

rla
Bu
Microprocessor system

j
ro
Su
ith
W BY
Suroj Burlakoti
Lecturer
n
ar

DoECE, National College of Engineering

Le
Pin Configuration of 8085 Microprocessor

t i
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 2
Pin Configuration of 8085

i
t
ko
Microprocessor

rla
Bu
1. Power supply and clock signals

j
2. Address bus

ro
3. Data bus

Su
4. Control and status signals
5. Interrupts and externally initiated signals

ith
6. Serial I/O ports W
n
ar
Le

#Burlas 3
1.Power supply and Clock

i
frequency signals

t
ko
rla
• Vcc : + 5 volt power supply

Bu
• Vss : Ground
• X1, X2 : Crystal or R/C network or LC network

j
ro
connections to set the frequency of internal clock
generator.

Su
• The frequency is internally divided by two. Since the

ith
basic operating timing frequency is 3 MHz, a 6 MHz
crystal is connected externally.
W
• CLK (output)-Clock Output is used as the system
clock for peripheral and devices interfaced with the
n
microprocessor.
ar
Le

#Burlas 4
 i
2. Address Bus

t
ko
rla
• A8 - A15 (Higher byte of address)

Bu
• It carries the most significant 8 bits of the
memory address or the 8 bits of the I/O

j
ro
address.

Su
ith
W
n
ar
Le

#Burlas 5
 i
3. Multiplexed Address / Data Bus:

t
ko
rla
• AD0 - AD7 (8 bit data or lower byte of address)

Bu
• These multiplexed set of lines used to carry the
lower order 8 bit address as well as data bus.

j
ro
• During the opcode fetch operation, in the first clock
cycle, the lines deliver the lower order address A0 -

Su
A7.
• In the subsequent IO / memory, read / write clock

ith
cycle the lines are used as data bus.
W
• The CPU may read or write out data through these
lines.
n
ar
Le

#Burlas 6
4. Control and Status signals:

t i
ko
• These signals include two control signals (RD & WR)

rla
three status signals (IO/M, S1 and So) to identify the
nature of the operation and one special signal (ALE) to

Bu
indicate the beginning of the operations.
• ALE (output) - Address Latch Enable.
• This signal helps to capture the lower order address presented

j
on the multiplexed

ro
address / data bus. When it is the pulse, 8085 begins an
operation. It generates

Su
AD0 - AD7 as the separate set of address lines A0 –A7.
• 𝑹𝑫 (active low) - Read memory or IO device.

ith
• This indicates that the selected memory location or I/O device is
to be read and
that the data bus is ready for accepting data from the memory
W
or I/O device.
• 𝑾𝑹 (active low) - Write memory or IO device.
n
• This indicates that the data on the data bus is to be written into
ar

the selected
memory location or I/O device.
Le

#Burlas 7
4. Control and Status signals:

i t
ko
rla
• IO/𝑴 (output) - Select memory or an IO device.

Bu
• This status signal indicates that the read / write
operation relates to whether the memory or I/O
device.

j
ro
• It goes high to indicate an I/O operation.

Su
• It goes low for memory operations.
• So, S1 (Status Signals):

ith
• It is used to know the type of current operation of
W
the microprocessor.
n
ar
Le

#Burlas 8
4. Control and Status signals:

t i
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 9
5. Interrupts and Externally

t i
initiated operations:

ko
rla
• They are the signals initiated by an external device to request
the microprocessor to do a

Bu
particular task or work.
• There are five hardware interrupts called,
•

j
TRAP

ro
• RST 7.5
• RST 6.5

Su
• RST 5.5
• INTR

ith
• 𝑰𝑵𝑻𝑨 (active low output)
• On receipt of an interrupt, the microprocessor acknowledges
W
the interrupt by the active low 𝑰𝑵𝑻𝑨 (Interrupt
Acknowledge) signal.
• Hold (Input)
n
• This indicates peripheral controller requesting the bus.
ar

• HLDA (Output)
Le

• This indicates the acknowledgement for the Hold request.

#Burlas 10
5. Interrupts and Externally

t i
initiated operations:

ko
rla
• READY (Input)
• It is used to delay the microprocessor read and write cycles until a

Bu
slow responding peripheral is ready to send or accept data.
• Memory and I/O devices will have slower response compared to
microprocessors.

j
• Before completing the present job such a slow peripheral may not

ro
be able to handle further data or control signal from CPU.
• The processor sets the READY signal after completing the present

Su
job to access the data.
• The microprocessor enters into WAIT state while the READY pin is
disabled.

ith
• 𝑹𝑬𝑺𝑬𝑻 𝑰𝑵 (input, active low)
• This signal is used to reset the microprocessor.
W
• The program counter inside the microprocessor is set to zero.
• The buses are tri-stated.
n
• RESET OUT(Output)
ar

• It indicates CPU is being reset.

Le

• Used to reset all the connected devices when the microprocessor

is reset. #Burlas 11
5. Single Bit Serial I/O ports

t i
ko
rla
• SID (input) - Serial input data line

Bu
• SOD (output) - Serial output data line
• These signals are used for serial communication.

j
ro
Su
ith
W
n
ar
Le

#Burlas 12
Bus Structure (Synchronous & Asynchronous)

t i
ko
1. Synchronous Bus

rla
• Each event on the bus is directly controlled by clock
• Clock transmits a regular sequence of 0’s & 1’s of equal duration

Bu
• All the events start at beginning of the clock cycle
• In synchronous read operation, processor

j
ro
issues START signal, memory read signal and
place the address on the address bus at the first

Su
clock pulse
• The addressed memory module recognizes the

ith
address and after a delay of one clock cycle it
places the data and acknowledgment signal on
W
the buses.
• In synchronous bus, all devices are tied to a
fixed rate, and hence the system can not take
n

advantage of device performance but it is easy

ar

to implement.
Le

#Burlas 13
 i
Bus Structure

t
ko
rla
2. Asynchronous Bus

Bu
• The timing is maintained in such way that
occurrence of one event on the bus follows and
depends on the previous event.

j
ro
• Here the CPU places Memory Read (Control)

Su
and address signals on the bus.
• Then it issues master synchronous signal

ith
(MSYNC) to indicate the presence of valid
address and control signals on the bus.
W
• The addressed memory module responds with
n
the data and the slave synchronous signal
ar

(SSYNC)
Le

#Burlas 14
Read and Write Bus Timing of 8085 Microprocessors

t i
ko
• Machine cycle:

rla
• The time required to complete one operation of accessing memory, I/O or acknowledge an
external request (3-6 T-states)

Bu
• Opcode Fetch
• Memory Read/Write
• I/O Read/write

j
• Request Acknowledgement

ro
• Here Op-Code fetch is an internal operation and other three are external operations.

Su
• During three operations, microprocessor generates and receives different signals. These all
operations are terms as machine cycle.

ith
• Clock cycle (T state):
• It is defined as one subdivision of the operation performed in one clock period
W
• Instruction cycle:
n
• It is defined as the time required completing the execution of an instruction. The 8085
ar

instruction cycle consists of one to six machine cycles or one to six operations.
Le

#Burlas 15
 i
Opcode Fetch Machine Cycle

t
ko
rla
• The first operation in

Bu
any instruction is Op-
Code fetch, The

j
microprocessor

ro
needs to get(fetch)

Su
this machine code
from the memory

ith
register where it is
stored before the W
microprocessor can
begin to execute the
n

instruction.
ar
Le

#Burlas 16
 i
Opcode Fetch Machine Cycle

t
ko
rla
Address Mnemonics Opcode
8000 MOV A,B 78

Bu
• E.g.
Step1: Microprocessor places the 16 bit
memory address from Program Counter

j
on the address bus. At T1, high order 80 (Higher Order Address)

ro
address (80) is placed at A15-A8 and
lower order address (00) is placed at AD7-

Su
AD0, ALE signal goes high. IO/M goes low 00 (LOA) 78 (Opcode)
and both S0 and S1 goes high for Op-Code
fetch.

ith
Step 2: The control unit sends the control
signal RD to enable the memory chip and
active during T2 and T3.
W
Step 3: The byte from the memory
location is placed on the data bus .that is
n
78 into D0-D7 and RD goes high
impedance.
ar

Step4: The instruction 78H is decoded

Le

and content of register B will be copied

into accumulator during clock cycle T4. #Burlas 17
 Memory Read Machine Cycle

t i
ko
Address Mnemonics Opcode

rla
8000 MVI A,55H 3E

Bu
8001 55
80 (higher order Address)

j
Step 1 : First machine cycle (Op-Code fetch)

ro
is identical for timing diagram of Op-Code
fetch cycle. 01(LOA) 55H (Data)

Su
Step 2:
• After completion of Op-Code fetch cycle,
8085 places the address 8001 on the

ith
address bus.
• ALE is asserted high, IO/ 𝑀 =0, S1=1, S0=0
W
for memory read
cycle.
• When RD =0, memory places the data
n
byte 55H on the dada bus.
ar
Le

#Burlas 18
Memory Write Machine Cycle

t i
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 19
 i
I/O Read Machine Cycle

t
ko
rla
• The I/O Read cycle is

Bu
executed by the processor to
read a data byte from I/O
port or from the peripheral,

j
ro
which is I/O, mapped in the

Su
system.
• The processor takes 3T states

ith
to execute this machine cycle.
• The IN instruction uses this
W
machine cycle during the
execution.
n
ar
Le

#Burlas 20
 i
I/O Write Machine Cycle

t
ko
rla
Bu
Address Mnemonics Opcode

j
8000 OUT 40 D3

ro
40(Port Address)
8001 40

Su
40(PA)

ith
W
n
ar
Le

#Burlas 21
 i
I/O Write Machine Cycle

t
ko
rla
Step 1:

Bu
In Machine Cycle M1, the microprocessor sends RD control signal which is
combined with IO/ 𝑀 to generate the MEMR signal and processor fetches
instruction code D3 using the data bus.

j
ro
Step 2:

Su
In 2nd Machine Cycle M2, the 8085 microprocessor places the next address
2081 on the address bus and gets the device address 40H via data bus.

ith
Step 3:
In machine Cycle M3, the 8085 places device address 01H on low order as
W
well as high order address bus. IO/ 𝑀 goes high for IO and accumulator
content are placed on Data bus which are to be written into the selected
n
output port
ar
Le

#Burlas 22
 t i
Timing Diagram for MOV A,B

ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 23
 MVI A,32

Le
ar
n
W
ith
#Burlas
Su
ro
j Bu
rla
ko
t i
24
 Address Mnemonics Opcode
8000 STA 9050 32

t i
8001 50
Timing diagram for STA

ko
8002 90

rla
9050 FF

j Bu
ro
80 80 80 90

Su
00 32 01 50 02 90 50 FF(Data)

ith
W
n
ar
Le

IO/ 𝑀= 0, S1=1,S0=1 0, 0, 1 0, 0, 1 0, 1, 0
#Burlas 25
 i
Assignment: Draw timing diagrams for:

t
ko
rla
• MOV

Bu
• MVI
• LXI

j
•

ro
LDA, STA
• LHLD,SHLD

Su
• INR,DCR
• LDAX, STAX

ith
• ADD,SUB W
• CALL
• RET
n

•
ar

Etc.
Le

#Burlas 26
 i
Memory Device Classification and Hierarchy

t
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 27
 i
Classification of Memory

t
ko
rla
j Bu
ro
Processor Memory
(Registers, Cache)

Su
ith
W
n
ar
Le

#Burlas 28
 i
1. Processor Memory

t
ko
rla
• Includes set of microprocessor registers that holds the temporary

Bu
results during computation and their speed matched to the speed of
processor.

j
ro
• Although the registers are very fast, the cost involved forces to

Su
include only few registers inside the processor
• So separate memory cache is used to give most frequently used

ith
information W
• The processor is then instructed to access the fast memory which
improved the execution speed significantly
n
ar
Le

#Burlas 29
 i
2. Primary Memory

t
ko
rla
• It is the memory used by microprocessor to execute programs.

Bu
• The microprocessor can access only those items that are stored in this
memory.

j
ro
• Hence, all data and program must be within primary memory prior to

Su
its execution.
• Primary memory is much larger than processer memory that is

ith
included in the microprocessor chip.
• Primary memory is divided in to two groups.
W
A. R/W Memory (RAM )
n
B. Read Only Memory (ROM)
ar
Le

#Burlas 30
 i
A. R/W Memory (RAM)

t
ko
rla
• Microprocessor can read for and write into this memory .

Bu
• This memory is used for information that are likely to be altered such
as writing program or receiving data.

j
ro
• This memory is volatile i.e. the content will be lost if the power is

Su
turned off and commonly known as RAM,

ith
• RAM are basically of two types.
i. Static RAM (SRAM)
W
ii. Dynamic RAM (DRAM)
n
ar
Le

#Burlas 31
 i
A. R/W Memory (RAM)

t
ko
rla
i. Static RAM (SRAM)

Bu
• This memory is made up of flip flops and it stores bit as voltage.

j
• A single flip flop stores binary data either 1 or 0.

ro
• Each flip flop is called storage cell.

Su
• Each cell requires six transistors.

ith
• Therefore, the memory chip has low density but high speed.
W
• This memory is more expensive and consumes more power.
n
ar
Le

#Burlas 32
 i
A. R/W Memory (RAM)

t
ko
rla
ii. Dynamic RAM (DRAM)

Bu
• This memory is made up of MOS transistor gates and it stores the bit
as charge.

j
ro
• The advantage of DRAM are it has high density, low power

Su
consumption and cheaper than SRAM.
• But the bit information leaks therefore needs to be rewritten again

ith
every few milliseconds.
• It is called refreshing the memory and requires extra circuitry to do
W
this.
n

• It is slower than SRAM.

ar
Le

#Burlas 33
 i
B. Read Only Memory (ROM)

t
ko
rla
• ROM contains a permanent pattern of data that cannot be changed.

Bu
• It is non volatile that is no power source is required to maintain the
bit values in memory.

j
ro
• ROM are basically of 5 types.

Su
• Masked ROM
• Programmable ROM (PROM)

ith
• Erasable PROM (EPROM)
W
• Electrically Erasable PROM(EEPROM)
• Flash Memory
n
ar
Le

#Burlas 34
 i
B. Read Only Memory (ROM)

t
ko
rla
i. Masked ROM:

Bu
• A bit pattern is permanently recorded by the manufactures during production.
ii. Programmable ROM:
• In this ROM, a bit pattern may be written into only once and the writing process is performed

j
ro
electrically.
• That may be performed by a supplier or customer.

Su
iii. Erasable PROM (EPROM):
• This memory stores a bit in the form of charge by using EPROM programmer which

ith
applies high voltage to charge the gate
• Information can be erased by exposing ultra violet radiation.
• It is reusable.
W
• The disadvantages are:
(i) it must be taken out off circuit to erase it
n
(ii)The entire chip must be erased
ar

(iii) the erasing process takes 15 to 20 minutes.

Le

#Burlas 35
 i
B. Read Only Memory (ROM)

t
ko
rla
iv. Electrically Erasable PROM(EEPROM):

Bu
• It is functionally same as EPROM except that information can be altered by
using

j
ro
electrical signal at the register level rather than erasing all the information.
• It is expensive compared to EPROM and flash and can be erased in 10 ms.

Su
v. Flash Memory:

ith
• It is variation of EPROM. The difference is that EPROM can be erased in
register level but flash memory must be erased in its entirety or at block level.
W
n
ar
Le

#Burlas 36
 i
3. Secondary Memory

t
ko
rla
• The device that provides backup storage are called secondary

Bu
memory
• They are auxiliary devices that stores large data, files and huge

j
ro
programs that are not needed by the processor frequently

Su
• Semi random (e.g. HD, DVD)

ith
• Sequential (e.g. Magnetic tapes)
W
n
ar
Le

#Burlas 37
 i
SSD

t
ko
rla
• Solid State Drive

Bu
• A storage device containing non volatile flash memory, used in place
of a hard disk because of its much greater speed

j
ro
Su
ith
W
n
ar
Le

#Burlas 38
 i
Performance of memory

t
ko
rla
1. Access time (ta):

Bu
• Read access time: It is the average time required to read the unit of
information from memory.

j
ro
• Write access time: It is the average time required to write the unit of

Su
information on memory.

ith
• The time delay between address placed on the address bus and valid
data present on the data bus
W
• Access rate (ra) = 1/ta
n
ar
Le

#Burlas 39
 i
Performance of memory

t
ko
rla
2. Cycle time (tc):

Bu
• It is the average time that lapses between two successive read or write
operation .

j
• Cycle rate (rc)= bandwidth = 1/tc

ro
Su
ith
W
n
ar
Le

#Burlas 40
 i
Access modes of memory:

t
ko
rla
It is the manner in which information can be accessed from the memory

Bu
I. Random access:
• Any location can be accessed randomly, the ta is independent of the location from

j
which the data is accessed. E.g. RAM, ROM

ro
II. Sequential access:

Su
• The memory is accessed in a sequential manner
• The ta is dependent of the location form which the data is accessed. E.g. magnetic

ith
type.
III. Semi random-access:
W
• Combines both sequential and random. E.g. In magnetic disk
n
• Memory location block can be accessed at random but within that block further
ar

access in location is sequential

Le

#Burlas 41
 i
Memory Hierarchy

t
ko
rla
• Capacity, cost and speed of different types of memory play a vital role while

Bu
designing a memory system for computers.
• If the memory has larger capacity, more application will get space to run
smoothly.

j
ro
• It's better to have fastest memory as far as possible to achieve a greater
performance.

Su
Moreover for the practical system, the cost should be reasonable.
• There is a tradeoff between these three characteristics cost, capacity and access

ith
time. One cannot achieve all these quantities in same memory module because
• If capacity increases, access time increases (slower) and due to which cost per bit decreases.
W
• If access time decreases (faster), capacity decreases and due to which cost per bit increases.
• The designer tries to increase capacity because cost per bit decreases and the more
application program can be accommodated. But at the same time, access time increases
n
and hence decreases the performance.
ar
Le

#Burlas 42
 i
Memory Hierarchy

t
ko
rla
• So the best idea will be to use memory hierarchy.

Bu
• Memory Hierarchy is to obtain the highest possible access speed while
minimizing the total cost of the memory system.

j
• Not all accumulated information is needed by the CPU at the same time.

ro
• Therefore, it is more economical to use low-cost storage devices to serve as

Su
a backup for storing the information that is not currently used by CPU
• The memory unit that directly communicate with CPU is called the main

ith
memory
• Devices that provide backup storage are called auxiliary memory
W
• The memory hierarchy system consists of all storage devices employed in a
computer system from the slow by high-capacity auxiliary memory to a
n
ar

relatively faster main memory, to an even smaller and faster cache memory
Le

#Burlas 43
 i
Memory Hierarchy

t
ko
rla
• The main memory occupies a central position by being able to communicate

Bu
directly with the CPU and with auxiliary memory devices through an I/O
processor
• A special very-high-speed memory called cache is used to increase the speed of

j
ro
processing by making current programs and data available to the CPU at a rapid
rate

Su
• CPU logic is usually faster than main memory access time, with the result that
processing speed is limited primarily by the speed of main memory

ith
• The cache is used for storing segments of programs currently being executed in
the CPU and temporary data frequently needed in the present calculations
W
• The memory hierarchy system consists of all storage devices employed in a
computer system from slow but high capacity auxiliary memory to a relatively
n
faster cache memory accessible to high speed processing logic. The figure below
ar

illustrates memory hierarchy.

Le

#Burlas 44
 i
Memory Hierarchy

t
ko
rla
Bu
Cost (decrease)
Access time (increase)

j
Size (increase)

ro
Su
ith
W
n
ar
Le

#Burlas 45
 i
Memory Hierarchy

t
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 46
 i
Memory Hierarchy

t
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 47
 i
Address Decoding

t
ko
rla
• A microprocessor system consist of a microprocessor, Memory, I/O devices that

Bu
are interconnected through common address and data bus
• only one devices can transmit the data through the bus at a time to avoid

j
multiple attempts from other devices cause ambiguous transmission

ro
• So address decoding is used to insure the proper devices get addressed at proper

Su
time
• All devices like I/O, memory are assigned a specific address

ith
• The address of each device is selected by using the address line from the
processor to derive a special device selection signal called chip-select signal (𝐶𝑆)
W
• If the microprocessor has to write or to read from a device, the 𝐶𝑆 signal to that
n
block should be enabled and the address decoding circuit must ensure that 𝐶𝑆
ar

signal to other devices are not activated.

Le

#Burlas 48
 i
Address Decoding

t
ko
rla
• Depending upon the no. of address lines used to generate chip select

Bu
signal for the device, the address decoding is classified as:
• I/O mapped I/O

j
ro
• Memory mapped I/O

Su
ith
W
n
ar
Le

#Burlas 49
Le
ar
n
W
ith
#Burlas
Su
ro
j Bu
rla
ko
t i
50
 i
Unique and Non-Unique Addressing

t
ko
rla
• If all the address lines on that mapping mode are used for address

Bu
decoding then that decoding is called unique address decoding. It
means all 8-lines in I/O mapped I/O and all 16 lines in memory

j
ro
mapped I/O are used to derive signal. It is expensive and complicated

Su
but fault proof in all cases.
• If all the address lines available on that mode are not used in address

ith
decoding then that decoding is called non unique address decoding.
Though it is cheaper there may be a chance of address conflict.
W
n
ar
Le

#Burlas 51
Le
ar
n
W
ith
#Burlas
Su
ro
j Bu
rla
ko
t i
52
Le
ar
n
W
ith
#Burlas
Su
ro
j Bu
rla
ko
t i
53
 i
Interfacing I/O

t
+5V

ko
rla
• Using NAND gate Data Bus Input lines

Bu
D7
7
D6 Tri-State 6

j
.
• IN 95H Buffer .

ro
.
A7 .
D0 𝐶𝑆

Su
A6 0
A5
A4
95 = 1001 0101 A3

ith
A2
A1
W
A0

IO/𝑀
n
𝑅𝐷
ar
Le

#Burlas 54
 i
Interfacing I/O

t
ko
rla
Output lines
• Using NAND gate Data Bus

Bu
D7 7
D6 6
Latch

j
.
• OUT 42H .

ro
. .
A7 D0 𝐶𝑆 0

Su
A6
A5
A4
42 = 0100 0010 +5V

ith
A3
A2
A1
W
A0

IO/𝑀
n
𝑊𝑅
ar
Le

#Burlas 55
 i
Interfacing I/O

t
Output lines

ko
Data Bus
D7

rla
7
D6 6
Latch
• Using Decoder . .

Bu
. .
D0 𝐶𝑆 0
IO/𝑀

j
A7
• IN F8 +5V

ro
A6 𝑊𝑅 +5V
A5
• OUT F9

Su
A4
A3
𝐸𝑁 111 Data Bus Input lines

ith
A2 110
101 D7
7
F8 = 1111 1000 A1
W 3 to 8 100 D6 Tri-State 6
Decoder 011 .
010 Buffer .
F9 = 1111 1001 A0 001
000
.
.
D0 𝐶𝑆
n
0
ar

IO/𝑀
Le

𝑅𝐷
#Burlas 56
 i
Interfacing Memory

t
ko
• Interfacing Single memory of size 1KB R/W Memory starting from A800H

rla
Size = 1KB = 210 B  no. of address lines = 10

Bu
 So A9-A0 directly connected to memory
A15A14A13A12 A11A10A9A8 A7A6A5A4 A3A2A1A0
𝑅𝐷 𝑊𝑅
Starting Address = A800 = 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Address Lines Data Lines

j
ro
Size (1KB) + 3FF = 11 1111 1111 A9 D7
Final Address = ABFF = 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 A6 MEM D6

Su
. .
1KB
. .
A0 𝐶𝑆 D0

ith
A15
W A14 IO/𝑀
A13
A12
A11
n
A10
ar
Le

#Burlas 57
 i
Interfacing More than One Memory

t
ko
• Interfacing two memory of size 4KB R/W Memory starting from 8000H Consecutively

rla
Size = 4KB = 22. 210 B = 212  no. of address lines = 12 𝑅𝐷 𝑊𝑅
 So A11-A0 directly connected to memory Address Lines Data Lines

Bu
MEM1 A15A14A13A12 A11A10A9A8 A7A6A5A4 A3A2A1A0 A11 D7
Starting Address = 8000 = 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A10 MEM2 D6
Size (4KB) + FFF = 1111 1111 1111 . .

j
4KB

ro
Final Address = 8FFF = 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 . .
A0 𝐶𝑆 D0
MEM2 +1

Su
Starting Address = 9000 = 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 IO/𝑀
Size (4KB) + FFF = 1111 1111 1111
Final Address = 9FFF = 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

ith
𝑅𝐷 𝑊𝑅
W A15
A11 D7
𝐸𝑁 111 A10 MEM1 D6
A14 110
.
101 4KB .
n
3 to 8 100 . .
A13
ar

Decoder 011 A0 𝐶𝑆 D0
010
A12
Le

001
000
#Burlas IO/𝑀 58
• Draw the interfacing circuit using 3:8 decoder (74LS138) needed to connect the following

i
memory units to 8085 microprocessor consecutively starting from memory location

t
A000H.

ko
• 2K*8 ROM Chip
• 2K*8 RAM Chip

rla
• 4K*8 EPROM Chip

Bu
For Size = 2KB = 21. 210 B = 211  no. of address lines = 11
For Size = 4KB = 22. 210 B = 212  no. of address lines = 12

j
ro
ROM A15A14A13A12 A11A10A9A8 A7A6A5A4 A3A2A1A0
Starting Address = A000 = 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Su
Size (2KB) + 7FF = 111 1111 1111
Final Address = A7FF = 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1

ith
RAM +1
Starting Address = A800 = 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
W
Size (2KB) + 7FF = 111 1111 1111
Final Address = AFFF = 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
EPROM +1
n
Starting Address = B000 = 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
ar

Size (4KB) + FFF = 1111 1111 1111

Le

Final Address = BFFF = 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

#Burlas 59
 𝑅𝐷
Address Lines Data Lines

t i
A10 D7

ko
A9 EPROM D6
. .
4KB

rla
. . 𝑅𝐷 𝑊𝑅
A0 𝐶𝑆 D0

Bu
IO/𝑀 A10 D7
A9 RAM D6
. .
A15 2KB
.

j
.

ro
A14 A0 𝐶𝑆 D0

Su
IO/𝑀
𝐸𝑁 111
𝑅𝐷

ith
A13 110
101 A10 D7
3 to 8 100 A9 ROM D6
A12
Decoder 011
W .
010 2KB .
A11 001 . .
000
n
A0 𝐶𝑆 D0
ar
Le

IO/𝑀
#Burlas 60
Le
ar
n
W
ith
#Burlas
Su
ro
j Bu
rla
ko
t i
61
Le
ar
n
W
ith
#Burlas
Su
ro
j Bu
rla
ko
t i
62
 t i
ko
CHAPTER Four

rla
Bu
Microprocessor system

j
ro
Su
ith
W BY
Suroj Burlakoti
Lecturer
n
ar

DoECE, National College of Engineering

Le
 i
Microprocessor System

t
ko
rla
4.5 Parallel Interface

Bu
4.5.1 Modes: Simple, Wait, Single Handshaking and Double Handshaking
4.5.2 Introduction to Programmable Peripheral Interface (PPI)

j
ro
4.6 Serial Interface

Su
4.6.1 Synchronous and Asynchronous Transmission
4.6.2 Serial Interface Standards: RS232, RS423, RS422, USB

ith
4.6.3 Introduction to USART
4.7 Introduction to Direct Memory Access (DMA) and DMA Controllers
W
n
ar
Le

#Burlas 2
 i
Serial and Parallel Interfacing

t
ko
rla
• Serial Interface

Bu
• Data are transferred serially one bit at a time starting from Least Significant
bit.

j
ro
• Slow due to single communication link but inexpensive to implement.

Su
• It uses clock to separate consecutive bits
• Its function is to deal with the data on the bus in the parallel mode and

ith
communicate with the connected device in serial mode.
• Its data bus has n data lines, the serial I/O interface accepts n bit of data
W
simultaneously from the bus and n bits are sent one at a time thus requiring n
time slots.
n

• Not suitable for fast operation needed microprocessor

ar
Le

#Burlas 3
 i
Serial and Parallel Interfacing

t
ko
rla
• Parallel Interface

Bu
• The device which can handle data at higher speed cannot support with serial
interface.

j
ro
• N bits of data are handled simultaneously by the bus and the links to the
device directly.

Su
• Achieves faster communication but becomes expensive due to need of
multiple wires.

ith
W
n
ar
Le

#Burlas 4
 i
Serial and Parallel Interfacing

t
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 5
 i
Parallel Interface

t
ko
rla
• Parallel Data Transfer

Bu
• Multiple bits at a time
• Fast data transfer

j
ro
• Requires large no. of lines

Su
• Costly

ith
W
n
ar
Le

#Burlas 6
 i
Methods of Parallel Data Transfer

t
ko
rla
a. Simple I/O

Bu
b. Simple strobe I/O

j
c. Single handshaking

ro
Su
d. Double handshaking

ith
W
n
ar
Le

#Burlas 7
 i
Simple I/O

t
ko
rla
• The receiving devices are always assumed to be ready

Bu
• The data is transfer by simple connecting input and output to the
respective ports

j
ro
• E.g. LED, Switch

Su
Valid Data

ith
W
n
ar
Le

#Burlas 8
 i
Simple strobe I/O

t
ko
rla
• Wait Interface

Bu
• The valid data presents on a data bus should be read within time
when its validity is indicated by strobe signal

j
ro
• E.g. keyboard, tri-state A/D converter

Su
ith
W Valid Data
n
ar
Le

#Burlas 9
 i
Single Handshaking

t
ko
rla
• Here the receiving devices confirms the

Bu
receipt of data
• The sending devices sends the data in data

j
bus and also the strobe (𝑆𝑇𝐵) signal

ro
• Receiving device reads the data after

Su
detecting the 𝑆𝑇𝐵 signal and sends the
Acknowledge (ACK) signal to sending Valid Data

ith
device to indicates that data has been read
and the peripheral can send next byte of
W
data
• E.g. Printer
n
ar
Le

#Burlas 10
 i
Double Handshaking

t
ko
rla
• Bidirectional handshaking

Bu
• Here, the sending device sends 𝑆𝑇𝐵 signal
to ask if the receiving device is ready

j
ro
• The receiving device raises its ACK signal

Su
to say it is ready
• The sending device then sends the data Valid Data

ith
and raises its strobe line high
• After reading the data, the receiving
W
system drops its ACK line and request to
n
send next byte of data
ar
Le

#Burlas 11
 i
Programmable Peripheral Interface

t
ko
rla
Data
• Using processor to generate or I/O

Bu
monitor strobe and acknowledge MP Devices
𝑆𝑇𝐵
signal for handshake or transfer ACK
data takes too much processor

j
time

ro
• So parallel port devices such as

Su
8255A called general purposed Data Data
programmable peripheral I/P

ith
interface are used to manage the 𝑆𝑇𝐵 Devices
handshaking operation
W Micro- INTR ACK
PPI
• 8255A can be programmed to processor
transfer data under various Data
n
condition from simple I/O to O/P
ar

handshake I/O 𝑆𝑇𝐵 Devices

ACK
Le

#Burlas 12
 i
8255A PPI Pin Description

t
ko
rla
• 8255A IC has 40 pins
• 24 I/O Pins D7 PA7

Bu
• Port A (8 bit) | |
• Port B (8 bit) D0 PA0
• Port C (8 bit or two 4 bit)

j
• 8 bit data lines (D7-D0)

ro
A1 PB7
• 6 Control Pins A0 |

Su
• 𝑅𝐷 signal indicates MPU reads data from 8255A PB0
selected port
𝑅𝐷
• 𝑊𝑅 signal indicates MPU writes data to

ith
selected port 𝑊𝑅 PC7
• RESET – initializes all ports as input and 8255A
W RESET |
resets VCC PC0
• 𝐶𝑆 is device select signal connected to address GND
decoding circuit
𝐶𝑆
n
• A1, A0 are connected to address line A1, A0 of
ar

processor
• 2 Power Supply Pins VCC and Ground (GND)
Le

#Burlas 13
 i
8255A PPI Pin Description

t
ko
rla
D7 PA7

Bu
| |
D0 PA0
𝐶𝑆 A1 A0 Port Selected

j
PB7

ro
0 0 0 Port A A1
A0 |
0 0 1 Port B

Su
8255A PB0
0 1 0 Port C 𝑅𝐷
0 1 1 Control Register 𝑊𝑅 PC7

ith
RESET |
1 x x 8255A Disable PC0
W VCC
GND
𝐶𝑆
n
ar
Le

#Burlas 14
 i
8255A internal bock diagram

t
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 15
 i
8255A PPI

t
ko
rla
• 8255A Operational Modes

Bu
1. Mode 0
• I/O ports works as simple I/O ports

j
ro
2. Mode 1
• Single handshaking mode

Su
• Port A or/and B can be initialized in mode 1 and works as input or output
• Some pins of port C is used to transfer handshaking signal

ith
3. Mode 2 W
• Bidirectional handshaking
• Port A can be used for bidirectional data transfer using handshaking signals from port
n
C
ar

• In this case port B can be set in either mode 0 or mode 1

Le

#Burlas 16
 i
Serial Interface

t
ko
rla
• Serial data transfer

Bu
• Bit by bit data transfer
• Requires less no. of wires

j
ro
• Economical

Su
• Slow
• Suitable for long distance

ith
• Synchronous and Asynchronous serial data transmission
W
n
ar
Le

#Burlas 17
 i
1. Synchronous Data Transmission

t
ko
• Transmitter (TX) and Receiver (RX) are first synchronized and then large

rla
blocks of data are sent one after another

Bu
• Some of Sync characters are sent at the start of each synchronous data
stream

j
ro
• RX uses the Sync characters to synchronize its internal clock with that of TX

Su
• Used for high speed transmission (>20Kbit/sec)
• Implementation in hardware

ith
W CLK@TX/RX
n
ar
Le

#Burlas 18
 i
1. Synchronous Data Transmission

t
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 19
 i
2. Asynchronous Data Transmission

t
ko
rla
• TX and RX are not synchronized
•

Bu
However TX and RX agreed upon a data rate before transmission
• When no data is being sent, signal line is at HIGH or Marking State
• The beginning of data is indicated by line going down LOW of one bit, called start bit

j
ro
• Then data bits are sent one after another, generally LSB is transmitted first

Su
• After data and parity bits are transmitted one are two stop bits (HIGH) are used before
next transmission

ith
W
n
ar
Le

#Burlas 20
 i
2. Asynchronous Data Transmission

t
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 21
 i
Bit Rate and Baud Rate

t
ko
rla
• Bit Rate: How many bits can be

Bu
sent per unit time or second
(bit/sec)
• Baud: How many times a signal

j
ro
changes per second (baud/sec)

Su
• Bit rate is controlled by baud
and number of signal levels

ith
• Bit rate (bit/sec)= Baud Rate
(signal/sec) * no. of bits per
W
signal (bit/signal)
n
• B=S*n
ar
Le

#Burlas 22
 i
Serial Interface Standards

t
ko
rla
• RS-232

Bu
• RS-423

j
• RS-422

ro
• USB

Su
ith
W
n
ar
Le

#Burlas 23
 i
RS-232C

t
ko
rla
• Developed in early 1960s by Electronic Industries Association (EIA)

Bu
• To ensure connections between equipment of different manufacturers
• To enable reliable communication

j
ro
• TIA232F was developed to standardize the interface between DTE and DCE
by Telecom Industry Association in 1997

Su
• RS232 defines signal voltage level, signal function, signal timing, protocols
(format) for information exchange and specification for connectors

ith
W
DTE = Data Terminal Equipment (Computer)
n
DTE DCE
DCE = Data Communication Equipment (Modem)
ar
Le

#Burlas 24
 i
RS-232C

t
ko
rla
• Signal Voltage Level

Bu
• For data signal:
• Logic 0: +3V to +25V

j
ro
• Logic 1: -3V to -25V
• Range between -3V to +3V  Undefined or invalid

Su
• For Control Signal
• opposite polarity to that of data signal

ith
W
n
ar
Le

#Burlas 25
 i
RS-232C

t
ko
rla
• Connector

Bu
• DTE has 25 pin DB-25 Male (Pin) connector
• DCE has 25 pin DB-25 Female (Socket) connector

j
ro
• Generally DE-9 (DB-9) connector is used if full functioning of RS232 is not

Su
required

ith
W
Fig: DB-25 Male (Pin) and DB-25 Female (Socket)
n
ar
Le

DB9
#Burlas 26
 i
RS-232 Signals

t
ko
rla
Direction (Flow)

Bu
Pin Number for DB-25 Pin Number for DB-9 Signal Description

2 3 TxD DTE to DCE Transmitted data

j
3 2 RxD DCE to DTE Received Data

ro
4 7 𝑅𝑇𝑆 DTE to DCE Request to Send

Su
5 8 𝐶𝑇𝑆 DCE to DTE Clear to Send
6 6 𝐷𝑆𝑅 DCE to DTE Data Set Ready

ith
7 W5 GND Common Ground Signal ground
8 1 𝐶𝐷 DCE to DTE Carrier Detect
20 4 𝐷𝑇𝑅 DTE to DCE Data Terminal Ready
n
22 9 RI DCE to DTE Ring Indicator
ar
Le

#Burlas 27
 i
RS-232 Signals

t
ko
rla
• After DTE is turned on, the terminal asserts 𝐷𝑇𝑅 signal to tell the modem (DCE)

Bu
that it is ready
• DCE (modem) will assert 𝐷𝑆𝑅 signal to DTE (computer) if it is ready to transmit or
receive data

j
ro
• When DTE has character(s) to send, it will assert 𝑅𝑇𝑆 signal to the DCE

Su
• DCE asserts 𝐶𝐷 signal to indicate it has established connection with the DTE
• When DCE is fully ready, it asserts 𝐶𝑇𝑆 signal

ith
• DTE then sends serial data to the modem through TxD and receive from RxD line
• When all characters are sent, DTE makes 𝑅𝑇𝑆 signal high. This causes modem to
W
unassert its signal and stop transmitting
• RI is asserted if telephone line rings or an external devices call DTE via DCE
n
ar
Le

#Burlas 28
 i
RS-232 Connection

t
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 29
 i
TTL to RS232 Interfacing

t
ko
rla
RS-232C TTL
Logic 0 +3V to +25V (+12V) 0V

Bu
Logic 1 -3V to -25V (-12V) +5V

j
ro
Su
ith
W
n
ar
Le

#Burlas 30
 i
Problems with RS232

t
ko
rla
• Can transmit up to 50 ft. @20KBd

Bu
• Baud rate will be drastically reduced for longer distance because of
the noise due to common ground

j
ro
Su
ith
W
n
ar
Le

#Burlas 31
 i
RS423A

t
ko
rla
• Improvement over RS-232C

Bu
• Uses similar signals as in RS232 but supports one transmitter and up to ten
receivers

j
• Specifies a low impedance single ended signal which can be sent over

ro
coaxial cable and partially terminated at the receiving end to prevent signal

Su
reflection
• Signal Voltage level

ith
• Logic 0: +4V to +6V
• Logic 1: -4V to -6V W
• Transmission rate:
• 100 KBd over 40 ft. line
n
• 1 KBd over 4000 ft. line
ar
Le

#Burlas 32
 i
TTL to RS-423A

t
ko
rla
j Bu
ro
Su
ith
W
n
ar
Le

#Burlas 33
 i
RS-422A

t
ko
rla
• Uses differential signals i.e. each signal is transmitted differentially over

Bu
two adjacent wires in a ribbon cable or twisted pair cable
• Eliminates common ground wire problem

j
• Signal voltage Level

ro
• Logic 0: line a is more positive than line b

Su
• Logic 1: line b is more positive than line a
• Voltage difference between two lines must be greater then 0.4V but less

ith
than 12V
• MC3487 produces a difference of 2V between a and b
W
• Transmission rate:
• 10000 KBd over 40 ft.
n

• 100 kBd over 4000 ft.

ar
Le

#Burlas 34
 RS422A

Le
ar
n
W
ith
#Burlas
Su
ro
j Bu
rla
ko
t i
35
 i
Universal Serial Bus (USB)

t
ko
rla
• It is a specification to establish serial communication between devices and

Bu
peripherals like (mobile, Phone, camera, etc.) and host controller (usually
PC)
• The connection is between master/host (PC) and slave/devices (Keyboard,

j
ro
mouse, printer, etc.)
• Defines cable, connectors and communication protocols used in bus for

Su
connection, communication and power supply between computer and
electronic devices

ith
• Single connector type, Hot-swappable, Plug and Play
W
• High performance, Expandability
• Power supplied from the bus
n

• Easy to use for end user, Low-cost implementation

ar
Le

#Burlas 36
Signals in USB

t i
ko
• Uses four shielded wire

rla
• Two for power supply

Bu
• Two for differential data signals

j
ro
Red

Su
White
Green
Black

ith
W
• Data is transmitted differentially over a twisted pair data lines (D+ and D+)
• Logic 1: D+ > D-
n
ar

• Logic 0: D- > D+
Le

#Burlas 37
 i
USB Standards

t
ko
rla
Bu
USB Version Data Rates Released Year
USB 1.0 Low Speed (1-5 Mbps) 1996

j
USB 1.1 Full Speed (12 Mbps) 1998

ro
USB 2.0 High Speed (480 Mbps) 2000

Su
USB 3.0 Super Speed (4.8 Gbps) 2008

ith
W
n
ar
Le

#Burlas 38
 i
USART

t
ko
rla
• Universal Synchronous Asynchronous Receiver Transmitter
• It is integrated circuit that sends parallel data through a serial line and receives a serial

Bu
bit into a parallel words between microprocessor unit and peripherals synchronized for
serial communication

j
• It is used in conjunction with other standards recommended by EIA

ro
• Intel 8251A is widely used USART

Su
• USART is mostly used in asynchronous mode and communication is full duplex
• USART constitutes a transmitter having a shift registers that loads data in parallel and

ith
then shift it out bit by bit at a specific rate and a receiver which shift in data bit by bit and
then reassembles the data in parallel
W
• Both Tx and Rx should agree upon parameters in advance such as baud rate, no. of data
bits, stop bits, use of parity bits etc.
• USART generally consist of clock generator, input and output shift registers, Transmit and
n

receive buffer, Parallel data bus buffer, Read/Write and Modem control etc.
ar
Le

#Burlas 39
 USART

Le
ar
n
W
ith
#Burlas
Su
ro
j Bu
rla
ko
t i
40
 t i
Direct Memory Access (DMA) & DMA Controller

ko
rla
• DMA is an I/O technique commonly used for high speed data transfer. E.g. data

Bu
transfer between system memory and disk driver controller, graphics cards, DUD
drives, ISA bus etc.
• In DMA the microprocessor releases the control of the buses to the device called

j
ro
DMA controller
• The DMA controller manages data transfer between memory and peripherals

Su
under its control, thus bypassing the MPU.
• The DMA controller basically uses two signals HOLD and HLDA for DMA operation

ith
• HOLD: Active HIGH signal, when the other devices request for the use of address and data
bus W
• HLDA: Active HIGH signal, sent from the processor giving control of its buses to the
requesting devices
• A DMA controller use these signals as if it were a peripheral requesting the MPU
n

for the control of buses (in slave mode)

ar
Le

#Burlas 41
 t i
Direct Memory Access (DMA) & DMA Controller

ko
rla
• The MPU communicates the controller by using Chip select signal buses

Bu
and other control signal lines
• However one the controller has gain control, it plays the roles of the

j
processor for data transfer (master mode)

ro
• To perform these function, DMA controller should have

Su
• Data bus
• Address bus

ith
• Read/Write Control Signal
W
• Control signals to disable its role as slave and to enable its role as master
• The process of changing its role is called switching
n

• Intel 8257 is a commonly used DMA controller specially used in ISA bus
ar
Le

#Burlas 42
 t i
ko
Direct Memory

rla
Access (DMA) &

Bu
DMA Controller

j
ro
Su
ith
W
n
ar
Le

#Burlas 43
Le
ar
n
W
ith
#Burlas
Su
ro
j Bu
rla
ko
t i
44