Intro to Digital Logic, Lab 4

High-Level Verilog

Lab Objectives
Implementing designs directly in schematics or structural (gate-level) Verilog can give you the best
control, and often the smallest designs. But, sometimes it can be a real pain to optimize all the way
down at that level. An alternative is high-level (Register Transfer Level – RTL) Verilog, where you tell the
CAD tools what you what the output to look like, and it automatically does the Boolean algebra for you!

Task #1 – Seven-Segment Displays

In lecture, we presented a seven-segment display driver. RTL code for that seven-segment display is
given below (Figure 1).
1) Create a new project in Quartus Prime and add the code to it.
2) Create a new module that uses two instances of the code – one that uses as
inputs and outputs to , and another that uses as inputs and outputs to .

The seven-segment displays on the DE1 are active low. That means that putting a FALSE on the
wire makes it light up, while a TRUE means that light is off. You will have to adjust your design
accordingly.

Figure 1: Verilog code for a basic seven-segment display driver.

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Task #2 – UPC code to display
In Lab 3, we built a system that took in a UPC and output whether a returned Nordstrom item was on
sale and whether it was stolen. A nearby store, Fred’s Pawn Shop, buys used items from customers that
were originally purchased from various stores that also use the UPC system. Fred wants a similar item-
checking system, but has found that devious customers are changing the UPC stickers on the items they
are selling to misrepresent the price. To combat that, Fred would like you to add a display on
that describes the product corresponding to that UPC – if the description doesn’t match the item,
then someone is trying to cheat Fred!
You already created the logic to output the and signals based on six specific UPC’s
and whether or not the item was marked. To simplify this lab, we will reuse all of that existing logic, but
now add hex display outputs for those six UPC’s. To let you exercise your creativity, you are asked to
come up with new item names.
1) Come up with exactly six new items to fill out the leftmost column of Table 1 – three expensive
items and three inexpensive items. You are not allowed to use any of the items from Lab 3 or
the example given below.
a) Make sure to match each item with a corresponding expensive or inexpensive UPC.
b) Since we only have six 7-segment displays, you should consider what items will lend
themselves to “good” (easily-distinguishable) displays.
2) Determine corresponding 7-segment encodings for your six items. The displays do not need to
use the entire item name, but they need to be at least 3 letters each and easily-distinguishable
from the other UPC descriptions. You may use upper- and lower-case letters or pictograms.
a) Example: The item “Dress Shoe” could be displayed as

There is no “correct” way to encode the entire alphabet on 7-segment displays. You may use
online resources such as http://tinyurl.com/h99785g for inspiration, but you should decide for
yourself whether or not your display is easily read or more of a stretch to interpret correctly.

3) Create a high-level design for the circuit using RTL. It should have three inputs ( , P, and C),
similar to the module, but will instead have six 7-bit outputs for the 7-seg displays.
4) Simulate your design in ModelSim, then hook it to the switches and lights of your board to make
sure it works.
5) Create a new module that uses one instance of your new display code and one instance of your
Lab 3 module. It should use them both so the system simultaneously computes the Sale LED,
Stolen LED, and HEX displays. Test and debug with ModelSim, then load onto your board.

Item Name UPC Discounted? Expensive?

<New Item 1> 0 0 0 No Yes
<New Item 2> 0 0 1 No No
<New Item 3> 0 1 1 Yes No
<New Item 4> 1 0 0 No Yes
<New Item 5> 1 0 1 Yes Yes
<New Item 6> 1 1 0 Yes No
Table 1: List of products being sold as well as their UPCs and shopping classifications.

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 ModelSim Tips to help you organize your signals:
• Signals from multiple modules can be displayed at the same time. Select modules in
the sim tab and then drag-and-drop signals from the Objects pane to the Wave pane.
• To (re-)order signals, you can click and drag names in the Wave pane.
• You can create groups of signals. Highlight multiple signals in the Wave pane, then
right-click on one of the signal names and select “Group.” You can now move the
signals as a group, and hide/expose them easily. Note: you can only group signals
from the same module.
• Don’t forget to save the formatting into the <modulename>_wave.do file!

Task #3 – Don’t Cares

Your design has outputs for only 6 of the 8 possible UPC codes. For the other two cases, a line such as
“ ” tells Quartus Prime that it can treat these cases as a Don’t Care
condition. If you didn’t do this, go back and correct it to do so. Test your design on the circuit board,
and record the pattern it shows for these Don’t Care conditions (hand drawn or photo will work).

Lab Grading
Working Design: 60 points for correctness, style, and testing.

Lab Demonstration/Turn-In Requirements

Lab Report (before Wednesday section, submit as PDF on Gradescope)
• Your completed Table 1, showing your new items, their UPC codes, and classifications.
• A screenshot of the ModelSim simulations you will demonstrate during the demo.
• Drawings of the 7-seg display output for each of the unused UPC codes.
• How many hours (estimated) it took to complete this lab in total, including reading, planning,
designing, coding, debugging, and testing.
• As a separate upload, your Verilog code for the double 7-seg and Fred’s Pawn Shop designs.

In-Person Demo (during your demo slot)

• Demonstrate both the double 7-seg and the Fred’s Pawn Shop circuits in ModelSim.
• Demonstrate both the double 7-seg and the Fred’s Pawn Shop circuits on the DE1.
• Be prepared to answer questions on both the theoretical and practical parts of the lab.

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Lab 4 Rubric
Grading Criteria Points

Q1: Completed table of products being sold 3 pts

Q2: ModelSim screenshot of double 7-seg circuit 3 pts

▪ Explanation of waveforms 5 pts

Q3: ModelSim screenshot of Fred’s Pawn Shop circuit 3 pts

▪ Explanation of waveforms 5 pts

Q4: Drawings of 7-seg display output for the unused UPC codes 4 pts

Time spent 2 pts

Verilog code uploaded 5 pts

LAB DEMO 30 pts

60 pts