Power Supply Design Seminar
Advanced Digital Controls
Improve PFC Performance
Reproduced from
2012 Texas Instruments Power Supply Design Seminar
SEM2000, Topic 7
TI Literature Number: SLUP310
© 2012, 2013 Texas Instruments Incorporated
Power Seminar topics and online power-
training modules are available at:
ti.com/psds
Advanced Digital Controls
Improve PFC Performance
Zhong Ye and Bosheng Sun
Abstract
A power-factor-correction (PFC) circuit’s boost inductor and power MOSFET output capacitance
resonate inevitably when the inductor current becomes discontinuous. The resonant current can be big
enough to distort the PFC current significantly. In this paper, we will describe a new digital control
scheme to predict the optimal MOSFET switching-on position. Using an external Vds sensing signal and
the predicted switching-on position, the PFC is able to turn on the MOSFET at the Vds valley or zero-
voltage positions to minimize switching loss and reduce PFC current distortion. The digital controller
uses oversampling to improve current-sensing accuracy and noise immunity – one of the most effective
ways to minimize PFC current distortion. An EMI filter’s X-cap is the main cause degrading power factor
at light load and high line. Digitally delaying the PFC current reference generates a lagging reactive
current to compensate for the X-cap’s leading reactive current. A 360-W PFC circuit validates the control
concepts, with performance improvements demonstrated through test results.
I. Introduction The resonant current can be big enough to
distort the PFC current significantly, as shown in
A power-factor-correction (PFC) circuit with a
Figure 2a. Depending on the MOSFET’s turn-on
power level more than 200 W, as shown in Figure
time, the resonant current can add to or subtract
1, usually uses average current-mode control and
from the boost inductor current, as shown in the
operates at a constant switching frequency. The
zoom-in waveforms of Figure 2b.
circuit’s boost inductor current, iL, can maintain
Since this effect occurs at much higher
continuous conduction mode (CCM) for certain
frequency than a PFC’s current-loop bandwidth at
heavy load ranges. However, at light loads, the
discontinuous conduction mode (DCM), the
current becomes discontinuous. Once the boost
current loop cannot regulate the boost inductor
inductor current declines to zero, the boost
current fast enough to compensate for the abrupt
inductor, L, resonates freely with the PFC
current disturbance.
MOSFET Q1’s output capacitance, C1.
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Figure 1 – Experimental digitally controlled 360-W PFC circuit.
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The first part of this paper introduces a new,
simple zero-current detection circuit and reliable
control to minimize PFC current distortion while
achieving zero voltage switching (ZVS) or valley
switching without using operating-mode
switching.
Unlike an analog controller, a digital controller
uses discrete data for signal processing. Ripple
and noise on the sensed signal could easily corrupt
the data acquired by single-point sensing per
switching cycle. Section IV of this paper will
cover one of the most effective ways to improve
signal-sensing accuracy and reject noise.
Some stringent power-factor specifications
(a) AC current distortion at crossover area. have made power-supply design more challenging
in the past few years. At light load and high line,
the EMI’s X-cap’s leading reactive current
contributes a large percentage of the total current,
which results in a low power factor. Section V of
this paper will introduce reactive current-
compensation control to minimize the impact of
the X-cap.
II. Circuit Operation and Blanking
Time Prediction
For steady state operation, a boost inductor’s
volt · second can be considered balanced in each
switching cycle. Referring to Figures 1 and 3a,
given Q1’s turn-on time, tDa, the time for the boost
inductor current, iL, to first return to zero is
(b) Zoom-in of waveform. expressed in Equation 1 [8].
Figure 2 – A typical current distortion waveform (1)
at light loads.
After iL becomes negative, the boost inductor,
Several techniques include adding a snubber L, resonates with MOSFET capacitance, C1. If
[1] and complex resonant-voltage valley tracking instantaneous AC input voltage Vin (=|Vac|) is
and duty-cycle prediction [2] [3] [4] [5] [6]. Using higher than one-half the boost output voltage, Vo,
a snubber to damp the resonant current is an the MOSFET Q1’s Vds never resonates to 0 V, as
undesirable approach because of the efficiency shown in Figure 3a. If the instantaneous AC
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penalty. Using a fast digital device to predict a voltage is lower than one-half the PFC output
boost MOSFET Vds valley position cycle by cycle voltage, the MOSFET’s Vds can resonate to 0 V
is expensive. Some solutions also require an and be clamped by the MOSFET body diode, as
operating-mode switch between CCM and DCM shown in Figure 3b.
operations. Adding an additional winding to a
boost inductor for boost-inductor-current-zero-
crossing detection is not a popular approach either
[6].
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(a) MOSFET valley switching.
(b) MOSFET ZVS.
Figure 3 – Resonant period between boost inductor and MOSFET output capacitance.
During this resonant period, when the boost the volt · second applied to the boost inductor
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inductor current, iL, resonates to a negative value maintains balance. Using volt-second balancing,
and then a second time returns to zero at time, tx, SA = SB + SC, tx can be described as Equation 2:
(2)
where Vp = Vo-Vin and ωr is the angular frequency
of the resonant circuit (ωr = 1/2π Tr).
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Equation 2 can be simplified to reduce Q2 is turned on when the main MOSFET, Q1,
processor computing time. An approximate tx switches on. Q1 is controlled by the PFC’s
value can be calculated in Equation 3: average-mode current loop. Q2 is turned off at the
end of the predicted switching period and the Syn
(3) signal restarts a DPWM period when it rises to a
valid logic level. As soon as a new period is
tx decreases when Vin increases until Vin is started, Q1 and Q2 are both turned on at almost
equal to or larger than Vo/2 when the MOSFET the same time when the MOSFET Q1 Vds is at a
Vds starts to oscillate freely. Therefore, tx’s low valley position. The waveforms are shown in
limit should be clamped to Tr/4 by firmware Figure 3a. When the Vds valley voltage is lower
calculation, which is used for valley-switching than 50 V, the nonlinear characteristic of the
control. From Equations (1) and (2) or (1) and (3), MOSFET output capacitance starts to affect the
a predicted pulse-width modulation (PWM) Vds waveform, as shown in the dashed line in
switching period is expressed as Equation 4: Figure 4. The actual valley occurs later than the
calculated position. However, since the valley
(4) becomes flat, the switching loss increase caused
by the premature turning on of the MOSFET is
These equations apply to both Vin larger and insignificant.
less than one-half Vo. It is possible for a digital
controller to update the switching period with the
predicted ts cycle by cycle and achieve ZVS or
valley switching of the MOSFET’s. However, a
MOSFET’s output capacitance is actually
nonlinear versus its drain-to-source voltage. The
output capacitance of a typical MOSFET, such as
SPP20N60C3, stays relatively constant from 600
V down to 50 V, but the value increases by about
10 times at Vds = 25 V and nearly 100 times at
Vds = 0 V.
The nonlinearity introduces some error to the Figure 4 – Effect of nonlinear parasitic
calculation when the instantaneous AC voltage is capacitance.
lower than one-half the PFC output voltage.
Instead of using ts to update the PWM switching When the instantaneous AC input voltage, Vin,
period directly to ensure ZVS, a simple zero Vds (= |Vac|) is lower than one-half the boost output
and zero iL detection circuit with ts as signal- voltage, Vo, the Vds of the MOSFET always
blanking time provides a more reliable control. resonates to zero voltage. As in the previous case,
The circuit consisting of D2, R, C2 and Q2, as Q2 is turned on when the main MOSFET, Q1,
shown in Figure 1, generates a synchronous signal, switches on. Q2 is turned off at the end of the
Syn, for controller digital pulse-width modulation predicted period, as shown in Figure 3b.
(DPWM) synchronization. To ensure Syn is generated at the point when iL
When the instantaneous AC input voltage Vin changes from a negative value to a positive value,
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(= |Vac|) is higher than one-half Vo, the boost Q2 should be turned off before the positive current
inductor, L, resonates freely with the MOSFET occurs. Theoretically, Q2 can be turned off at any
output capacitance, C1. For this case, tx is clamped place where iL is negative without affecting circuit
to Tr/4 and the switching period is calculated with performance. However, we have observed that
Equation 5: noise could mistrigger a circuit and a PWM period
could start prematurely if Q2 is turned off too
(5) early. The main task of Q2 here is to block noise
and allow the zero-current detection to generate
the Syn signal.
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When load increases and the boost inductor slightly lower with the new control, and the current
current is continuous, the calculated minimum ripple at switching frequency is greatly reduced.
period ts (= tDa + tDb + Tr/2) always becomes The reduction of measured THD is not as
larger than the PWM switching period (= tDa + significant as it appears. That is due to the
tDb) set for normal mode operation. A new 30th-harmonic measurement limitation of the test
switching period starts before Q2 is turned off; equipment. Figure 6c shows Vdc valley switching
therefore, Q2 is on all the time and Syn remains of Q1. Since the tx calculation equations are valid
low. For this case, the PFC returns to conventional for both instantaneous AC voltages higher and
hard-switching CCM operation, ignoring the input lower than one-half Vo, no operating-mode
AC voltage. switching control is required. When the PFC
operates at CCM, the computed period becomes
III. ZVS and Valley-Switching larger than the maximum PWM period, which is
Experiment and Test Results set based on hard-switching operation. No Syn
We used a 360-W PFC evaluation module [10] pulse is generated. The circuit transitions
with a UCD3040 digital controller [7] for the seamlessly between constant frequency mode and
concept validation. Figure 5a shows input current variable frequency mode.
waveforms at 120-Vac input and 10 percent load Figure 7 and 8 show the PFC THD, power
with conventional fixed-frequency hard-switching factor and efficiency data. Overall PFC efficiency
control. Figure 5b shows the reduction of harmonic improved, except at high line and 10 percent load.
current with the new control method. The low- The efficiency decrease at high line and 10 percent
frequency current distortion at the crossover points load was due to the additional switching loss
was almost completely eliminated. Total harmonic caused by the increased switching frequency. At
distortion (THD) dropped from 5.25 percent to these points, the increased switching loss surpasses
4.18 percent, while efficiency improved more than the energy saved from valley switching. The
2 percent. Figure 5c shows that the PFC MOSFET digital controller knows its own switching
achieves both ZVS and ZCS. frequency and can calculate or measure output
At high-line input and light loads, MOSFET load to disable the valley-switching control (based
Q1 operates in either valley switching or ZVS/ on preset conditions), avoiding performance
ZCS depending on the instantaneous AC voltage. degradation and enabling the control to once again
Figures 6a and 6b show current waveforms at gain the efficiency and THD benefit for the rest of
230-V input and 20 percent load before and after operating conditions.
applying the new control. The measured THDs are
Topic 7
Texas Instruments 7-6 SLUP310
(a) With conventional control: THD = 5.25 percent, power factor (PF) = 0.99.
(b) With proposed control: THD = 4.18 percent, PF = 0.99.
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(c) ZVS and ZCS waveforms with proposed control.
Figure 5 – PFC current harmonic reduction and ZVS/ZCS operation at low line and 10 percent load.
Texas Instruments 7-7 SLUP310
(a) With conventional control: THD = 4.34 percent, PF = 0.96.
(b) With proposed control: THD = 4.18 percent, PF = 0.99.
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(c) ZVS and ZCS waveforms with proposed control.
Figure 6 – PFC current harmonic reduction and ZVS/ZCS operation at high line and 20 percent load.
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(a) THD comparison.
(b) Power factor correction.
Topic 7
(c) Efficiency comparison.
Figure 7 – THD, PF and efficiency comparison with and without ZVS or valley switching at low line.
Texas Instruments 7-9 SLUP310
(a) THD comparison.
(b) Power factor correction.
Topic 7
(c) Efficiency comparison.
Figure 8 – THD, PF and efficiency comparison with and without ZVS or valley switching at high line.
Texas Instruments 7-10 SLUP310
IV. Oversampling Reduces PFC oversampling scales up the control loop’s
Current Distortion frequency response to a higher frequency range
and increases the loop’s bandwidth [9].
PFC inductor current shape changes
Oversampling is one of the most effective
dramatically from CCM to DCM, as shown in
ways to reduce PFC current distortion. It has been
Figures 9 and 10. With CCM, the current at the
widely used in high-end PFC product design in the
mid-point of PWM is the average current; but with
past few years. Figure 11 shows a well-tuned PFC
DCM, the current is no more an average current.
without oversampling and Figure 12 shows the
In addition, driver and power-stage delay also
current distortion reduction when 8x oversampling
contribute to current-sensing variation. Single-
is enabled. Figures 13 and 14 provide THD
point current sensing per switching period cannot
comparison before and after oversampling is
guarantee that the sensed value is an average
enabled. As you can see, THD is reduced
value. Current-sensing error can negatively impact
considerably across the whole load range at both
THD. Furthermore, a PFC’s current-loop
high line and low line. We took the current
bandwidth decreases significantly when operating
waveforms from a 360-W PFC converter with a
at DCM, which makes it even more difficult for
Texas Instruments UCD3020 controller. There is
the PFC current to follow current command.
significant current distortion reduction by using
Oversampling effectively averages out current
the 8x oversampling technique.
ripple and noise. It minimizes noise effect and
improves current-sensing accuracy. Besides that,
Figure 9 – PFC inductor current sensing at CCM.
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Figure 10 – PFC inductor current sensing with oversampling at DCM.
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Figure 11 – Input AC current waveform without oversampling.
Figure 12 – Input AC current waveform with 8x oversampling.
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Figure 13 – THD comparison at low line.
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Figure 14 – THD comparison at high line.
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V. X-Cap Reactive-Current the leading current. In common design practices,
Compensation the PFC is controlled to draw a current in phase
with Vac from input. The total AC input current
AC input EMI filters typically consist of
becomes leading, as illustrated in Figure 16,
X-caps, Y-caps and common-mode inductors.
because of the effect of the X-cap’s reactive
Some may use different mode inductors for one
currents. If an AC reference current iref is
EMI stage. The X-cap’s capacitance has to be
generated with a lagging phase and the lagging
sized large enough to absorb most switching
phase angle is controlled based on X-cap value,
current ripple. The larger capacitance X-caps
input AC voltage and load, the leading reactive
have, the better current ripple attenuation the EMI
current can be fully compensated theoretically, as
filter can achieve. However, a large X-cap, often
depicted in Figure 17. Figures 18a and 18b show
seen in Class-B AC/DC converter designs, can
the waveforms with and without reactive-current
degrade input power factor.
compensation. With reactive-current compensation
The impact of X-caps becomes more
at the specific test condition listed in the figures,
significant at high line and light loads, where the
the power factor can improve from 0.86 to 0.92.
leading reactive current generated by the X-caps
Note that PF increase is at the cost of THD
becomes large enough to affect the total AC
degradation. Since the PFC is not able to generate
current phase.
enough inductor current at the AC voltage
Figure 15 shows the EMI filter with differential
crossover area when a current phase offset is
current paths, AC voltage and current polarity
added, the current becomes distorted.
references for analysis purposes. All capacitor
currents, denoted as ic1, ic2 and ic3, contribute to
Figure 15 – A typical EMI filter at PFC input.
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Figure 16 – AC leading current caused by X-caps. Figure 17 – X-cap leading current compensation.
Texas Instruments 7-14 SLUP310
(a) With no reactive current compensation (b) With reactive current compensation
(PF = 0.86, THD = 8.8 percent). (PF = 0.92, THD = 11.3 percent).
Figure 18 – PFC control. Test condition: Vin = 220 Vac, Vo = 360 V, load = 108 W.
VI. Conclusion controller should disable valley-switching control
when a light load is detected in product designs.
We have validated the proposed ZVS and
Oversampling of digital control improves
valley-switching control concept. The control uses
signal-sensing accuracy and noise immunity. It
a synchronization signal generated by external
scales up frequency response to a higher frequency
hardware to restart a new PWM cycle for ZVS and
region. It increases the control-loop bandwidth
valley switching. The predicted time, ts, is used to
without sacrificing its phase margin. Oversampling
block noise and prevent mistriggering PWM
is one of the most effective ways to reduce
synchronization.
harmonics and improve power factor to meet
This control proved to be valid for all line and
stringent specification requirements in product
load conditions and both CCM and DCM
designs.
operations. It allows the PFC to transfer between a
Digital controllers give the freedom of
constant frequency hard-switching mode and
computing and control, generating a delayed PFC
variable-frequency ZVS or valley-switching mode
current reference based on variables of X-cap
seamlessly, without using any conditional mode-
capacitance, input AC voltage and load conditions.
switching mechanism. The control reduces current
The leading reactive current caused by EMI X-cap
ripple significantly. It improves PFC overall
can be compensated out in real time. Our tests
performance, including THD, power factor and
showed a significant power factor improvement.
Topic 7
efficiency, at low line and light loads.
However, the improvement is at the cost of THD.
Good PF improvement and some THD
A good design practice can utilize this trade-off
reduction were also achievable at high line.
between PF and THD to achieve a design goal.
However, we observed an efficiency decrease
below 10 percent load and at high line. The
Texas Instruments 7-15 SLUP310
VII. References [6] Chen, F., and D. Maksimovic. “Digital Control
for Improved Efficiency and Reduced
[1] De Gusseme, K., D.M. Van de Sype, A.P. Van Harmonic Distortion over Wide Load Range
Den Bossche, and J.A. Melkebeek. “Input- in Boost PFC Rectifiers.” IEEE Transactions
Current Distortion of CCM Boost PFC on Power Electronics 25 (2010) 2683-2692.
Converters Operated in DCM.” IEEE
[7] Texas Instruments Data Sheet. “Fusion Digital
Transactions on Industrial Electronics 54
Power Controller UCD3040.” Accessed June
(2007) 858-865.
19, 2012. http://www.ti.com/product/
[2] De Gusseme, K., D.M. Van de Sype, A.P. Van ucd3040.
den Bossche, and J.A. Melkebeek. “Digitally
[8] Ye, Zhong, and Bosheng Sun. “PFC Efficiency
Controlled Boost Power-Factor-Correction
Improvement and THD Reduction at Light
Converters Operating in Both Continuous
Loads with ZVS and Valley Switching.”
and Discontinuous Conduction Mode.” IEEE
Paper presented at Applied Power Electronics
Transactions on Industrial Electronics 52
Conference and Exposition (APEC) 2012,
(2005) 88-97.
February 5-9, 2012.
[3] Huber, Laszlo, Brian T. Irving, and Milan M.
[9] Xu, S., and Zhong Ye. “Analysis of
Jovanović. “Line Current Distortions of
Oversampling Effects on Digitally Controlled
DCM/CCM Boundary Boost PFC
Power Supply Performances.” Paper
Converter.” IEEE Transactions on Industrial
presented at Applied Power Electronics
Electronics 54 (2007) 858-856.
Conference and Exposition (APEC) 2012,
[4] Chen, J., A. Prodic, R.W. Erickson, and D. February 5-9, 2012.
Maksimovic. “Predictive Digital Current
[10] Texas Instruments Application Note. “Fusion
Programmed Control.” IEEE Transactions
Digital Power UCD3138 PFC EVM-
on Power Electronics 18 (2003) 411-419.
PWR026.” Accessed June 19, 2012. http://
[5] Zhang, W., G. Feng, Y.F. Liu, and B. Wu. “A www.ti.com/lit/an/slua644/slua644.pdf.
Digital Power Factor Correction (PFC)
Control Strategy Optimized for DSP.” IEEE
Transactions on Power Electronics 19
(2004) 1475-1485.
Topic 7
Texas Instruments 7-16 SLUP310
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