VLSIDESIGN
Astt.Prof.Munish Verma ECEDeptt. HaryanaCollegeofTechnology&Management
Ids versusVds relation
I ds = I sd = Ch arg e induced in channel (Qc ) Electron transit time ( )
sd =
Length of channel ( L) Velocity (v)
but velocity
v = Eds
Vds Eds = L
v=
thus
Vds
L
L2 = Vds
sd
(1)
n = 650 cm 2 / V sec p = 240 cm 2 / V sec
Ids versusVds relation
The non-saturated region: Vds<Vgs - Vt
Now
Thus ,
ch arg e / unit area = E g ins o
induced ch arg e, Qc = E g ins oWL where E g = average electric field gate to channel
ins = relative permittivi ty (4.0 for SiO2 ) o = permittivi ty of free space(8.854 10 14 Fcm 1 )
ds (Vgs Vt ) V2 Now E g = where D = oxide thickness D WL ins o (Vgs Vt ) Vds Thus , Qc = ( 2) D 2 combining eq ' s (1) & (2)
I ds =
ins o W
D L
(V
gs Vt )
Vds 2
Vds
Ids versusVds relation
or
or or
W I ds = K L
2 Vds (Vgs Vt )Vds 2 W Also, = K so that L 2 Vds I ds = (Vgs Vt )Vds 2
(3)
(3.1)
gate / channel capaci tan ce C g =
ins oWL
D
we will have so that
Also,
K=
Cg WL
2 Cg Vds I ds = 2 (Vgs Vt )Vds L 2
(3.2)
C g = CoWL
so that
W I ds = Co L
2 Vds (Vgs Vt )Vds 2
(3.3)
Ids versusVds relation
Saturated region:
W (Vgs Vt ) I ds = K 2 L
Vds=Vgs - Vt
2
( 4)
or
or or
I ds =
I ds =
(V
2
gs Vt )
( 4.1)
2
Cg
W (Vgs Vt )2 I ds = Co 2L
2L
(V
gs Vt )
( 4 .2 ) ( 4.3)
MOStransistortransconductancegm &O/Pconductancegds
Transconductance expresses the relationship between output current Ids & the input I ds voltage Vgs.
gm =
we know,
I ds =
Qc
Vgs
Vds = cons tan t
Thus change in current
I ds
L2 Now, ds = Vds
Thus
Qc = ds
I ds =
QcVds
L2
but change in charge Qc so that Now,
I ds =
C g Vgs Vds
= C g Vgs
gm =
I ds = Vgs
L2 C g Vds
L2
MOStransistortransconductancegm &O/Pconductancegds
Vds = Vgs Vt Cg Vgs Vt gm = 2 L WL substituting for C g = ins o D W g m = ins o (Vgs Vt ) D L
In saturation
The output conductance gds can be expressed as:
g ds
I ds 1 = = Vgs L
MOStransistorfigureofmerito:
1 gm = o = (Vgs Vt ) = C g L2 sd
switching speed depends on gate voltage above threshold and on carrier mobility and inversely as the square of channel length.
ThenMOSinverter
Vdd = 5V Vgspu= 0 always (nMOS)
Gate tied to source
Vgspu Vin I Vgspd
Vdspu
(W/L)pu Vout (W/L)pd
[Vthpu = -0.6Vdd = -3V]
Vdspd
[Vthpd = 0.2Vdd = +1V]
pullup tx :depletionmodetransistor (onatVgs=0V) pulldown tx :enhancementmodetransistor (offatVgs=0V,onatVgs>Vthpd) Vth :devicethreshold(ON)voltage,valueofVgs whendevicebeginsto conductfromdraintosource
IdealInverterVoltageTransferCharacteristic
Vout Vdd
Vinv
Ideal inverter characteristic : VOH = Vdd (5V) VOL = OV
Vinv
Vdd
Vinv (inverter switching threshold voltage) - point where Vout = Vin
PracticalInverterVoltageTransferCharacteristic
In practice the pull-down device behaves differently than an ideal switch. It generally exhibits a leakage current in the off state, a finite resistance in the on state and a transition region where the switch can neither be considered as ON or OFF. This deviation from the ideal leads to a non ideal transfer characteristics
In practice, nMOS inverter transfer characteristic is not ideal VOL 0 W Slope < and is affected by ratio L Z
p.u.
W L
p.d .
= p.u.
Z p.d .
Zpu/Zpd ratiofornMOSinverterdrivenbyanothernMOS inverter
For depletion mode devices, Vgs=0; V inv = 0.5VDD at this point both transistors are in saturation Vgs Vt 2 W I ds = K
In the depletion mode
W p.u. ( Vtd )2 I ds = K L p.u. 2
sin ce Vgs = 0
In the enhancement mode
W p.d . (Vinv Vt )2 I ds = K L p.d . 2
sin ce Vgs = Vinv
Equating (since currents are the same) we have
W p.d . L p.d .
(Vinv Vt )
W p.u. L p.u.
( Vtd )2
Zpu/Zpd ratiofornMOSinverterdrivenbyanothernMOS inverter L L
Define
Z p.d . =
1
p.d .
W p.d .
; Z p.u. =
1
p.u.
W p.u.
We have
Z p.d .
(Vinv Vt )2 =
Z p.u.
( Vtd )2
Whence
Vinv = Vt
Vtd Z p.u. / Z p.d Vtd = 0.6VDD
Substituting typical values
Vt = 0.2VDD;
Vinv = 0.5VDD ( for equal m arg ins ) 0 .6 0 .5 = 0 .2 + Z p.u. / Z p.d
Z p.u. / Z p.d = 2 thus Z p.u. / Z p.d = 4 / 1
Zpu/Zpd ratiofornMOSinverterdriventhroughoneormore passtransistors Inverter 1 Vdd Inverter 2 Vdd
A Vin1 connection of pass transistor will degrade the logic 1 level into inverter 2 Critical case is when A is at 0 volts. B C
Vout2
Inverter 1 with input=VDD
inverter 2 with input=VDD-Vtp
W p.d .1 Vds12 (V for the p.d. transistor I ds = K DD Vt )Vds1 L p.d .1 2 Therefore Vds1 1 L p.d .1 1 = R1 = Vds1 I ds K W p.d .1 V DD Vt 2
Vds1 is small and Vds1/2 can be ignored. So,
1 1 R1 = Z p.d .1 V K DD Vt
for the p.u. transistor in saturation with Vgs=0
W p.u.1 ( Vtd )2 I1 = I ds = K 2 L p.u.1 (Vtd )2 2
The product
I1R1=Vout1 ,Thus
Z p.d .1 1 Vout1 = I1R1 = Z p.u.1 VDD Vt
1 1 R2 = Z p.d .2 (VDD Vtp ) Vt K
I2 = K
Thus
1 Z p.u.2
( Vtd )2
2 ( Vtd )2 2
Z p.d .2 1 Vout 2 = I 2 R2 = Z p.u.2 VDD Vtp Vt Z p.u.2 Z p.d .2 = Z p.u.1
For two outputs' to be equal Vout1=Vout2. therefore
Z p.d .1 VDD Vtp Vt
(VDD Vt )
)
Z p.u.1
taking typical values
Vt = 0.2VDD ; Vtp = 0.3VDD
8 =2 = Z p.d .2 Z p.d .1 1 Z p.u.2
Z p.u.1 0.8 = Z p.d .2 Z p.d .1 0.5
Z p.u.2
Alternativeformofpullupckt:
Vdd Basic Inverter: Transistor with source connected to ground and a load resistor connected from the drain to the positive supply rail Output is taken from the drain and control input connected between gate and ground Resistors are not easily formed in silicon - they occupy too much area
R Pull-Up Vo
Vin
Pull Down
Transistors can be used as the pull-up Vss device
NMOSDepletionModeTransistorPull Up:
Vdd D Pull-Down turns on when Vin > Vt With no current drawn from outputs, Ids S for both transistors is equal V0 D Vin S Vss Vin Non-zero output Vt Vdd Pull-Up is always on Vgs = 0; depletion
Vo
NMOSEnhancementModeTransistorPull Up:
Vdd Dissipation is high since current flows when Vin = 1 Vout can never reach Vdd (effect of channel) Vgg If Vgg is higher than Vdd, and extra supply rail is required
Vo
S D
V0 Vdd
Vt (pull up)
Vin S Vss
Vt (pull down) Vin Non zero output
CMOStransistor
Vout Vtn Vtp
P on N off Both On
N on P off
1: Logic 0 : p on ; n off Vin Vss Vdd 5: Logic 1: p off ; n on 2: Vin > Vtn. Vdsn large n in saturation Vdsp small p in resistive Small current from Vdd to Vss 4: same as 2 except reversed p and n 3: Both transistors are in saturation Vin Large instantaneous current flows
CMOStransistor
Current through n-channel pull-down transistor
I dsn =
n
2
VDD + Vtp + Vtn Vin = 1+
(Vin Vtn )2
n p
Current through p-channel pull-up transistor
n p
(Vin VDD Vtp ) 2 At logic threshold, Idsn = -Idsp
I dsp =
2
If n = p and Vtp = Vtn
V Vin = DD 2
2
n
2
(Vin Vtn )
= =
p
2
( (Vin VDD ) + Vtp )
pW p
Lp
nWn
Ln
n
2
(Vin Vtn )
p
2
( (Vin VDD ) + Vtp )
n (V V ) = Vin + VDD + Vtp p in tn
1 + n = Vin p
Mobilities are unequal : n = 2.5 p
n +V V +V p tn DD tp
Wp Lp
= 2.5
Wn Ln
