tage=1V.

If input (c) topology

effect (b) 3 SEMESTER Total
IV
the draw
function 1. rest.Note:EXAMINATION
SEMESTER
Hours
Time: END
(a)
A For dB
3 No.
of Rp
the For Assume
gain thissignalpowerfeedback the
Fig.
1(a) HH! Question of
and Vpp bandwidthfor G(s)
frequency thCS
e ages-4
stage
Az V,=1V drawcircuit suitable
=100 amplifier Vout
o
=u
Vin Voutstage I EC
is network. the is
and
preceded and shown VinQ, response compulsory.
missing 202
A the (s)shown
an iswith circuit Analog
verall having in
Rc
amplifier? ignoring
voltage Fig. 1(b)
Fig. (magnitude Fig.in data,
Q2
by i.e. Rp RLVcc Electronics
devicethe Attempt
if
back, a an the 1(b) any.
clean gain determine
1(a)
R2 oVout
input amplifier identify IVO......
IKOLL
and any
amplifier A, -I
with noise =1, Vino capacitances
phase). four
Marks:
Max. 40
2018)
(May -
back is with the VEE
the from B.Tech.
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signaldriven feedback Fig.
1(¢) Q1
Vcc
loading What transfer
RLVout o the
with 3
3
V, by is and
 fa br s iJaJie IWinVUoho.alsyen
remain unchanged determine the improvement in signal to
noise ratio at the output of the overall system. 3
(d) Draw the transfer characteristic curve for the circuit f
shownin Fig 1(c). 3

2.(a) Draw Bode magnitude and phase plot of a

voltage
amplifier having three poles as, o,1= 1000r/s, Op2 5000 r/s
and p3= 50000r/s respectively. The
mid-band gain of the
amplifier may be considered as 100. 3

(b) The common-emitter stage of Fig. 2

load to achieve a high gain (at low employs an active
A<0 and using Miller's theorem,frequencies). Assuming
draw unilateral smal
signal model of the amplifier and
output poles of the circuit.
determine the input and
4

Vçc Vcc
Rc
Q2 R1
o Vout Vino R_ Ct H2 TVout
Rs H RL
Vine1 R2
-.
Fig.2 Fig. 3

3.(a)For the transistor amplifier

shown in Fig. 3 assume Rs = 1
k2, Cj = Ch = 10 uF, Cp= 200 uF, R =
R =10k2, Rc= R=
Rg =1k2, Br = Bo =100, and the
bias current Ic = 2.5 mA.
Determine lower 3 dB frequency fy of the
the
amplifier. 5
 et)pin hg vrosotbf cslckee bapiek is
al to more than a single stageamplifier? 2
3
wE. 4. For the circuit shown in Fig.4 determine the condition and
ircuit frequency of oscillation. 7

3
X
R
Rc
oltage Rg
00r/s
f the
3
cR R4

active Fig.4
uming 5.(a) Draw the high frequency equivalent circuit of an emitter
Small follower and derive expression for its a, time constant. 3
ut and
(b) Giving circuit of a class B complementary symmetry push
4
pull configuration derive expression for maximum efficiency
and maximum power dissipation. 4

6.(a) A feedback amplifier utilizing voltage sampling and

out employing a basic voltage amplifier with a gain of 100 and an
output resistance of 1 kQ has a closed loop output resistance of
100 2. Determine the closed loop gain of the amplifier. If the
basic amplifier is used to implement a unity-gain voltage buffer
what output resistance do you expect? 2

Rs =1
=RL=
5 mA.
5 PTO.
6. (b) For the feedback amplifer circuit shown in Fig. 4identify
the feedback topology and determine the basic amplifier gain A
closed loop gain Ar, Rrp and Ror. The amplifier has Rs = 600 2,
R,= 5002, RÍ =20 kl, R,=1 k2, R= 50k2, R=2 kQ and 1
gm=100mS. 5

Imi
RVi 1.
RL fu
Vs
dr
R1 th
R2
RiF R oF

Fig. 4
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