Hardware Design Methodology

Dr. Prasanna Kumar Misra

Assistant Professor, IIIT Allahabad
Outline:
• Introduction
• Why Hardware Design Methods are required ?
• PROM, PAL, PLA
• FPGA, ASIC, SOC
• Programming Methods
• Hardware-Software Codesign
• RISC CPUs, DSPs, GPUs,
• SRAM, DRAM, Flash, MRAM
• Power Supplies, Regulators, Converters etc.
• Applications
Introduction:
Introduction:
ASIC is an energy efficient solution with price of programmability.
𝞵P is a quick solution with the price of energy.
TxRx Chip:
Vdd IFp+_TX IFn+_TX Vdd I/O

Vin_Rx_RF

Vout_TX

V_tail_PLL

Vout_RX

Vbias_PLL GND I/O

f_ref_PLL Gnd
ADC & DAC chip: TRNG o/p
AVdd
TRNG o/p
Vdd TRNG
TRNG
o/p
TRNG i/p o/p

• B1-B6 = Output of 6-bit ADC

• b1-b6 = Input of DAC

Vref (DAC) B1

S/H clk B2

ADC clk B3

Vin (ADC) B4
DAC out B5

b6 B6

TRNG
b5 o/p

TRNG
b1 b2 b3 b4
o/p gnd Agnd
Classification

General Purpose
•Die size = 112 mm2
• 90 nm Process Technology
• 16 kB L1 Cache, 1 MB L2
Cache
• 125000000 transistors

Intel Pentium 4 Processor [ISSCC 2004]

Classification

Application Specific
• Die size = 2.25 mm2
• Core size = 1 mm2
• 180 nm Process Technology
• No Cache memory (Used
only registers)
• Clock Freq = 20 MHz

Network Processor [IITK-2011]

process the incoming IPv4 packet headers of 20 bytes
(Prasanna Kumar Misra, S. Qureshi)
Introduction:
FPGA:
• Quick solution to proof of concept (Quick Prototype)
• Low design cost (low Volume production)
• Reprogram the digital system/controller
ASIC:
• Improved clock frequency
• Low cost for high volume production
• Energy efficient
• Reconfiguration is not of much interest
SOC:
• System with multi functions
• Integration of IPs/Systems
• Energy efficient
• Huge fixed investment cost
General Purpose Circuits/Systems:

Commercial
Technology

1. Amplifiers OPAMP chips, Data Converters

2. Oscillators PLL chips
3. Digital Systems Microprocessors, DSPs
4. Registers Memory chips (DRAM, Flash)
5. RF Components Transceivers (WiFi, Cellular, Bluetooth, IoT)
6. External Supply DC-DC Power Supply chips
Semiconductor Foundries for ASIC/SOC
Based Systems:
1. TSMC

2. UMC

3. IBM

4. Samsung

5. Global Foundries

6. ST Microelectronics

7. IHP Germany

8. SCL India
FPGA Providing Vendors for FPGA based
Systems:
• Xilinx
• Toshiba
• Concurrent logic
• Altera
• AMD
• Actel
• Quicklogic
• Crosspoint
Recent Trends on VLSI Technology Industry:

1. Logic CMOS (CPUs, OPAMP, Data Converter, Memories)

2. RF CMOS (High Speed Circuits, Data Converter, Transceiver)

3. SiGe BiCMOS (High Speed Circuits, Data Converter, TxRx)

4. HV CMOS (Circuits/Systems for Electric Vehicle, Solar power

generating systems, Power Electronics etc.)

5. III-V Compound Semiconductor (GaAs Amplifiers, Oscillators,

InP Amplifiers, Oscillators, Drivers, Opto electronics etc.)
Hardware, Software Productivity gap:

VLSI Technology Productivity ~ f (PR, TE)

(Scaling)
PR = Physical Resources
TE = Technology Experts

Hardware Design Productivity ~ f (PR, TE, HE)

(CPU, GPU, DSP) HE = Hardware Experts

Software Design Productivity ~ f (PR, TE, HE, SE)

(Applications)
SE = Software Experts
More people are involved to manage the complexity
Hardware, Software Productivity gap:

VLSI Technology Physics, Material Science

(Scaling)

Electronics (SPICE, Verilog)

Hardware Design
Computer Science
(CPU, GPU, DSP)

Software Design
(Applications) How fast a complex system can be realized,
which is in working condition and sellable ?
Design Management and Execution:

Design Engineers, Managers improve the system productivity by

1. Managing the system complexity with support of EDA Tools for

practical realization purpose.
2. Reducing design cycle with support of design team & verification
team (SPICE, Verilog Programming, Automation with Scripts)
3. Collaborating with semiconductor manufacturing companies for
fabrication
4. Packaging and Testing the chip after fabrication
5. placing the system into product level application
Design Management and Execution:

Design Engineers would like to design circuits based on the

operating frequency requirements.

1. Circuit design using pre-existing components/devices

(SPICE simulations followed by practical realization)
2. Circuit Design using Integrated devices of a IC Technology
(SPICE simulations, verifications followed by fabrication)
3. When circuit complexity increases, simulation time
increases resulting to increase in design time and design
cost. (In this case, you need help of EDA Tools)
Various SPICE Simulators:
For learning purpose, one can choose a simple low cost simulator.
For commercial purpose, a complex simulator may be chosen.
(which is normally costly).

1. AIMSPICE (SPICE code, SPICE simulations)

2. LTSPICE (Graphical interface + SPICE code generation, simulation)
3. SPECTRE (Complex system design and verification like 𝝻P, ADC,
DAC, Transceiver, Power supply etc.)
4. HSPICE (Complex system design and verification)
5. ELDO (Complex system design and verification)
Analog/RF System design flow:

Provided by Semiconductor
Manufacturing Companies SPICE Simulation
1. Design Rules
2. Transistor models
3. Passive device models
4. I/O pads, Bond pads

System Examples:
1. OPAMP Design
2. Transceiver Design SPICE Simulation
3. Power Supply Design
4. Memory Design
Test Plan of Transceiver chip:

Fig. 1: Block diagram of Transceiver for

Fig.1: Transceiver chip (UMC 180 nm 865-867 MHz band
CMOS)

Fig.2: Test Plan for Transceiver chip

Test Plan of ADC chip (EDU080):
Table 1: Specification of ADC
ADC Specification
Technology 180nm
Resolution 6 bits
Supply Voltage 1.8
Sampling Speed ~ 300 MS/s
Power <350µW
Dissipation
SNR ~30dB
ENOB ~5.3
INL <1
DNL <1
Chip area 0.75mm2

Fig.3: Chip received from SCL Mohali

Fig.4: Test Plan for 6-bit ADC chip
Digital System design flow:
System Examples:
1. Microprocessor Design
2. Digital Controller Design

Obtained through spice simulations

& characterizations using a
Semiconductor Process Technology
Utility of SPICE Programming:

1. Circuit can be modeled using SPICE programs

2. MOSFET models can be incorporated into the program
3. Current voltage relations can be understood in each part
of the circuit.
4. Performance of the circuit can be optimized.
5. Bugs can be removed in early stage of design

• Once VLSI technology is decided for designing circuits,

MOSFET models can be requested from the Industry for
circuit simulation.
• For different technologies and different foundries, the models
are different.
Utility of Verilog Programming:

1. Complex system design using SPICE programs is time

consuming process.
2. To reduce the design time, VLSI systems are modeled
using Verilog program.
3. EDA Tools are used for GATE level netlist generation
and physical layout of the Verilog design for quick
completion of the design and verification.
4. Verilog simulation is faster.
5. SPICE simulation is more accurate.

For chip design both knowledge are required.

Why to Use Simulators/EDA Tools:

Commercial EDA Tools for VLSI design:

1. Cadence
2. Synopsys
3. Mentor Graphics

Design flow using EDA Tools:

1. Analog/RF VLSI Design flow

2. Digital VLSI design flow

EDA tools helps in identifying the mistakes of design engineers

in early stage of design. Therefore it supports for designing
complex circuits/systems with minimum mistakes.
Applications (ASICs, SOCs):

• Fabless Companies (Design Engineers)

• Foundries (Technologists, Engineers)
• EDA Tool providers (Cadence, Synopsys, Mentor)

• SPICE Code of Circuit for simulation and verification

• N-Channel and P-Channel MOSFET Model parameters
• Equations in EDA Tools
Basic Components in Process Design Kit for ASIC:
SS S G D D G S SS

+++++ -------
------ +++++
P+ N+ N+ P+ P+
P+ N+

NMOS PMOS
NWell

P Substrate

C B E B C

N+
P
N

NPN Bipolar Junction Transistor

Applications (FPGA):

Logic Blocks can be configured by

• Logic GATEs (AND, OR, MUX etc.)

• AND – OR Planes (PROM, PAL, PLA)
• Look up Table (Using Memory)
PROM, PAL, PLA:
PROM:
PROM:

Fixed AND
ARRAY
PAL:

A B C
Fixed OR ARRAY

AB

A C’

A B’

B C’

Programmable
AND ARRAY
x y
PLA:
A B C
Programmable
OR ARRAY
AB

A C’

A B’

BC

Programmable
AND ARRAY
x y
CPLD:
High Logic to Interconnect ratio
Ideal option for implementation of simple functions
Look up Tables:

4 memory/SRAM cells are

required to store the output.
Look up Tables:

8 memory/SRAM cells are required to store the output.

Look up Tables in FPGA:

• DFF
• Unlatched combinational circuit output
• Latched combinational circuit output
Basic Elements of FPGA:

1. Logic Block
2. Interconnect Block
3. I/O Block
CPLD vs FPGA:
FPGA providing vendors:

• Xilinx
• Toshiba 1. SRAM based Programming
• Concurrent logic 2. Floating gate based programming

• Altera 3. Antifuse based programming

• AMD
• Actel
• Quicklogic
• Crosspoint
Antifuse based Programming:

• Actel
• Quicklogic
• Crosspoint

• By applying a voltage nearly 10 V, the polysilicon to

n+ diffusion path offers low resistance.

• One time programmable

Floating gate based programming:

• Altera
• AMD

Transistor can be disabled by applying high voltage

between gate and drain terminal of transistor
SRAM based Programming:

• Xilinx
• Toshiba
• Concurrent logic
Programming an FPGA:
Application:
Software

Instruction Set Architecture

Hardware

Instruction Set Architecture provides a well defined hardware/software

interface that has complete collection of instructions understood by CPU.

Applications

Operating System
Compiler Firmware

Instruction Set Architecture

CPU Memory I/O
Digital Circuit
Transistors (NMOS, PMOS)
Performance gain of a program on CPU:

[1] David Patterson, “50 years of Computer Architecture: From the Mainframe CPU to
the Domain-Specific TPU and the Open RISC-V Instruction Set, ISSCC 2018.”
Hardware Software Productivity gap:

VLSI Technology
(Scaling)

Hardware Design
(CPU, GPU, DSP)

Software Design
(Applications)
Methods for Algorithm Execution:

1. Hardwired System (ASIC or Board with integrated components)

2. Software programmed system (Microprocessor, DSP, FPGA)

Flexible vs. in-flexible solution

Systems for Computing:

1. General Purpose Systems
2. Application Specific systems
Methods for Algorithm Execution:

1. Fully hardwired system (Highly inflexible) ASIC

2. Fully Programmable system (Flexible) µP
3. Partly Programmable System (Tradeoff betn µP, ASIC)

High level of flexibility and high performance

is not possible !
Coupling:

Microprocessor
+
Reconfigurable Logic
Coupling:

Partitioning of Tasks

Microprocessor (flexible, slow)

+
Reconfigurable Hardware (Inflexible, Fast)

Loop, Branch Control can be executed using microprocessor.

Complex functions can be executed using reconfigurable hardware.
Coupling:

• Variable length loops, branch Control can

not be mapped to reconfigurable logic.

• These types of operations are usually carried

out with a conventional microprocessor.
FPGA based Processor:

• Microprocessors are highly optimized for generally

purpose programs. (Imperative language, Optimizing
compilers, memory access)
• FPGAs provide a flexibility in implementing a given
algorithm that cannot be achieved by conventional
microprocessors.
• Processors developed using FPGA can have many
custom instructions that can provide better results for
specific applications.

[2] Axel Jantsch, Peeter Ellervee, Johnny Oberg, and Ahmed Hemani, “A Case Study on Hardware software
Partitioning”, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines, 1994, pp. 111-118.
TOP Down Design Process for Systems:
Specification

System Architecture

Behavior Process Processes

Communication

RTL Structural Modules

Description

Logic Detailed High Level Language

Logical
Structure
Physical Object Code

Integration Integration

System Test
Courtsey: Wayne Wolf
Applications:
Summary:

• Tradeoff between Conventional Microprocessor

vs FPGA based processor
• Hardware-Software partitioning
FPGA vs ASIC vs Fully Custom Chips:
ASIC Design Flow:
System Examples:
1. Microprocessor Design
2. Digital Controller Design

Obtained through spice simulations

& characterizations using a
Semiconductor Process Technology
Library for ASIC Design:

cmos180.tech (Technology rules for placement, routing)

pdk180.lib (standard cells: Timing, Power, symbol)
pdk180.db (standard cells: Timing, Power, symbol)

pdk180.lef (standard cells: Timing, power, geometry)

Performance of Digital ICs:

For fast switching and minimum delay:

1. Increase the load current
2. Reduce load capacitance
Performance of Digital ICs (Tech. Aspect)

For increasing the Current,

1. Mobility can be increased (Strained silicon MOSFETs)
2. COX’ can be increased (Reduce gate dielectric thickness)
3. COX’ can be increased by improving gate dielectric Permittivity
4. Reduce threshold voltage (Technology scaling)
5. SOI CMOS for reducing CL
6. Use of multi gate transistors for high on current
Performance of Digital ICs (Design Aspects)

For increasing the Current,

1. Multiple VDD systems
2. Multiple threshold voltage systems
3. Use of bipolar transistor for high drive strength (BiCMOS Tech.)
4. Interconnects with low resistivity material (Minimum CL)
Clock Gating (Low power Aspects)”

FF is active all the time due

to transitions in clock input.

When Inputs of XOR gate is same enable is 0 (clock deactivated)

When inputs of XOR gate is different enable is 1 (clock activated)
Dynamic power of flipflop reduced with the clock gating.
Power Gating (Low power Aspects)”

Sub threshold Leakage reduce when

logic block is not computed.
Probability of switching:

If PA and PB are the probabilities the inputs A and B are 1, then the
output transition probability P01 can be expressed as
For NAND, P01 = P0 . P1 = PA PB (1- PA PB)
For NOR, P01 = P0 . P1 = [1- (1- PA )(1- PB)] [(1- PA )(1- PB)]
Probability of switching:

1. Chain implementation has a lower switching activity

than the tree implementation for random inputs.
2. This results to low power consumption in chain
implementation in the price of delay.
Input Ordering:

If the input transition probabilities of the design is

known, then by reordering the inputs the power
consumption can be reduced.
Inverter Design:
S G D D G S VDD

+++++ -------
------ +++++
P+ N+ N+ P+ P+
P+ N+

NWell

P Substrate
Inverter Voltage Transfer Characteristics:
Inverter Voltage Transfer Characteristics:
Noise Margin of Inverter:

NMH= VOH – VIH

NML= VIL – VOL

VOH
Logic 1
VIH

Undefined

VIL
Logic 0
VOL
Inverter Layout:
Power Estimation of Inverter:
NAND2, NOR2 Optimization:
VTC of NAND2, NOR2 w.r.t. Inverter :
VTC of NAND2 :
VTC of NOR2 :
Logic Families:

• Static CMOS
• Complementary CMOS
• Pseudo NMOS
• Pass transistor
• Dynamic Circuit
• Domino Logic
SIMD:
Temporal Architecture is
used by CPUs and GPUs.
Controller and register file is
shared by all ALUs.

More no of data movements

from memory to ALU.

IEEE CICC 2017 [7]

More power consumption, increased heatsink requirements.

Power hungry systems !!
Spatial Architectures:
Control logic and register files are
part of all ALUs.

Reduced no of data movements.

Low power consumption. IEEE CICC 2017 [7]

Low Power systems !!

Fully Custom Design Flow:

Provided by Semiconductor
Manufacturing Companies SPICE Simulation
1. Design Rules
2. Transistor models
3. Passive device models
4. I/O pads, Bond pads

System Examples:
1. OPAMP Design
2. Transceiver Design SPICE Simulation
3. Power Supply Design
4. Memory Design
PDK for Fully Custom Design:
SS S G D D G S SS

+++++ -------
------ +++++
P+ N+ N+ P+ P+
P+ N+

NMOS PMOS
NWell

P Substrate

C B E B C

N+
P
N

NPN Bipolar Junction Transistor

Performance of Analog ICs (Design Aspects)

1. High Voltage gain using minimum current

2. Gain-Bandwidth Product
3. High Common mode rejection ratio
4. High Power Supply rejection ratio
5. Use of high quality voltage and current sources
6. Minimum Variations
Performance of Analog ICs (Design Aspects)

Source: Behzad Razavi, ”Design of analog CMOS integrated circuits”

Focus to optimize one parameter at a time to have in-depth

knowledge on circuit. Gradually, other parameters can be
considered for optimization.
Performance of Analog ICs (Design Aspects)

When you try to make a better design in terms of

performance and power, your design is going to be complex.

To handle the complexity efficiently without any error you

take the help of EDA tools, Design Engineers, foundry support
and Mathematical modeling.
Quality of Voltage and Current Sources
Ideal voltage source is one whose terminal voltage, V is a specified
function of time regardless of the current, I through the source.
Ideal current source is one whose terminal current, I is a specified
function of time regardless of the voltage across the terminals .

Design Ideal Voltage Sources for biasing

Design Ideal Current Sources for biasing and amplifying
Minimize the variations in the final circuit/chip
Important Property

Trans-conductance, gm > Output Conductance, gds

Bipolar Junction Transistor
MOSFET

For MOSFET, λ=0.1, (VGS –VT) = 0.2 V, Av= 100

For HBT, VA=10, VT (kT/q) = 0.026 V, Av= 384
For HBT, VA=20, VT (kT/q) = 0.026 V, Av= 769
RC Circuit Analysis:

RC Circuit Transient Simulation

R1 in out 1K
C1 out 0 1p
Vin in 0 AC PULSE(0 1.8 1n 1n 1n 10n 20n)
.plot transient v(in) v(out)
Inverter Design:
S G D D G S VDD

+++++ -------
------ +++++
P+ N+ N+ P+ P+
P+ N+

NWell

P Substrate
SPICE Code for Inverter (AIMSPICE):

Inverter Design

vdd 3 0 dc 1.8
Vin in 0 dc 0.0 PULSE(0 1.8 2n 2n 2n 25n 50n)

m1 out in 3 3 ptype l=180n w=480n

m2 out in 0 0 ntype l=180n w=240n

.plot v(in) v(out)

.MODEL ntype NMOS (Use All parameters here)

.MODEL ptype PMOS (Use All parameters here)
Inverter Voltage Transfer Characteristics:

Vout

Vin
Can you use this as an amplifier ?:

Slope =-1

|Gain| > 1

Slope =-1

Amplifier gain should be constant over a range of input bias

Amplifier should be linear in the range of operation
Amplifier load should be stable
Amplifier saturates with variations of input bias, supply voltage, noise
Example of a badly designed amplifier:
Voltage gain is positive.
Cascaded system increases the magnitude of gain.
Sensitive to input bias, supply, noise.
Visualize the steepness of the transition in next slide.
SPICE Code for two stage Amp:

vdd 3 0 dc 1.8
vin in 0 dc 0.0 sin(0.85 0.01 1KHz 0 0)
m1 2 in 3 3 ptype l=180n w=4800n
m2 2 in 0 0 ntype l=180n w=2400n

m3 out 2 3 3 ptype l=180n w=4800n

m4 out 2 0 0 ntype l=180n w=2400n

.plot v(out) v(in)

.MODEL ntype NMOS (Use All parameters here)

.MODEL ptype PMOS (Use All parameters here)
Modification in Amplifier:
Remove PMOS and input connection to PMOS.
Use fixed load, R, instead of variable load.
SPICE Code for two stage Amp:

vdd 3 0 dc 1.8
vin in 0 dc 0.0 sin(0.75 0.01 1KHz 0 0)
R1 2 3 10K
m1 2 in 0 0 ntype l=180n w=2400n
R2 out 3 10K

m2 out 2 0 0 ntype l=180n w=2400n

.plot v(out) v(in)

.MODEL ntype NMOS (Use All parameters here)

.MODEL ptype PMOS (Use All parameters here)
Amplifier Analysis
1. Voltage amplifier: (vin ~ v0)
2. Trans-conductance amplifier: (vin ~ i0)
3. Current amplifier: (iin ~i0)
4. Trans-impedance amplifier: (iin ~v0)
Amplifier Analysis

High input impedance

Low output impedance
High Gain (Virtual Ground for 2 input terminal)

Open loop gain

Amplifier Requirement
Importance of input and output impedance

Can you design an amplifier with open loop gain of 100000

and 1GHz bandwidth with rail to rail swing ?
Meaning of Various Amplifier:
In common source amplifier,

Source is either connected to Ground or DC Bias.

Input, output can be connected to other terminals.

In common gate amplifier,

Gate is either connected to Ground or DC Bias.

Input, output can be connected to other terminals.

In common drain amplifier,

Drain is either connected to Ground or DC Bias.

Input, output can be connected to other terminals.
DC Analysis, Saturation
DC Analysis, Saturation

Dependent Current Source

DC Analysis

Design Tips:
1. With technology scaling, gds value of MOSFET increases.
2. Therefore, intrinsic voltage gain gets affected.
3. Use higher channel length than the minimum value.
4. Overdrive voltage > 200 mV but should be < 500 mV
Small Signal Analysis
Small Signal Analysis
Small Signal Analysis
Biasing
Biasing is needed With biasing, amplified output
to fix the DC operating point should be received
Biasing
• VDS changes due to RL value
• IDS changes due to VDS • AC power will be received
• Transistor may go towards linear • Biasing will not be affected
Biasing
• Bias and Signal has same ref value
• Bias is shorted.
• Bias from supply
• Don’t have control on bias voltage
Biasing
• Now VGS is different than VDD
• Advantage of negative feedback
• Use a coupling capacitor
• Gain improved
Capacitor Replacement
• Use - supply to avoid CG
• Use circuit with low o/p resistance to avoid CD
Capacitor Replacement
• Replace CS
• Use a low impedance path
SPICE Code of Differential Amplifier
vdd 3 0 dc 1.8

v1 in1 0 dc 0.9 ac 1 sin(0.5 0.2 1KHz 0 0)

v2 in2 0 dc 0.9
v3 vbias1 0 dc 0.6
R1 out1 3 40k
R2 out2 3 40k
C1 out2 0 10p
C2 out1 0 10p

m1 out1 in1 vir 0 ntype l=180n w=4800n

m2 out2 in2 vir 0 ntype l=180n w=4800n
m3 vir vbias1 0 0 ntype l=180n w=9600n

.defwave vo = v(out1)-v(out2)
.defwave vi = v(in1)-v(in2)
RS was replaced by m3 Transistor .plot ac vdb(vo,vi)
In SPICE code
.MODEL ntype NMOS (use parameters)
.MODEL ptype PMOS (use parameters)
Results of Diff Amp:
CE/CS Amplifier
Miller Capacitance
The capacitance value is amplified that effects the
bandwidth of the CE/CS amplifier
Bandwidth of CS Amplifier
Question1 (DC Bias effect):

Circuit 1 Circuit 2

Which one provides better low frequency gain and why ?

Question2 (Load Resistance effect)

Circuit 1 Circuit 2

Which one provides better low frequency gain and why ?

Question3 (W/L ratio effect):

Circuit 1 Circuit 2

Which one provides better low frequency gain and why ?

Question4 (output conductance effect)

Circuit 1 Circuit 2

Which one provides better low frequency gain and why ?

Question5

Can you design an Common Source Amplifier

with low frequency voltage gain > 20 dB ?
CS with Active Load:

common source amplifier

vdd 3 0 dc 1.8
vg 1 0 dc 0.5
vin 4 0 dc 0.8 ac 1.0 sin(0.5 0.5 1GHz 0 0)
m1 2 1 3 3 ptype l=180n w=1000n
m2 2 4 0 0 ntype l=180n w=1600n

.plot ac vdb(2,4)
.plot v(2) v(4)

.MODEL ntype NMOS (Use All parameters here)

.MODEL ptype PMOS (Use All parameters here)
Results of CS Amp with Active Load:
CS with source degeneration

How to give input bias of 0.9 V ?

What will be the output DC voltage ?

CS with source degeneration

Please try this in lab exercise ?

Find CC value for your design ?
Negative feedback due to RS
Assume Vth of transistor increases after
fabrication compared to the designed value.

Vth IDS IDSRS VGS IDS

The decrease in current value is

compensated with the increase in
current value due to the negative
feedback used in circuit.
CS with source degeneration
What will be output impedance, Rout ?

RL

R0
CS with source degeneration
Negative feedback by the resistor, RS
Independent on transistor internal parameters

Approximately, AV = -RL/ RS
CS with source degeneration, current load

Output resistance is approximately r01

Trans-conductance value remains same

r01

High value
If somebody did mistake in connection,
then what will be output ?
Linearity

By increasing the input signal power, Voltage, the amplifier

saturates and signal swing is limited.
Rail to Rail Swing
Minimum Voltage is limited by VDS value of transistor
Transistor goes to linear mode for low value of VDS
Noise Performance

Thermal noise power = 4kTRB

K = Boltzmann constant
R = Resistance
T = Temperature
B = Bandwidth

1. Minimize the resistance value. Use noiseless resistor.

2. Use filter to regulate the bandwidth
3. Minimize the heating and hence lattice temperature

Thermal noise is responsible for noise performance of amplifier.

Flicker noise is responsible for phase noise of oscillator
CB/CG Amplifier
CB/CG Amplifier
Bandwidth of CG Amplifier
SPICE Code of CG Amplifier

vdd 5 0 dc 1.8
R1 1 5 100K
R2 1 0 157K
Rd 4 5 5K
Rs 2 0 1.5K
c1 2 3 1u
c2 4 0 10p
vin 3 0 dc 0.0 ac 1.0 sin(0.5 0.5 1KHz 0 0)

m1 4 1 2 0 ntype l=180n w=16000n

.plot ac vdb(4,3)
.plot v(4)v(3)

.MODEL ntype NMOS (Use All parameters here)

.MODEL ptype PMOS (Use All parameters here)
Results of CG Amp:
CC/CD Amplifier
Transforms from high impedance to Tunable impedance
CC/CD Amplifier

Find f3db ?
Detailed Analysis of CS Amplifier

Schematic of CS Amplifier Small signal equivalent of CS Amplifier

Detailed Analysis of Voltage Gain
Detailed Analysis of CG Amplifier
(1)

(2)

(3)

Schematic of CG Amplifier Small signal equivalent of CG Amplifier

Detailed Analysis of Voltage Gain
Detailed Analysis of CD Amplifier
(1)

(2)

(3)
(4)

Schematic of CD Amplifier Small signal equivalent of CD Amplifier

Detailed Analysis of Voltage Gain
Differential Amplifier Design:
vdd 3 0 dc 1.8
vin1 v1 0 dc 0.85 ac 1 sin(0.5 0.4 1KHz 0 0)
vin2 v2 0 dc 0.85

m1 p1 v1 n1 0 ntype l=180n w=9000n

m2 vout v2 n1 0 ntype l=180n w=9000n
m3 p1 p1 3 3 ptype l=180n w=3000n
m4 vout p1 3 3 ptype l=180n w=3000n
m5 n1 n2 0 0 ntype l=180n w=6000n
m6 n2 n2 0 0 ntype l=180n w=6000n
m7 n2 n2 3 3 ptype l=180n w=1500n
C1 vout 0 2p

.plot ac vdb(vout,v1)
.MODEL ntype NMOS (Use parameters)
.MODEL ptype PMOS (Use parameters)
Results of Diff Amp:
Operational Amplifier Design:
SPICE Code of Operational Amplifier:
vdd 3 0 dc 1.8
vin1 v1 0 dc 0.85 ac 1 sin(0.5 0.4 1KHz 0 0)
vin2 v2 0 dc 0.85

m1 p1 v1 n1 0 ntype l=180n w=4500n

m2 p2 v2 n1 0 ntype l=180n w=4500n
m3 p1 p1 3 3 ptype l=180n w=15000n
m4 p2 p1 3 3 ptype l=180n w=15000n
m5 n1 n2 0 0 ntype l=180n w=6000n
m6 n2 n2 0 0 ntype l=180n w=6000n
m7 n2 n2 3 3 ptype l=180n w=180n
m8 vout p2 3 3 ptype l=180n w=30000n
m9 vout n2 0 0 ntype l=180n w=1800n

C1 p2 vout 2.2p
C2 vout 0 10p
.plot ac vdb(vout,v1)
.MODEL ntype NMOS (Use All parameters here)
.MODEL ptype PMOS (Use All parameters here)
Results of 2-stage OPAMP:
Thank you