EEC 118 Lecture #1: MOSFET Overview

Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

Permissions to Use Conditions & Acknowledgment

Permission is granted to copy and distribute this slide set for educational purposes only, provided that the complete bibliographic citation and following credit line is included: "Copyright 2002 J. Rabaey et al." Permission is granted to alter and distribute this material provided that the following credit line is included: "Adapted from (complete bibliographic citation). Copyright 2002 J. Rabaey et al." This material may not be copied or distributed for commercial purposes without express written permission of the copyright holders. Slides 13-17 Adapted from CSE477 VLSI Digital Circuits Lecture Slides by Vijay Narayanan and Mary Jane Irwin, Penn State University
Amirtharajah/Parkhurst, EEC 118 Spring 2006 2

Outline
Administrative Details Survey of Digital IC Technology MOSFET Overview

Amirtharajah/Parkhurst, EEC 118 Spring 2006

Personnel Prof. Raj Amirtharajah (Instructor)

Office: 3173 Kemper Hall Email: [email protected] Please put EEC 118 in email subject line. Office Hours: Th 1-3 PM or by appointment.

Anurag Chaudry
Email: [email protected] Office Hours: TBD

Amirtharajah/Parkhurst, EEC 118 Spring 2006

Course Materials Textbook

CMOS Digital Integrated Circuits (3rd ed.) By S-M. Kang and Y. Leblebici

Suggested References
Digital Integrated Circuits (2nd ed.), Rabaey, Chandrakasan CMOS VLSI Design (3rd ed.) Weste, Harris

Handouts
Labs, lab report cover sheets, slides, and lecture notes available on course web page in PDF format.

Web Page
http://www.ece.ucdavis.edu/courses/S06/EEC118 Linked from Prof. Amirtharajahs home page
Amirtharajah/Parkhurst, EEC 118 Spring 2006 5

Grading Letter A: 100 - 90% B: 90 - 80% C: 80 - 70% D: 70 - 60% F: below 60%

Expect class average to be around B- / C+ Curving will only help you

Amirtharajah/Parkhurst, EEC 118 Spring 2006 6

Weighting
Labs 15% Design Project 15% Weekly Homework 5% Scale for each problem: 0 = poor effort, 1 = close, but fundamental problem, 2 = correct Quizzes 10% Four throughout the quarter (approx. every other week), lowest score dropped (April 12, April 26, May 17, May 31) Midterm 20% Wednesday, May 3 Final 35% Wednesday, June 14, 8 AM Cumulative, but emphasizes material after midterm
Amirtharajah/Parkhurst, EEC 118 Spring 2006 7

Labs and CAD Software Usage

Need to know/learn SPICE Circuit Simulation Use same breadboard as EEC 180A

Amirtharajah/Parkhurst, EEC 118 Spring 2006

Education Demand for Circuit Design

Industry needs circuit designers Not just logic designers Must understand operation at transistor level Not just digital designers Must understand analog effects Not just analog designers Must be able to comprehend Deep Sub-Micron (DSM) effects (<0.13um) Fundamental circuit knowledge critical Similar techniques for bipolar transistors, NMOS (even relays and vacuum tubes!) Must be able to exploit nanoscale devices in future
Amirtharajah/Parkhurst, EEC 118 Spring 2006 9

Education Demand for System Design

Industry needs system designers Need to understand system implications of your design Power Delivery, Clock Loading What do you need Need to design from the system point of view Communication protocol how to effectively talk with other blocks What should be added into your block to meet system design requirements(i.e. comprehend soft block methodology for optimization of area, interconnect, etc.)

You must operate at both levels!

Amirtharajah/Parkhurst, EEC 118 Spring 2006 10

Historical Background

Graph shows the growing complexity of designing integrated circuits

Amirtharajah/Parkhurst, EEC 118 Spring 2006 11

Memory, Processors and Graphics

Used to be that memory and processors were the two main design drivers.

Amirtharajah/Parkhurst, EEC 118 Spring 2006

http://turquoise.wpi.edu/webcourse/ch01/ch01.html 12

Memory, Processors and Graphics

We now have graphics also driving integration
1000

100

Gr
10

hic ap

8x/ s

mo 18

o x/18m CPU 2
1H96 2H96 1H97 2H97 1H98 2H98 1H99 2H99 1H00 2H00

From ISPD 1999 Keynote Speech by Chris Malachowsky of NVIDIA Amirtharajah/Parkhurst, EEC 118 Spring 2006 13

Hybrid to Monolithic Trend

We continue to integrate multiple functions on a single chip Mixture of Analog, Radio Frequency (RF), Digital Graphics/Motherboard chipset an example of this Cost and Performance driving market Higher performance achieved on chip than off chip Lower cost due to a single die versus multi-chip design Saves on packaging, total area by eliminating redundant functions System-on-a-Chip (SOC) concept
Amirtharajah/Parkhurst, EEC 118 Spring 2006 14

What are the issues facing the industry ?

Growth of transistors is exponential Growth of operating frequency is exponential Reaching a limit due to power dissipation (see next generation Pentiums and Itaniums) Complexity continues to grow Trend is toward multiple cores on one chip Design teams cannot keep up with trend Power dissipation a concern Power delivery, thermal issues, long term reliability Manufacturing providing us with lots of transistors How do we use them effectively (besides large caches)?
Amirtharajah/Parkhurst, EEC 118 Spring 2006 15

Why worry about power? Power Dissipation

Lead microprocessors power continues to increase
100 P6 Pentium 10 8086 286 1 8085 8080 486 386

Power (Watts)

8008 4004

0.1 1971 1974 1978 Year 1985 1992 2000

Power delivery and dissipation will be prohibitive

Source: Borkar, De Intel

Amirtharajah/Parkhurst, EEC 118 Spring 2006

16

Why worry about power? Chip Power Density

10000 Power Density (W/cm2)

Suns Surface Rocket Nozzle Nuclear Reactor

chips might become hot

1000

100

8086 Hot Plate 10 4004 P6 Pentium 8008 8085 386 286 486 8080 1 1970 1980 1990 Year 2000 2010

Source: Borkar, De Intel

Amirtharajah/Parkhurst, EEC 118 Spring 2006

17

Chip Power Density Distribution

Power Map
250

On-Die Temperature
110 100
200 Heat Flux (W/cm2)

150

80 70 60 50 40

100

50

Power density is not uniformly distributed across the chip Silicon not the best thermal conductor (isotopically pure diamond is) Max junction temperature is determined by hot-spots Impact on packaging, cooling
Amirtharajah/Parkhurst, EEC 118 Spring 2006 18

Temperature (C)

90

Recent Battery Scaling and Future Trends

Battery (40+ lbs)

Battery energy density increasing 8% per year, demand increasing 24% per year (Economist, January 6, 2005)
Amirtharajah/Parkhurst, EEC 118 Spring 2006 19

Why worry about power? Standby Power

Year Power supply Vdd (V) Threshold VT (V) 2002 1.5 0.4 2005 1.2 0.4 2008 0.9 0.35 2011 0.7 0.3 2014 0.6 0.25

Drain leakage will increase as VT decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption.
50%

8KW 1.7KW 400W 88W 12W

and phones leaky!

40%

Standby Power

30%

20%

10%

0% Source: Borkar, De Intel

2000 2002 2004 Amirtharajah/Parkhurst, EEC 118 Spring 2006

2006

2008

20

Emerging Microsensor Applications

Industrial Plants and Power Line Monitoring (courtesy ABB) Operating Room of the Future (courtesy John Guttag)

NASA/JPL sensorwebs Target Tracking & Detection Location Awareness (Courtesy of ARL) (Courtesy of Mark Smith, HP) Websign

Amirtharajah/Parkhurst, EEC 118 Spring 2006

21

Chip Design Styles

Field-Programmable Gate Array (FPGA)
Regular structure. Not all transistors are usable. Programmed via software (configurable wiring)

Gate Array
Regular structure. Higher usage of transistors than FPGA Two step manufacturing process. Diffusion and poly initially. Design must be fairly stable Metal layers fabricated once design is finalized

Cell based design

All transistors used (may have spares to fill in area) Each cell is fixed height so that they can be placed in rows

Full Custom
Highest level of compactness and performance Manually intensive. Not conducive to revision (ECO)
Amirtharajah/Parkhurst, EEC 118 Spring 2006 22

Logic Design Families

Static CMOS Logic Good power delay product (energy) Good noise margin Not as fast as dynamic Dynamic Logic Very fast but inefficient in use of power Domino, CPL, OPL Pass Transistor Logic Poor noise margin Sometimes static power dissipation Less area than static CMOS
Amirtharajah/Parkhurst, EEC 118 Spring 2006 23

Design Parameters
Reliability (Not Dealt with when relating to layout) Factors that dictate reliable operation of the circuit Electromigration, thermal issues, hot electrons, noise margins Performance (Dealt with in this class) Not just measured in clock speed. Power-Delay Product (PDP, equivalent to energy) is a better measure Area (Not Dealt with when relating to layout) Directly affects cost
Amirtharajah/Parkhurst, EEC 118 Spring 2006 24

Current State of the Art

Pentium 4 @ 3.73 GHz (1 or 2 cores/chip going to 4+) 800 - 1066 MHz system bus AGP 8x graphics (533 MHz bus) Memory bus at 533 MHz (DDR) Complex Designs demand resources Design teams resource limited due to logistics and cost Cannot afford to miss issues due to cost of product recall Emphasis on pre-silicon verification as opposed to post silicon testing
Amirtharajah/Parkhurst, EEC 118 Spring 2006 25

Expectations
You should already know Solid State (i.e. PN junctions, semiconductor physics, ..) What we will cover MOS Transistors Fabrication and Equations CMOS logic at the transistor level Sequential logic Memory Arithmetic Circuits Interconnect Framework Course to use power point for the most part Bring PowerPoint slides to class and write notes on them
Amirtharajah/Parkhurst, EEC 118 Spring 2006 26

MOS Transistor Types

Kang & Leblebici Ch. 3 Two transistor types (analogous to bipolar NPN, PNP) NMOS: p-type substrate, n+ source/drain, electrons are charge carriers PMOS: n-type substrate, p+ source/drain, holes are charge carriers
gate N+ source P-substrate bulk (substrate) N+ drain P+ source N-substrate bulk (substrate) gate P+ drain

NMOS
Amirtharajah/Parkhurst, EEC 118 Spring 2006

PMOS
27

MOS Transistor Symbols

NMOS G S D G S D G S
Amirtharajah/Parkhurst, EEC 118 Spring 2006

D B

PMOS G

D B S D

G S D

G S

B
28

Note on MOS Transistor Symbols

All symbols appear in literature Symbols with arrows are conventional in analog papers PMOS with a bubble on the gate is conventional in digital circuits papers Sometimes bulk terminal is ignored implicitly connected to source: NMOS PMOS

Unlike physical bipolar devices, source and drain are usually symmetric
Amirtharajah/Parkhurst, EEC 118 Spring 2006 29

MOS Transistor Structure

Important transistor physical characteristics Channel length L = Lgate 2LD Channel width W Thickness of oxide tox

W tox L

LD
Amirtharajah/Parkhurst, EEC 118 Spring 2006 30

NMOS Transistor I-V Characteristics I

I-V curve vaguely resembles bipolar transistor curves Quantitatively very different Turn-on voltage called Threshold Voltage VT
Amirtharajah/Parkhurst, EEC 118 Spring 2006 31

NMOS Transistor I-V Characteristics II

Drain current varies quadratically with gate-source voltage VGS

Amirtharajah/Parkhurst, EEC 118 Spring 2006 32

MOS Transistor Operation: Cutoff

Simple case: VD = VS = VB = 0 Operates as MOS capacitor (Cg = gate to channel) Transistor in linear region When VGS < VT0, depletion region forms No carriers in channel to connect S and D (Cutoff) Vg < VT0 Vs = 0 Vd = 0 depletion source drain region
P-substrate

VB = 0
Amirtharajah/Parkhurst, EEC 118 Spring 2006 33

MOS Transistor Operation: Inversion

When VGS > VT0, inversion layer forms Source and drain connected by conducting ntype layer (for NMOS) Conducting p-type layer in PMOS Vg > VT0 Vs = 0
source

Vd = 0
drain P-substrate

depletion region

inversion layer
Amirtharajah/Parkhurst, EEC 118 Spring 2006

VB = 0
34

Threshold Voltage Components

Four physical components of the threshold voltage 1. Work function difference between gate and channel (depends on metal or polysilicon gate): GC 2. Gate voltage to invert surface potential: -2F 3. Gate voltage to offset depletion region charge: QB/Cox 4. Gate voltage to offset fixed charges in the gate oxide and oxide-channel interface: Qox/Cox

Cox =

ox
tox

: gate oxide capacitance per unit area

Amirtharajah/Parkhurst, EEC 118 Spring 2006

35

Threshold Voltage Summary

If VSB = 0 (no substrate bias):
VT 0 = GC 2 F QB 0 Qox Cox Cox

(3.20)

If VSB 0 (non-zero substrate bias)

VT = VT 0 +

2 F + VSB 2 F

(3.23)

Body effect (substrate-bias) coefficient:

2qN A Si (3.24) = Cox

Threshold voltage increases as VSB increases!
Amirtharajah/Parkhurst, EEC 118 Spring 2006 36

Threshold Voltage (NMOS vs. PMOS)

NMOS Substrate Fermi potential Depletion charge density Substrate bias coefficient Substrate bias voltage PMOS

F < 0 QB < 0 >0 VSB > 0

F > 0 QB > 0 <0 VSB < 0

37

Amirtharajah/Parkhurst, EEC 118 Spring 2006

Body Effect
Body effect: Source-bulk voltage VSB affects threshold voltage of transistor Body normally connected to ground for NMOS, Vdd (Vcc) for PMOS Raising source voltage increases VT of transistor Implications on circuit design: series stacks of devices

A Vx B VT0
Amirtharajah/Parkhurst, EEC 118 Spring 2006

If Vx > 0, VSB (A) > 0, VT(A) > VTO

38

MOS Transistor Regions of Operation

Three main regions of operation Cutoff: VGS < VT No inversion layer formed, drain and source are isolated by depleted channel. IDS 0 Linear (Triode, Ohmic): VGS > VT, VDS < VGS-VT Inversion layer connects drain and source. Current is almost linear with VDS (like a resistor) Saturation: VGS > VT, VDS VGS-VT Channel is pinched-off. Current saturates (becomes independent of VDS, to first order).

Amirtharajah/Parkhurst, EEC 118 Spring 2006

39

MOSFET Drain Current Overview

Saturation:

ID =

Cox W
2 L

(VGS VT ) (1 + VDS )
2

Linear (Triode, Ohmic):

2 VDS W I D = Cox (VGS VT )VDS L 2

Cutoff:

ID 0

Classical MOSFET model, will discuss deep submicron modifications as necessary (Kang, Eq. 3.54 - 3.59)
Amirtharajah/Parkhurst, EEC 118 Spring 2006 40

A Fourth Region: Subthreshold

Subthreshold:

ID = ISe

VGS n kT q

V DS 1 e kT q

Sometimes called weak inversion region When VGS near VT, drain current has an exponential dependence on gate to source voltage Similar to a bipolar device Not typically used in digital circuits Sometimes used in very low power digital applications Often used in low power analog circuits, e.g. quartz watches
Amirtharajah/Parkhurst, EEC 118 Spring 2006 41

Next Time: MOSFET Details

MOS Structure Derivation of threshold voltage, drain current equations MOSFET Scaling MOSFET Capacitances

Amirtharajah/Parkhurst, EEC 118 Spring 2006

42