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Sync Fifo

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Samy
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64 views9 pages

Sync Fifo

Uploaded by

Samy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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[tmc-fe09@kailash syn_fifo]$ ls

comp.log csrc fifo.v Makefile README simv simv.daidir tb_fifo.v ucli.key


[tmc-fe09@kailash syn_fifo]$ vi tb_fifo.v
[tmc-fe09@kailash syn_fifo]$ ls
comp.log csrc fifo.v Makefile README simv simv.daidir tb_fifo.v ucli.key
[tmc-fe09@kailash syn_fifo]$ make comp
vcs fifo.v tb_fifo.v +v2k -debug_access+pp+f -l comp.log
Chronologic VCS (TM)
Version R-2020.12 -- Mon Mar 28 19:41:24 2022
Copyright (c) 1991-2020 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.


and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'fifo.v'


Parsing design file 'tb_fifo.v'
Top Level Modules:
tb_fifo
No TimeScale specified
Starting vcs inline pass...

1 module and 0 UDP read.


recompiling module tb_fifo
make[1]: Entering directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
make[1]: Leaving directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
make[1]: Entering directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -z notext -m elf_i386 -Bsymbolic -o .//../simv.daidir//_cuarc0.so
objs/amcQw_d.o
rm -f _cuarc0.so
if [ -x ../simv ]; then chmod a-x ../simv; fi
g++ -o ../simv -m32 -m32 -rdynamic -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-
rpath=./simv.daidir -Wl,-rpath=/tools/synopsys/installers/vcs/linux/lib
-L/tools/synopsys/installers/vcs/linux/lib -Wl,-rpath-link=./
_12397_archive_1.so _cuarc0.so SIM_l.o rmapats_mop.o rmapats.o rmar.o
rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lvirsim -lerrorinf -
lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative
/tools/synopsys/installers/vcs/linux/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli
-Wl,-no-whole-archive _vcs_pli_stub_.o
/tools/synopsys/installers/vcs/linux/lib/vcs_save_restore_new.o
/tools/synopsys/installers/verdi/share/PLI/VCS/LINUX/pli.a
/tools/synopsys/installers/vcs/linux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -
ldl
../simv up to date
make[1]: Leaving directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
CPU time: .435 seconds to compile + .600 seconds to elab + .430 seconds to link
[tmc-fe09@kailash syn_fifo]$ ./simv
Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12; Runtime version R-2020.12; Mar 28 19:41 2022
VCD+ Writer R-2020.12 Copyright (c) 1991-2020 by Synopsys Inc.
********* FIFO : Underflow = 0, Overflow = 0 **********

************ WRITING INTO FIFO *************

FIFO WRITE: Data = 16, Address = 0

FIFO WRITE: Data = 15, Address = 1

FIFO WRITE: Data = 14, Address = 2

FIFO WRITE: Data = 13, Address = 3

FIFO WRITE: Data = 12, Address = 4

FIFO WRITE: Data = 11, Address = 5

FIFO WRITE: Data = 10, Address = 6

FIFO WRITE: Data = 9, Address = 7

FIFO WRITE: Data = 8, Address = 8

FIFO WRITE: Data = 7, Address = 9

FIFO WRITE: Data = 6, Address = 10

FIFO WRITE: Data = 5, Address = 11

FIFO WRITE: Data = 4, Address = 12

FIFO WRITE: Data = 3, Address = 13

FIFO WRITE: Data = 2, Address = 14

FIFO WRITE: Data = 1, Address = 15

FIFO WRITE: Data = 1, Address = 0

WRITE ERROR: FIFO IS FULL

********* FIFO : Underflow = 0, Overflow = 1 **********


FIFO WRITE: Data = 1, Address = 0

WRITE ERROR: FIFO IS FULL

************ READING FIFO *************

FIFO READ: Address = 0,


********* FIFO : Underflow = 0, Overflow = 0 **********
FIFO READ: Data = 16

FIFO READ: Address = 1,


FIFO READ: Data = 15

FIFO READ: Address = 2,


FIFO READ: Data = 14

FIFO READ: Address = 3,


FIFO READ: Data = 13

FIFO READ: Address = 4,


FIFO READ: Data = 12

FIFO READ: Address = 5,


FIFO READ: Data = 11

FIFO READ: Address = 6,


FIFO READ: Data = 10

FIFO READ: Address = 7,


FIFO READ: Data = 9

FIFO READ: Address = 8,


FIFO READ: Data = 8

FIFO READ: Address = 9,


FIFO READ: Data = 7

FIFO READ: Address = 10,


FIFO READ: Data = 6

FIFO READ: Address = 11,


FIFO READ: Data = 5

FIFO READ: Address = 12,


FIFO READ: Data = 4

FIFO READ: Address = 13,


FIFO READ: Data = 3

FIFO READ: Address = 14,


FIFO READ: Data = 2

FIFO READ: Address = 15,


FIFO READ: Data = 1

FIFO READ: Address = 0,


READ ERROR: FIFO IS EMPTY

********* FIFO : Underflow = 1, Overflow = 0 **********


FIFO READ: Data = 1

FIFO READ: Address = 0,


READ ERROR: FIFO IS EMPTY

FIFO READ: Data = 1

FIFO WRITE: Data = 0, Address = 0

********* FIFO : Underflow = 0, Overflow = 0 **********


FIFO WRITE: Data = 1, Address = 1
FIFO READ: Address = 0,
FIFO READ: Data = 0

FIFO READ: Address = 1,


FIFO READ: Data = 1

FIFO WRITE: Data = 2, Address = 2

FIFO WRITE: Data = 3, Address = 3

FIFO WRITE: Data = 8, Address = 4

FIFO READ: Address = 2,


FIFO READ: Data = 2

$finish called from file "tb_fifo.v", line 116.


$finish at simulation time 955
V C S S i m u l a t i o n R e p o r t
Time: 955
CPU Time: 0.790 seconds; Data structure size: 0.0Mb
Mon Mar 28 19:41:31 2022
[tmc-fe09@kailash syn_fifo]$ ls
comp.log csrc fifo.v Makefile README simv simv.daidir tb_fifo.v ucli.key
vcdplus.vpd
[tmc-fe09@kailash syn_fifo]$ dve &
[1] 12726
[tmc-fe09@kailash syn_fifo]$
Error-[DVAP021] DVE
Cannot connect to X server.
Please check your DISPLAY setting.

-------------------------------------------
login as: tmc-fe09
[email protected]'s password:
Last login: Mon Mar 28 19:48:46 2022 from 192.168.0.1
[tmc-fe09@kailash ~]$ ls
tmc-fe09-Shriniket tmc-fe09-Suresh_Kumar
[tmc-fe09@kailash ~]$ cd tmc-fe09-Sh
-bash: cd: tmc-fe09-Sh: No such file or directory
[tmc-fe09@kailash ~]$ cd tmc-fe09-Shriniket/
[tmc-fe09@kailash tmc-fe09-Shriniket]$ cd
Synopsys_examples/basic-hdl/verilog/syn_fifo/
[tmc-fe09@kailash syn_fifo]$ ls
comp.log csrc DVEfiles fifo.v Makefile README simv simv.daidir tb_fifo.v
ucli.key vcdplus.vpd
[tmc-fe09@kailash syn_fifo]$ csh
[tmc-fe09@kailash syn_fifo]$ ls
comp.log csrc DVEfiles fifo.v Makefile README simv simv.daidir tb_fifo.v
ucli.key vcdplus.vpd
[tmc-fe09@kailash syn_fifo]$ make comp
vcs fifo.v tb_fifo.v +v2k -debug_access+pp+f -l comp.log
Chronologic VCS (TM)
Version R-2020.12 -- Mon Mar 28 19:56:32 2022
Copyright (c) 1991-2020 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.


and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'fifo.v'


Parsing design file 'tb_fifo.v'
Top Level Modules:
tb_fifo
No TimeScale specified
Starting vcs inline pass...

1 module and 0 UDP read.


However, due to incremental compilation, no re-compilation is necessary.
make[1]: Entering directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
make[1]: Leaving directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
make[1]: Entering directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -z notext -m elf_i386 -Bsymbolic -o .//../simv.daidir//_cuarc0.so
objs/amcQw_d.o
rm -f _cuarc0.so
if [ -x ../simv ]; then chmod a-x ../simv; fi
g++ -o ../simv -m32 -m32 -rdynamic -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-
rpath=./simv.daidir -Wl,-rpath=/tools/synopsys/installers/vcs/linux/lib
-L/tools/synopsys/installers/vcs/linux/lib -Wl,-rpath-link=./
_17273_archive_1.so _prev_archive_1.so _cuarc0.so SIM_l.o rmapats_mop.o
rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lvirsim -
lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative
/tools/synopsys/installers/vcs/linux/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli
-Wl,-no-whole-archive _vcs_pli_stub_.o
/tools/synopsys/installers/vcs/linux/lib/vcs_save_restore_new.o
/tools/synopsys/installers/verdi/share/PLI/VCS/LINUX/pli.a
/tools/synopsys/installers/vcs/linux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -
ldl
../simv up to date
make[1]: Leaving directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
CPU time: .417 seconds to compile + .575 seconds to elab + .416 seconds to link
[tmc-fe09@kailash syn_fifo]$ make all
\rm -rf simv* csrc* *.log
vcs fifo.v tb_fifo.v +v2k -debug_access+pp+f -l comp.log
Chronologic VCS (TM)
Version R-2020.12 -- Mon Mar 28 19:56:47 2022
Copyright (c) 1991-2020 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.


and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'fifo.v'


Parsing design file 'tb_fifo.v'
Top Level Modules:
tb_fifo
No TimeScale specified
Starting vcs inline pass...

1 module and 0 UDP read.


recompiling module tb_fifo
make[1]: Entering directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
make[1]: Leaving directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
make[1]: Entering directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../simv ]; then chmod a-x ../simv; fi
g++ -o ../simv -m32 -m32 -rdynamic -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-
rpath=./simv.daidir -Wl,-rpath=/tools/synopsys/installers/vcs/linux/lib
-L/tools/synopsys/installers/vcs/linux/lib -Wl,-rpath-link=./ objs/amcQw_d.o
_17775_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o
rmar_llvm_0_1.o rmar_llvm_0_0.o -lvirsim -lerrorinf -lsnpsmalloc -lvfs
-lvcsnew -lsimprofile -luclinative
/tools/synopsys/installers/vcs/linux/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli
-Wl,-no-whole-archive _vcs_pli_stub_.o
/tools/synopsys/installers/vcs/linux/lib/vcs_save_restore_new.o
/tools/synopsys/installers/verdi/share/PLI/VCS/LINUX/pli.a
/tools/synopsys/installers/vcs/linux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -
ldl
../simv up to date
make[1]: Leaving directory
`/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/basic-hdl/verilog/syn_fifo/
csrc'
CPU time: .402 seconds to compile + .576 seconds to elab + .413 seconds to link
simv -l run.log
make: execvp: simv: Permission denied
make: *** [run] Error 127
[tmc-fe09@kailash syn_fifo]$ ./simv
Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12; Runtime version R-2020.12; Mar 28 19:56 2022
VCD+ Writer R-2020.12 Copyright (c) 1991-2020 by Synopsys Inc.
********* FIFO : Underflow = 0, Overflow = 0 **********

************ WRITING INTO FIFO *************

FIFO WRITE: Data = 16, Address = 0

FIFO WRITE: Data = 15, Address = 1

FIFO WRITE: Data = 14, Address = 2

FIFO WRITE: Data = 13, Address = 3

FIFO WRITE: Data = 12, Address = 4

FIFO WRITE: Data = 11, Address = 5

FIFO WRITE: Data = 10, Address = 6


FIFO WRITE: Data = 9, Address = 7

FIFO WRITE: Data = 8, Address = 8

FIFO WRITE: Data = 7, Address = 9

FIFO WRITE: Data = 6, Address = 10

FIFO WRITE: Data = 5, Address = 11

FIFO WRITE: Data = 4, Address = 12

FIFO WRITE: Data = 3, Address = 13

FIFO WRITE: Data = 2, Address = 14

FIFO WRITE: Data = 1, Address = 15

FIFO WRITE: Data = 1, Address = 0

WRITE ERROR: FIFO IS FULL

********* FIFO : Underflow = 0, Overflow = 1 **********


FIFO WRITE: Data = 1, Address = 0

WRITE ERROR: FIFO IS FULL

************ READING FIFO *************

FIFO READ: Address = 0,


********* FIFO : Underflow = 0, Overflow = 0 **********
FIFO READ: Data = 16

FIFO READ: Address = 1,


FIFO READ: Data = 15

FIFO READ: Address = 2,


FIFO READ: Data = 14

FIFO READ: Address = 3,


FIFO READ: Data = 13

FIFO READ: Address = 4,


FIFO READ: Data = 12

FIFO READ: Address = 5,


FIFO READ: Data = 11

FIFO READ: Address = 6,


FIFO READ: Data = 10

FIFO READ: Address = 7,


FIFO READ: Data = 9

FIFO READ: Address = 8,


FIFO READ: Data = 8

FIFO READ: Address = 9,


FIFO READ: Data = 7

FIFO READ: Address = 10,


FIFO READ: Data = 6

FIFO READ: Address = 11,


FIFO READ: Data = 5

FIFO READ: Address = 12,


FIFO READ: Data = 4

FIFO READ: Address = 13,


FIFO READ: Data = 3

FIFO READ: Address = 14,


FIFO READ: Data = 2

FIFO READ: Address = 15,


FIFO READ: Data = 1

FIFO READ: Address = 0,


READ ERROR: FIFO IS EMPTY

********* FIFO : Underflow = 1, Overflow = 0 **********


FIFO READ: Data = 1

FIFO READ: Address = 0,


READ ERROR: FIFO IS EMPTY

FIFO READ: Data = 1

FIFO WRITE: Data = 0, Address = 0

********* FIFO : Underflow = 0, Overflow = 0 **********


FIFO WRITE: Data = 1, Address = 1

FIFO READ: Address = 0,


FIFO READ: Data = 0

FIFO READ: Address = 1,


FIFO READ: Data = 1

FIFO WRITE: Data = 2, Address = 2

FIFO WRITE: Data = 3, Address = 3

FIFO WRITE: Data = 8, Address = 4

FIFO READ: Address = 2,


FIFO READ: Data = 2

$finish called from file "tb_fifo.v", line 116.


$finish at simulation time 955
V C S S i m u l a t i o n R e p o r t
Time: 955
CPU Time: 0.790 seconds; Data structure size: 0.0Mb
Mon Mar 28 19:56:58 2022
[tmc-fe09@kailash syn_fifo]$ ls
comp.log csrc DVEfiles fifo.v Makefile README simv simv.daidir tb_fifo.v
ucli.key vcdplus.vpd
[tmc-fe09@kailash syn_fifo]$ dve &
[1] 18096
[tmc-fe09@kailash syn_fifo]$
Error-[DVAP021] DVE
Cannot connect to X server.
Please check your DISPLAY setting.

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