Chapter 4:

Manufacturing process of BJT

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Introduction
oThe BJT technology is classified into two main subcategories;
◦ NPN Transistor

◦ PNP Transistor

o The first step in manufacturing process of monolithic IC’s is crystal growth.

o When we want to realize a silicon bipolar junction transistor, we start with a p-type single crystal
oriented (1,1,1) and with a resistivity of 10 ohms centimeter.

oThese are usual, the most common starting substrate specification, when you want to fabricate an
npn bipolar junction transistor.

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Oxidation
o Silicon di-oxide will mask against the doping. So silicon dioxide has excellent insulating
properties, dielectric properties, and masking properties which brings us next step namely the
oxidation.

o One we have oxidized the silicon substrate it looks like a transparent glass like layer on the
single crystal substrate and it also shows different color. Depending on the thickness of the
oxide the color will be blue, green or pink…etc.

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 Photoresist
o Spin on photoresist
o Photoresist is a light-sensitive organic polymer

o Softens where exposed to light

o At first we put the photosensitive material or photo resist on the entire substrate then we bring this
photo resist coated substrate in contact with a mask.

o Mask is a simple glass plate with patterns. Then we subject it to a particular radiation. U-V radiation is
most commonly used radiations.

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 Lithography
oExpose photoresist through n-well mask
o Strip off exposed photoresist

o We know that photo resist is a light sensitive material so through the transparent radians of the mask
this photo resist is exposed to the U-V light radiations and it properties changed it become soft or easy
to remove those portions.

o The rest portion the photo resist is hard and it is difficult to remove so it is going to protect the
underline oxide layer. Photoresist
SiO2

p substrate

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 Etch
o Then our subject is to etching, for etching of oxide we put it in hydrofluoric acid solution which can
etch silicon di-oxide while preserving a silicon substrate. So when this is put in hydrofluoric acid
solution only oxide portion will remove.

Photoresist
SiO2

p substrate

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 Strip Photoresist
o And then we can remove the remaining photo resist using trichloroethylene from the rest of the
portions. This term is called opening of a window in the oxide. We have opened a window in the oxide.

o After we have realized this window pattern the next step will be to dope through the window (the
region where the oxide is not present) and we usually do diffusion process (N+) (N+ is very heavily
doped N region).

o This particular diffusion incidentally is called buried layer diffusion. This N+ layer diffusion usually
the dopant used for this is antimony or arsenic.
SiO2

p substrate

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 Diffusion or Ion implantation
o n-well is formed with diffusion or ion implantation

o Diffusion
o Place wafer in furnace with arsenic gas

o Heat until As atoms diffuse into exposed Si

o Ion Implanatation
o Blast wafer with beam of As ions

o Ions blocked by SiO2, only enter exposed Si

SiO2

n well

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 Strip Oxide
o Strip off the remaining oxide using HF

o Back to bare wafer with n-well

o Subsequent steps involve similar series of steps

Etching

Diffusion (Ion
Implantation)

n well
p substrate

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Epitaxi
o Growing n layer the n+ layer diffuses layer out of this and the structure looks like the
following figure:

o Now we have a p type substrate, n+ buried layer diffusion and on the top n epitaxial layer.

o This in epitaxial layer is going to be the collector of the n-p-n transistor and the n+ buried
layer diffusion is done in order to reduce the collector resistance.

p type substrate

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Continue…
o Now this n epitaxial layer is going to be the collector of the bipolar junction transistor,
obviously we are not going to have just one transistor in this entire silicon chip, we are going
to have thousands of transistors. The collectors are shorted together because all of them are
housed in the same epitaxial region.

o We do not want this condition. Because we do not know what kind of circuit we made, if we
were making discrete transistors then this problem is not come in front of us because we cut
individual transistor, but in case of integrated circuit everything such as passive components,
interconnections, active components etc. is housed in the same chip then we can’t allow that
all the collectors are shorted together.

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Continue…
o So this is one important criteria of integrated technology that is to provide isolation between

adjacent devices.

o So we must concentrate the scheme to adjacent the devices. The oldest technology for

isolation between transistors, use is a reverse bias p-n junction.

o We know a reverse bias p-n junction is a blocking contact. It’s not allows the flow of current

between two transistors.

o In this case we generally call this process p-n junction isolation.

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Continue…
o In this process we protect the active region by means of an oxide and dope by p+ diffusion. It
is very important that this doping (p+) comes all the way to the p-type substrates.

o Then we get that our transistor are isolated to each other.

o In figure we can clearly see that two transistor are isolated from each other through reversed
bias p+ junction it means current can not flow through this reverse bias p+ junction.

o One main thing in this process is that the substrate is connected to the most –ve point of the
supply. This process is called p-n isolation.

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Continue…
o The main precaution point of this process is that the selectivity diffused this p+ region.

o The top view of mask for this p+ region is shown:

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Continue…
o The previous figure tells us that the p+ dopant enter only through outer region or surrounding the
active region of our transistor. The active region is marked by n+ barred layer diffusion. So right
now we realize the collector.

o The next task is to realize the base and emitter.

o The base is doped earlier then emitter because the emitter is more highly doped as compare to the
base.

o So at first we will concentrate on base doping. For this purpose all we have to do now is to have a
p region. P region used doping for the base.

o The doping for the base region is shown in the next figure.

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 Continue…
o In order to realize a p region oxidation, photolithography, etching and diffusion. These all process are
used almost in every stage processing or in other words we can say that these process step are repeated.

o The base region is located within the active region mask. The top view is this is shown in the next
figure.

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Continue…
o In the above figure, base is actually located within the active region mask, only base region
will be transparent when we are going to have the mask for the base.

o So we have realized the base. Now we will focus on the realization of emitter. Within the base
window we have the emitter region.

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 Continue…
o The object view and top view of the mask for realization of this is shown in the following figures:

o When we are going for emitter doping we also have a small n region in order to facilitate taking contact from the
collector region.

Doping for Emitter Realization

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 Continue…
o In figure our collector is n, this is epitaxial n region, it is lightly doped n region. So in order to take

contact from that lightly doped n region we want to reduce contact resistance it is difficult to have a

proper ohmic contact to a lightly doped n region.

o So the usual practice is we have a small pocket of n+ diffusion for collector contact.

o This small pocket for collector contact is shown in above figure. This needs no extra step. This can be

done along with the emitter diffusion.

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 Continue…
o This pocket box is present inside the active region.

o So the transistor is almost ready we have realized the emitter, base, collector, and isolation between

adjacent devices. The remaining part of this process is to establish the contact with the outside world.

This is done by a technique is called contact metallization.

o This metallization needs selective deposition of metal over the base, emitter and collector region. That

is when we use the term of selective we take help for this by using photolithography process. Because

for this purpose we also must have masks.

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Continue…
o The aluminum material is used usually for contacting purpose in VLSI. Aluminum is also a
group three element it means aluminum would actually dope silicon p type. So when we are
contacting in p region the use of aluminum is very easy. The aluminum makes it p+ therefore
the contact resistance is going to be very small.

o The situation is very tuff when we have a n region, however if we have a heavily doped n+
region it’s not a problem because it is good enough for ohmic contact. The only problem when
we have lightly doped n region so for the solution purpose we use a n+ pocket for taking
collector contacts.

o For metallization process we will also require masks; the final contact diagram and the mask
is shown in the next slide.
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 Continue…
o So these are the simple steps we need to realize a bipolar junction transistor.

Contact Diagram of Final Transistor Top view of Mask for Metallization Purpose

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PNP Transistors
▪ The integrated PNP transistors are fabricated in one of the following three structures:
✓ Substrate or vertical PNP
✓ Lateral or horizontal PNP
✓ Triple diffused PNP

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Substrate or vertical PNP
The p-substrate of the IC is used as the collector, the N-epitaxial layer is used as the base and the
next P-diffusion is used as the emitter region of the PNP transistor.

The collector region of transistor structure is formed in parallel with the emitter region of the PNP
transistor. The structure of a vertical monolithic PNP transistor is shown in the next figure.

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 Vertical pnp BJT

Base Emitter Collector

n+ buried collector implant

This has the advantage that it can be fabricated simultaneously with the processing steps of an
NPN transistor and therefore it requires as the base of the PNP transistor.

During the P-type base diffusion process of NPN transistor, two parallel P-regions are formed
which make the emitter and collector regions of the horizontal PNP transistor.

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 Lateral pnp BJT
BE E C CB

Lateral pnp BJT

▪ This is called a triple diffusion process, because it involves an additional diffusion of P-region
in the second N-diffusion region of a NPN transistor.

▪ The structure of the triple diffused monolithic PNP transistor Q2 is also shown in the figure.

▪ This has the limitations of requiring additional fabrication steps and sophisticated fabrication
assemblies.

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Continue…

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Comparison of monolithic NPN and PNP transistor
✓ Normally, the NPN transistor is preferred in monolithic circuits due to the following
reasons:

✓ The vertical PNP transistor must have his collector held at a fixed negative voltage.

✓ The lateral PNP transistor has very wide base region and has the limitation due to the
lateral diffusion of P-type impurities into the N-type base region.

✓ This makes the photographic mask making, alignment and etching processes very difficult.

✓ This reduces the current gain of lateral PNP transistors as low as 1.5 to 30 as against 50 to
300 for a monolithic NPN transistor.

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 The End of Chapter 4

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