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L6714
4 phase controller with embedded drivers
for Intel VR10, VR11 and AMD 6Bit CPUs

Features
■ 0.5% output voltage accuracy
■ 7/8 bit programmable output up to 1.60000V -
Intel VR10.x, VR11 DAC
■ 6 bit programmable output up to 1.5500V -
AMD 6Bit DAC
TQFP64 (Exposed Pad)
■ High current integrated gate drivers
■ Full differential current sensing across inductor
or low side MOSFET
■ Embedded VRD thermal monitor Description
■ Integrated remote sense buffer L6714 implements a four phase step-down
■ Dynamic VID management controller with 90º phase-shift between each
phase with integrated high current drivers in a
■ Adjustable reference voltage offset
compact 10mm x 10mm body package with
■ Programmable Soft-Start exposed pad.
■ Low-Side-Less startup The device embeds selectable DACs: the output
■ Programmable over voltage protection voltage ranges up to 1.60000V (both Intel VR10.x
■ Preliminary over voltage and VR11 DAC) or up to 1.5500V (AMD 6Bit
DAC) managing D-VID with ±0.5% output voltage
■ Constant over current protection accuracy over line and temperature variations.
■ Oscillator internally fixed at 150kHz externally Additional programmable offset can be added to
adjustable the reference voltage with a single external
■ Output enable resistor.

■ SS_END / PGOOD signal The controller assures fast protection against load
over current and under / over voltage (in this last
■ TQFP64 10mm x 10mm package
case also before UVLO). In case of over-current
with Exposed Pad
the system works in Constant Current mode until
UVP.
Application
Selectable current reading adds flexibility to the
■ High current VRD for desktop CPUs
design allowing current sense across inductor or
■ Workstation and server CPU power supply LS MOSFET.
■ VRM modules System Thermal Monitor is also provided allowing
system protection from over-temperature
conditions.
Order codes
Part number Package Packaging

L6714 TQFP64 Tube

L6714TR TQFP64 Tape and reel

November 2006 Rev 3 1/70

www.st.com 70
Contents L6714

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Mapping for the Intel VR11 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Voltage Identification (VID) for Intel VR11 mode . . . . . . . . . . . . . . . . . . . 17
5.3 Voltage Identifications (VID) for Intel VR10 mode + 6.25mV . . . . . . . . . . 19
5.4 Mapping for the AMD 6BIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5 Voltage identifications (VID) codes for AMD 6BIT mode . . . . . . . . . . . . . 21

6 Reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8 Configuring the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.1 DAC selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10 Current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . 32

10.1 Low side current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.2 Inductor current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11 Remote voltage sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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L6714 Contents

12 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
12.1 Droop function (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.2 Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

13 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

14 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

15 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
15.1 Intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
15.2 AMD mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15.3 Low-Side-Less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

16 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 47

16.1 Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
16.2 Preliminary over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
16.3 Over voltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
16.4 PGOOD (Only for AMD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

17 Maximum Duty-cycle limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

18 Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

18.1 Low side MOSFET sense over current . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
18.2 Inductor sense over current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

19 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

20 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

21 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

21.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

22 Thermal monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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Contents L6714

23 Tolerance band (TOB) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

23.1 Controller tolerance (TOB controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
23.2 Ext. current sense circuit tolerance
(TOB CurrSense - Inductor Sense) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
23.3 Time constant matching error tolerance (TOB TCMatching) . . . . . . . . . . 63
23.4 Temperature measurement error (VTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 63

24 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
24.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
24.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 65

25 Embedding L6714 - Based VR... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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L6714 Block diagram

1 Block diagram

Figure 1. L6714 block diagram

VCCDR1

VCCDR2

VCCDR3

VCCDR4
PHASE1

PHASE2

PHASE3

PHASE4
UGATE1

UGATE2

UGATE3

UGATE4
LGATE1

LGATE2

LGATE3

LGATE4
PGND1

PGND2

PGND3

PGND4
BOOT1

BOOT2

BOOT3

BOOT4
VR_HOT
SS_END / PGOOD

HS1 HS1 HS2 LS2 HS3 LS3 HS4 LS4

VR_FAN
LOGIC PWM LOGIC PWM LOGIC PWM LOGIC PWM
ADAPTIVE ANTI ADAPTIVE ANTI ADAPTIVE ANTI ADAPTIVE ANTI
CROSS CONDUCTION CROSS CONDUCTION CROSS CONDUCTION CROSS CONDUCTION

3.600V
CURRENT SHARING CURRENT SHARING CURRENT SHARING CURRENT SHARING
CORRECTION CORRECTION CORRECTION CORRECTION
OSC / FAULT
OSCILLATOR
4 PHASE

TM
PWM1 PWM2 PWM3 PWM4

3.200V
SS_OSC / REF

CS_SEL
PWM1 PWM2 PWM3 PWM4

CURRENT
AVERAGE
DIGITAL CS1-
SOFT START CH1 CURRENT
VCC OCP1 CS1+
READING
VCCDR L6714 OCP2
OCP1 CS_SEL
OUTEN CONTROL LOGIC OCP3

VID0 DAC/CS_SEL AND PROTECTIONS OCP4 CS2-

CH2 CURRENT
VID1 READING CS2+
IOFFSET

IDROOP
WITH DYNAMIC

VID2
VID CONTROL

OFFSET CS_SEL OCP2 CS_SEL

VID3
DAC

VID4 TOTAL DELIVERED CURRENT CS3-

CH3 CURRENT
VID5 READING CS3+
+150mV / 1.800V / OVP
VID6
64k OCP3 CS_SEL
VID7 / D-VID OVP
COMPARATOR
64k CS4-
VID_SEL ERROR CH4 CURRENT
12.5µA

12.5µA
AMPLIFIER READING CS4+
1.240V
REMOTE 64k OCP4
IOFFSET

BUFFER
64k VCC SGND
OUTEN OUTEN OVP DAC / CS_SEL
COMP

FB

DROOP

OFFSET

VSEN

FBR
FBG

OVP

DAC / CS_SEL

VCC

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Pin settings L6714

2 Pin settings

2.1 Connections
Figure 2. Pin connection (Through top view)

SS_END / PGOOD

OSC / FAULT
VID7 / D-VID

VID_SEL
VR_HOT
VR_FAN

VID0
VID1
VID2
VID3
VID4
VID5
VID6

OVP
FBG
FBR
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TM 49 32 OFFSET
SGND 50 31 CS1-
VCCDR4 51 30 CS1+
LGATE4 52 29 CS3-
PGND4 53 28 CS3+
PGND2 54 27 CS2-
LGATE2 55 26 CS2+
VCCDR2 56 25 CS4-
VCCDR3 57 L6714 24 CS4+
LGATE3 58 23 COMP
PGND3 59 22 FB
PGND1 60 21 DROOP
LGATE1 61 20 VSEN
VCCDR1 62 19 SGND
PHASE1 63 18 SSOSC / REF
N.C. 64 17 OUTEN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
UAGTE1
BOOT1
N.C.
PHASE3
UGATE3
BOOT3
N.C.
PHASE2
UGATE2
BOOT2
N.C.
PHASE4
UGATE4
BOOT4
VCC
DAC / CS_SEL

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L6714 Pin settings

2.2 Functions

Table 1. Pin functions

N° Pin Function

Channel 1 HS driver output.

1 UGATE1
A small series resistors helps in reducing device-dissipated power.
Channel 1 HS driver supply.
Connect through a capacitor (100nF typ.) to PHASE1 and provide necessary
2 BOOT1 Bootstrap diode.
A small resistor in series to the boot diode helps in reducing Boot capacitor
overcharge.
3 N.C. Not internally connected.
Channel 3 HS driver return path.
4 PHASE3 It must be connected to the HS3 mosfet source and provides return path for the
HS driver of channel 3.
Channel 3 HS driver output.
5 UGATE3
A small series resistors helps in reducing device-dissipated power.
Channel 3 HS driver supply.
Connect through a capacitor (100nF typ.) to PHASE3 and provide necessary
6 BOOT3 Bootstrap diode.
A small resistor in series to the boot diode helps in reducing Boot capacitor
overcharge.
7 N.C. Not internally connected.
Channel 2 HS driver return path.
8 PHASE2 It must be connected to the HS2 mosfet source and provides return path for the
HS driver of channel 2.
Channel 2 HS driver output.
9 UGATE2
A small series resistors helps in reducing device-dissipated power.
Channel 2 HS driver supply.
Connect through a capacitor (100nF typ.) to PHASE2 and provide necessary
10 BOOT2 Bootstrap diode.
A small resistor in series to the boot diode helps in reducing Boot capacitor
overcharge.
11 N.C. Not internally connected.
Channel 4 HS driver return path.
12 PHASE4 It must be connected to the HS4 mosfet source and provides return path for the
HS driver of channel 4.
Channel 4 HS driver output.
13 UGATE4
A small series resistors helps in reducing device-dissipated power.
Channel 4 HS driver supply.
Connect through a capacitor (100nF typ.) to PHASE4 and provide necessary
14 BOOT4 Bootstrap diode.
A small resistor in series to the boot diode helps in reducing Boot capacitor
overcharge.

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Pin settings L6714

Table 1. Pin functions

N° Pin Function

Device supply voltage. The operative voltage is 12V ±15%. Filter with 1µF (typ)
15 VCC
MLCC vs. SGND.
DAC and Current Sense SELection Pin.
This pin sources a constant 12.5µA current. By connecting a resistor vs. SGND
it is possible to select between Intel and AMD integrated DACs and Current
DAC/ Sense methods.
16
CS_SEL
Filter with 100pF(max) vs. SGND.
DACs and Current Sense methods cannot be changed dynamically.
See “DAC selection” Section and See Table 10 for details.
OUTput ENable Pin.
Forced low, the device stops operations with all MOSFET OFF: all the
protections are disabled except for Section 16.2: Preliminary over voltage on
17 OUTEN page 47.
Set free, the device starts-up implementing soft-start up to the selected VID
code.
Cycle this pin to recover latch from protections; filter with 1nF (typ) vs. SGND.
Intel Mode. Soft Start OSCillator Pin.
By connecting a resistor RSSOSC vs. SGND, it allows programming the frequency
FSS of an internal additional oscillator that drives the reference during Soft-Start.
Setting this frequency allows programming the Soft-Start time TSS proportionally
SSOSC/
18 to the RSSOSC connected with a gain of 20.1612 [µs / kΩ]. The same slope
REF
implemented to reach VBOOT has to be considered also when the reference
moves from VBOOT to the programmed VID code. See “Soft start” Section for
details.
AMD Mode. REFerence Output. Filter with 47Ω - 4.7nF vs. SGND.
All the internal references are referred to this pin. Connect to the PCB Signal
19 SGND
Ground.
Remote Buffer Output, it manages OVP and UVP protections and PGOOD
20 VSEN (when applicable). See “Output voltage monitor and protections” Section and
See Table 10 for details.
A current proportional to the total current read is sourced from this pin according
to the Current Reading Gain.
Short to FB to implement Droop Function or Short to SGND to disable the
21 DROOP
function.Connecting to SGND through a resistor and filtering with a capacitor,
the current info can be used for other purposes.
See “Droop function (Optional)” Section
Error Amplifier Inverting Input. Connect with a resistor RFB vs. VSEN and with an
22 FB
RF - CF vs. COMP.
Error Amplifier Output. Connect with an RF - CF vs. FB.
23 COMP
The device cannot be disabled by pulling down this pin.
Channel 4 Current Sense Positive Input.
LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source.
24 CS4+ Inductor DCR Sense: connect through an R-C filter to the phase-side of the
channel 4 inductor.
See “Layout guidelines” Section for proper layout of this connection.

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L6714 Pin settings

Table 1. Pin functions

N° Pin Function

Channel 4 Current Sense Negative Input.

LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain.
25 CS4- Inductor DCR Sense: connect through a Rg resistor to the output-side of the
channel 4 inductor.
See “Layout guidelines” Section for proper layout of this connection.
Channel 2 Current Sense Positive Input.
LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source.
26 CS2+ Inductor DCR Sense: connect through an R-C filter to the phase-side of the
channel 2 inductor.
See “Layout guidelines” Section for proper layout of this connection.
Channel 2 Current Sense Negative Input.
LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain.
27 CS2- Inductor DCR Sense: connect through a Rg resistor to the output-side of the
channel 2 inductor.
See “Layout guidelines” Section for proper layout of this connection.
Channel 3 Current Sense Positive Input.
LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source.
28 CS3+ Inductor DCR Sense: connect through an R-C filter to the phase-side of the
channel 3 inductor.
See “Layout guidelines” Section for proper layout of this connection.
Channel 3 Current Sense Negative Input.
LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain.
29 CS3- Inductor DCR Sense: connect through a Rg resistor to the output-side of the
channel 3 inductor.
See “Layout guidelines” Section for proper layout of this connection.
Channel 1 Current Sense Positive Input.
LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source.
30 CS1+ Inductor DCR Sense: connect through an R-C filter to the phase-side of the
channel 1 inductor.
See “Layout guidelines” Section for proper layout of this connection.
Channel 1 Current Sense Negative Input.
LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain.
31 CS1- Inductor DCR Sense: connect through a Rg resistor to the output-side of the
channel 1 inductor.
See “Layout guidelines” Section for proper layout of this connection.
Offset Programming Pin.
Internally fixed at 1.240V, connecting a ROFFSET resistor vs. SGND allows
32 OFFSET setting a current that is mirrored into FB pin in order to program a positive offset
according to the selected RFB. Short to SGND to disable the function.
See “Offset (Optional)” Section for details.

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Pin settings L6714

Table 1. Pin functions

N° Pin Function

Over Voltage Programming Pin. Internally pulled up by 12.5µA(typ) to 5V.

Set free to use built-in protection thresholds as reported into Table 10.
33 OVP Connect to SGND through a ROVP resistor and filter with 100pF (max) to set the
OVP threshold to a fixed voltage according to the ROVP resistor.
See “Over voltage and programmable OVP” Section Section for details.
Intel Mode.
It allows selecting between VR10 (short to SGND, Table 7) or VR11
34 VID_SEL (floating,Table 6 ) DACs ,internally pulled up by 12.5µA (typ.).. See “Configuring
the device” Section for details.
AMD Mode. Not Applicable. Needs to be shorted to SGND.
Remote Buffer Non Inverting Input.
35 FBR Connect to the positive side of the load to perform remote sense.
See “Layout guidelines” Section for proper layout of this connection.
Remote Buffer Inverting Input.
36 FBG Connect to the negative side of the load to perform remote sense.
See “Layout guidelines” Section for proper layout of this connection.
Oscillator Pin.
It allows programming the switching frequency FSW of each channel: the
equivalent switching frequency at the load side results in being multiplied by the
phase number N.
OSC/
37 Frequency is programmed according to the resistor connected from the pin vs.
FAULT
SGND or VCC with a gain of 6kHz/µA (see relevant section for details). Leaving
the pin floating programs a switching frequency of 150kHz per phase.
The pin is forced high (5V) to signal an OVP FAULT: to recover from this
condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details.
VID7 - Intel Mode. See VID5 to VID0 Section.
DVID - AMD Mode. DVID Output.
VID7/
38 CMOS output pulled high when the controller is performing a D-VID transition
DVID
(with 32 clock cycle delay after the transition has finished). See “Dynamic VID
transitions” Section Section for details.
Intel Mode. See VID5 to VID0 Section.
39 VID6
AMD Mode. Not Applicable. Need to be shorted to SGND.
Intel Mode. Voltage IDentification Pins (also applies to VID6, VID7).
Internally pulled up by 25µA to 5V, connect to SGND to program a '0' or leave
floating to program a '1'.
They allow programming output voltage as specified in Table 6 and Table 7
according to VID_SEL status. OVP and UVP protection comes as a
consequence of the programmed code (See Table 10).
40 to VID5 to
AMD Mode. Voltage IDentification Pins.
45 VID0
Internally pulled down by 12.5µA, leave floating to program a '0' while pull up to
more than 1.4V to program a '1'.
They allow programming the output voltage as specified in Table 9 on page 21
(VID7 doesn’t care). OVP and UVP protection comes as a consequence of the
programmed code (See Table 10).
Note. VID6 not used, need to be shorted to SGND.

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L6714 Pin settings

Table 1. Pin functions

N° Pin Function

SSEND - Intel Mode. Soft Start END Signal.

Open Drain Output set free after SS has finished and pulled low when triggering
any protection. Pull up to a voltage lower than 5V (typ), if not used it can be left
SS_END/ floating.
46
PGOOD PGOOD - AMD Mode.
Open Drain Output set free after SS has finished and pulled low when VSEN is
lower than the relative threshold. Pull up to a voltage lower than 5V (typ), if not
used it can be left floating.
Voltage Regulator HOT. Over Temperature Alarm Signal.
Open Drain Output, set free when TM overcomes the Alarm Threshold.
47 VR_HOT
Thermal Monitoring Output enabled if Vcc > UVLOVCC.
See “Thermal monitor” Section for details and typical connections.
Voltage Regulator FAN. Over Temperature Warning Signal.
Open Drain Output, set free when TM overcomes the Warning Threshold.
48 VR_FAN
Thermal Monitoring Output enabled if Vcc > UVLOVCC.
See “Thermal monitor” Section for details and typical connections.
Thermal Monitor Input.
It senses the regulator temperature through apposite network and drives
49 TM
VR_FAN and VR_HOT accordingly.Short TM pin to SGND if not used.
See “Thermal monitor” Section for details and typical connections.
All the internal references are referred to this pin. Connect to the PCB Signal
50 SGND
Ground.
Channel 4 LS Driver Supply.
It must be connected to others VCCDRx pins.
51 VCCDR4
LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap
vs. PGND4.
Channel 4 LS Driver Output. A small series resistor helps in reducing device-
52 LGATE4
dissipated power.
53 PGND4 Channel 4 LS Driver return path. Connect to Power ground Plane.
54 PGND2 Channel 2 LS Driver return path. Connect to Power ground Plane.
Channel 2 LS Driver Output. A small series resistor helps in reducing device-
55 LGATE2
dissipated power.
Channel 2 LS Driver Supply.
It must be connected to others VCCDRx pins.
56 VCCDR2
LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap
vs. PGND2.
Channel 3 LS Driver Supply.
It must be connected to others VCCDRx pins.
57 VCCDR3
LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap
vs. PGND3.
Channel 3 LS Driver Output.A small series resistor helps in reducing device-
58 LGATE3
dissipated power.
59 PGND3 Channel 3 LS Driver return path. Connect to Power ground Plane.

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Pin settings L6714

Table 1. Pin functions

N° Pin Function

60 PGND1 Channel 1 LS Driver return path. Connect to Power ground Plane.

Channel 1 LS Driver Output.A small series resistor helps in reducing device-
61 LGATE1
dissipated power.
Channel 1 LS Driver Supply.
It must be connected to others VCCDRx pins.
62 VCCDR1
LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap
vs. PGND1.
Channel 1 HS driver return path.
63 PHASE1 It must be connected to the HS1 mosfet source and provides return path for the
HS driver of channel 1.
64 N.C. Not internally connected.
Thermal pad connects the Silicon substrate and makes good thermal contact
THERMAL with the PCB to dissipate the power necessary to drive the external mosfets.
PAD
PAD
Connect to the PGND plane with several VIAs to improve thermal conductivity.

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L6714 Electrical data

3 Electrical data

3.1 Maximum rating

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VCC, VCCDRx to PGNDx 15 V

VBOOTx -
Boot voltage 15 V
VPHASEx
VUGATEx -
15 V
VPHASEx
VCC - VBOOTx 7.5 V
LGATEx, PHASEx, to PGNDx -0.3 to VCC + 0.3 V
VID0 to VID7, VID_SEL -0.3 to 5 V
All other Pins to PGNDx -0.3 to 7 V
Static condition
To PGNDx, VCC=14V, BOOTx=7V, -7.5 V
VPHASEx PHASEx=-7.5V
Positive peak voltage to PGNDx;
26 V
T < 20ns @ 600kHz

3.2 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

Thermal resistance junction to ambient

RthJA 40 °C/W
(Device soldered on 2s2p PC Board)
TMAX Maximum junction temperature 150 °C
TSTG Storage temperature range -40 to 150 °C
TJ Junction temperature range 0 to 125 °C
PTOT Maximum power dissipation at TA = 25°C 2.5 W

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Electrical characteristics L6714

4 Electrical characteristics

VCC = 12V ± 15%, TJ = 0°C to 70°C, unless otherwise specified

Table 4. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Supply Current

HGATEx and LGATEx = OPEN

ICC VCC supply current 17 mA
VCCDRx = BOOTx = 12V
LGATEx = OPEN;
ICCDRx VCCDRx supply current 1 mA
VCCDRx = 12V
HGATEx = OPEN; PHASEx to
IBOOTx BOOTx supply current 0.75 mA
PGNDx; VCC = BOOTx = 12V

Power-ON

VCC turn-ON VCC Rising; VCCDRx = 5V 8.9 9.3 V

UVLOVCC
VCC turn-OFF VCC Falling; VCCDRx = 5V 7.3 7.7 V
VCCDR turn-ON VCCDRx Rising; VCC = 12V 4.5 4.8 V
UVLOVCCDR
VCCDR turn-OFF VCCDRx Falling; VCC = 12V 3.9 4.3 V
Pre-OVP turn-ON VCC Rising; VCCDRx = 5V 3.6 3.85 V
UVLOOVP
Pre-OVP turn-OFF VCC Falling; VCCDRx = 5V 3.05 3.3 V

Oscillator and Inhibit

OSC = OPEN 135 150 165

FOSC Main Oscillator Accuracy kHz
OSC = OPEN; TJ = 0°C to 125°C 130 170
T1 SS Delay Time Intel mode 1 ms
T2 SS Time T2 Intel mode; RSSOSC = 25kΩ 500 µs
T3 SS Time T3 Intel mode 50 µs
Rising thresholds voltage 0.80 0.85 0.90 V
Output enable intel mode
Hysteresis 100 mV
OUTEN Input low 0.80 V
Output enable AMD mode
Input high 1.40 V
Pull-up current 12.5 µA
OSC = OPEN; IDROOP = 0µA 80 %
dMAX Maximum duty cycle
OSC = OPEN; IDROOP = 140µA 40 %
∆VOSC PWMx ramp amplitude 4 V
FAULT Voltage at Pin OSC OVP Active 5 V

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L6714 Electrical characteristics

Table 4. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Reference and DAC

Intel mode
VID = 1.000V to VID = 1.600V -0.5 - 0.5 %
FBR = VOUT; FBG = GNDOUT
kVID Output voltage accuracy
AMD mode
VID=1.000V to VID = 1.550V -0.6 - 0.6 %
FBR = VOUT; FBG = GNDOUT
REF Reference accuracy AMD mode; respect VID -10 - 10 mV
VBOOT Boot voltage Intel mode 1.081 V
VID Pull-up current Intel mode; VIDx to SGND 25 µA
IVID
VID Pull-down current AMD mode; VIDx to 5.4V 12.5 µA
Intel mode; Input Low 0.3
VIDIL V
AMD mode; Input Low 0.8
VID thresholds
Intel mode; Input High 0.8
VIDIH V
AMD mode; Input High 1.35
VID_SEL threshold Input low 0.3
VID_SEL V
(Intel mode) Input high 0.8

Error amplifier and remote buffer

A0 EA DC gain 80 dB
SR EA slew rate COMP = 10pF to SGND 20 V/µs
RB DC gain 1 V/V
Remote buffer common mode
CMRR 40 dB
rejection ratio

Differential current sensing and offset

LS sense 25
ICSx+ Bias current µA
Inductor sense 0
I
INFOx AVG-
–I Rg = 1kΩ; IINFOx = 25µA
-----------------------------------------
I AVG Current sense mismatch -3 - 3 %

IOCTH Over current threshold ICSx-(OCP) - ICSx-(0) 30 35 40 µA

Droop current deviation from OFFSET = SGND; Rg = 1kΩ

kIDROOP -2 - 2 µA
nominal value IDROOP = 0 to 80µA;
KIOFFSET Offset current accuracy IOFFSET = 50µA to 250µA -8 - 8 %
IOFFSET OFFSET current range 0 250 µA
VOFFSET OFFSET pin bias IOFFSET = 0 to 250µA 1.240 V

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Electrical characteristics L6714

Table 4. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Gate drivers

BOOTx - PHASEx = 10V;

tRISE_UGATEx HS rise time 15 30 ns
CUGATEx to PHASEx = 3.3nF
IUGATEx HS source current BOOTx - PHASEx = 10V 2 A
RUGATEx HS sink resistance BOOTx - PHASEx = 12V 1.5 2 2.5 Ω
VCCDRx = 10V;
tRISE_LGATEx LS rise time 30 55 ns
CLGATEx to PGNDx = 5.6nF
ILGATEx LS source current VCCDRx = 10V 1.8 A
RLGATEx LS sink resistance VCCDRx = 12V 0.7 1.1 1.5 Ω

Protections

Intel mode; before VBOOT 1.300 V

Over voltage protection
OVP Intel mode; above VID 100 150 200 mV
(VSEN Rising)
AMD mode 1.700 1.740 1.780 V

Program- IOVP current OVP = SGND 11.5 12.5 13.5 µA

mable OVP Comparator offset voltage OVP = 1.8V -50 0 50 mV
UVLOOVP < VCC < UVLOVCC
Preliminary over voltage VCC > UVLOVCC & 1.800 V
Pre-OVP OUTEN = SGND
protection
Hysteresis 350 mV
UVP Under voltage protection VSEN falling; below VID -750 mV
AMD mode; -300
PGOOD PGOOD threshold mV
VSEN falling; below VID

VSSEND/ SSEND / PGOOD

I = -4mA 0.4 V
PGOOD Voltage low

Thermal Monitor

TM Warning (VR_FAN) VTM rising 3.2 V

VTM TM Alarm (VR_HOT) VTM rising 3.6 V
TM Hysteresis 100 mV

VVR_HOT; VR_HOT voltage low; 0.4 V

I = -4mA
VVR_FAN VR_FAN voltage low 0.4 V

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L6714 VID Tables

5 VID Tables

5.1 Mapping for the Intel VR11 mode

Table 5. Voltage Identification (VID) Mapping for Intel VR11 Mode

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

800mV 400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV

5.2 Voltage Identification (VID) for Intel VR11 mode

Table 6. Voltage Identification (VID) for Intel VR11 mode (See Note).
Output Output Output Output
HEX Code voltage HEX Code voltage HEX Code voltage HEX Code voltage
(1) (1) (1) (1)

0 0 OFF 4 0 1.21250 8 0 0.81250 C 0 0.41250

0 1 OFF 4 1 1.20625 8 1 0.80625 C 1 0.40625
0 2 1.60000 4 2 1.20000 8 2 0.80000 C 2 0.40000
0 3 1.59375 4 3 1.19375 8 3 0.79375 C 3 0.39375
0 4 1.58750 4 4 1.18750 8 4 0.78750 C 4 0.38750
0 5 1.58125 4 5 1.18125 8 5 0.78125 C 5 0.38125
0 6 1.57500 4 6 1.17500 8 6 0.77500 C 6 0.37500
0 7 1.56875 4 7 1.16875 8 7 0.76875 C 7 0.36875
0 8 1.56250 4 8 1.16250 8 8 0.76250 C 8 0.36250
0 9 1.55625 4 9 1.15625 8 9 0.75625 C 9 0.35625
0 A 1.55000 4 A 1.15000 8 A 0.75000 C A 0.35000
0 B 1.54375 4 B 1.14375 8 B 0.74375 C B 0.34375
0 C 1.53750 4 C 1.13750 8 C 0.73750 C C 0.33750
0 D 1.53125 4 D 1.13125 8 D 0.73125 C D 0.33125
0 E 1.52500 4 E 1.12500 8 E 0.72500 C E 0.32500
0 F 1.51875 4 F 1.11875 8 F 0.71875 C F 0.31875
1 0 1.51250 5 0 1.11250 9 0 0.71250 D 0 0.31250
1 1 1.50625 5 1 1.10625 9 1 0.70625 D 1 0.30625
1 2 1.50000 5 2 1.10000 9 2 0.70000 D 2 0.30000
1 3 1.49375 5 3 1.09375 9 3 0.69375 D 3 0.29375
1 4 1.48750 5 4 1.08750 9 4 0.68750 D 4 0.28750
1 5 1.48125 5 5 1.08125 9 5 0.68125 D 5 0.28125
1 6 1.47500 5 6 1.07500 9 6 0.67500 D 6 0.27500

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VID Tables L6714

Table 6. Voltage Identification (VID) for Intel VR11 mode (See Note).
Output Output Output Output
HEX Code voltage HEX Code voltage HEX Code voltage HEX Code voltage
(1) (1) (1) (1)

1 7 1.46875 5 7 1.06875 9 7 0.66875 D 7 0.26875

1 8 1.46250 5 8 1.06250 9 8 0.66250 D 8 0.26250
1 9 1.45625 5 9 1.05625 9 9 0.65625 D 9 0.25625
1 A 1.45000 5 A 1.05000 9 A 0.65000 D A 0.25000
1 B 1.44375 5 B 1.04375 9 B 0.64375 D B 0.24375
1 C 1.43750 5 C 1.03750 9 C 0.63750 D C 0.23750
1 D 1.43125 5 D 1.03125 9 D 0.63125 D D 0.23125
1 E 1.42500 5 E 1.02500 9 E 0.62500 D E 0.22500
1 F 1.41875 5 F 1.01875 9 F 0.61875 D F 0.21875
2 0 1.41250 6 0 1.01250 A 0 0.61250 E 0 0.21250
2 1 1.40625 6 1 1.00625 A 1 0.60625 E 1 0.20625
2 2 1.40000 6 2 1.00000 A 2 0.60000 E 2 0.20000
2 3 1.39375 6 3 0.99375 A 3 0.59375 E 3 0.19375
2 4 1.38750 6 4 0.98750 A 4 0.58750 E 4 0.18750
2 5 1.38125 6 5 0.98125 A 5 0.58125 E 5 0.18125
2 6 1.37500 6 6 0.97500 A 6 0.57500 E 6 0.17500
2 7 1.36875 6 7 0.96875 A 7 0.56875 E 7 0.16875
2 8 1.36250 6 8 0.96250 A 8 0.56250 E 8 0.16250
2 9 1.35625 6 9 0.95625 A 9 0.55625 E 9 0.15625
2 A 1.35000 6 A 0.95000 A A 0.55000 E A 0.15000
2 B 1.34375 6 B 0.94375 A B 0.54375 E B 0.14375
2 C 1.33750 6 C 0.93750 A C 0.53750 E C 0.13750
2 D 1.33125 6 D 0.93125 A D 0.53125 E D 0.13125
2 E 1.32500 6 E 0.92500 A E 0.52500 E E 0.12500
2 F 1.31875 6 F 0.91875 A F 0.51875 E F 0.11875
3 0 1.31250 7 0 0.91250 B 0 0.51250 F 0 0.11250
3 1 1.30625 7 1 0.90625 B 1 0.50625 F 1 0.10625
3 2 1.30000 7 2 0.90000 B 2 0.50000 F 2 0.10000
3 3 1.29375 7 3 0.89375 B 3 0.49375 F 3 0.09375
3 4 1.28750 7 4 0.88750 B 4 0.48750 F 4 0.08750
3 5 1.28125 7 5 0.88125 B 5 0.48125 F 5 0.08125
3 6 1.27500 7 6 0.87500 B 6 0.47500 F 6 0.07500
3 7 1.26875 7 7 0.86875 B 7 0.46875 F 7 0.06875

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L6714 VID Tables

Table 6. Voltage Identification (VID) for Intel VR11 mode (See Note).
Output Output Output Output
HEX Code voltage HEX Code voltage HEX Code voltage HEX Code voltage
(1) (1) (1) (1)

3 8 1.26250 7 8 0.86250 B 8 0.46250 F 8 0.06250

3 9 1.25625 7 9 0.85625 B 9 0.45625 F 9 0.05625
3 A 1.25000 7 A 0.85000 B A 0.45000 F A 0.05000
3 B 1.24375 7 B 0.84375 B B 0.44375 F B 0.04375
3 C 1.23750 7 C 0.83750 B C 0.43750 F C 0.03750
3 D 1.23125 7 D 0.83125 B D 0.43125 F D 0.03125
3 E 1.22500 7 E 0.82500 B E 0.42500 F E OFF
3 F 1.21875 7 F 0.81875 B F 0.41875 F F OFF
1. According to VR11 specs, the device automatically regulates output voltage 19mV lower to avoid any
external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage
is than what extracted from the table lowered by 19mV built-in offset.

5.3 Voltage Identifications (VID) for Intel VR10 mode + 6.25mV

(VID7 does not care)

Table 7. Voltage identifications (VID) for Intel VR10 mode + 6.25mV (See Note).
Output Output
VID VID VID VID VID VID VID VID VID VID VID VID VID VID
voltage voltage
4 3 2 1 0 5 6 (1) 4 3 2 1 0 5 6 (1)

0 1 0 1 0 1 1 1.60000 1 1 0 1 0 1 1 1.20000
0 1 0 1 0 1 0 1.59375 1 1 0 1 0 1 0 1.19375
0 1 0 1 1 0 1 1.58750 1 1 0 1 1 0 1 1.18750
0 1 0 1 1 0 0 1.58125 1 1 0 1 1 0 0 1.18125
0 1 0 1 1 1 1 1.57500 1 1 0 1 1 1 1 1.17500
0 1 0 1 1 1 0 1.56875 1 1 0 1 1 1 0 1.16875
0 1 1 0 0 0 1 1.56250 1 1 1 0 0 0 1 1.16250
0 1 1 0 0 0 0 1.55625 1 1 1 0 0 0 0 1.15625
0 1 1 0 0 1 1 1.55000 1 1 1 0 0 1 1 1.15000
0 1 1 0 0 1 0 1.54375 1 1 1 0 0 1 0 1.14375
0 1 1 0 1 0 1 1.53750 1 1 1 0 1 0 1 1.13750
0 1 1 0 1 0 0 1.53125 1 1 1 0 1 0 0 1.13125
0 1 1 0 1 1 1 1.52500 1 1 1 0 1 1 1 1.12500
0 1 1 0 1 1 0 1.51875 1 1 1 0 1 1 0 1.11875
0 1 1 1 0 0 1 1.51250 1 1 1 1 0 0 1 1.11250
0 1 1 1 0 0 0 1.50625 1 1 1 1 0 0 0 1.10625

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VID Tables L6714

Table 7. Voltage identifications (VID) for Intel VR10 mode + 6.25mV (See Note).
Output Output
VID VID VID VID VID VID VID VID VID VID VID VID VID VID
voltage voltage
4 3 2 1 0 5 6 (1) 4 3 2 1 0 5 6 (1)

0 1 1 1 0 1 1 1.50000 1 1 1 1 0 1 1 1.10000
0 1 1 1 0 1 0 1.49375 1 1 1 1 0 1 0 1.09375
0 1 1 1 1 0 1 1.48750 1 1 1 1 1 0 1 OFF
0 1 1 1 1 0 0 1.48125 1 1 1 1 1 0 0 OFF
0 1 1 1 1 1 1 1.47500 1 1 1 1 1 1 1 OFF
0 1 1 1 1 1 0 1.46875 1 1 1 1 1 1 0 OFF
1 0 0 0 0 0 1 1.46250 0 0 0 0 0 0 1 1.08750
1 0 0 0 0 0 0 1.45625 0 0 0 0 0 0 0 1.08125
1 0 0 0 0 1 1 1.45000 0 0 0 0 0 1 1 1.07500
1 0 0 0 0 1 0 1.44375 0 0 0 0 0 1 0 1.06875
1 0 0 0 1 0 1 1.43750 0 0 0 0 1 0 1 1.06250
1 0 0 0 1 0 0 1.43125 0 0 0 0 1 0 0 1.05625
1 0 0 0 1 1 1 1.42500 0 0 0 0 1 1 1 1.05000
1 0 0 0 1 1 0 1.41875 0 0 0 0 1 1 0 1.04375
1 0 0 1 0 0 1 1.41250 0 0 0 1 0 0 1 1.03750
1 0 0 1 0 0 0 1.40625 0 0 0 1 0 0 0 1.03125
1 0 0 1 0 1 1 1.40000 0 0 0 1 0 1 1 1.02500
1 0 0 1 0 1 0 1.39375 0 0 0 1 0 1 0 1.01875
1 0 0 1 1 0 1 1.38750 0 0 0 1 1 0 1 1.01250
1 0 0 1 1 0 0 1.38125 0 0 0 1 1 0 0 1.00625
1 0 0 1 1 1 1 1.37500 0 0 0 1 1 1 1 1.00000
1 0 0 1 1 1 0 1.36875 0 0 0 1 1 1 0 0.99375
1 0 1 0 0 0 1 1.36250 0 0 1 0 0 0 1 0.98750
1 0 1 0 0 0 0 1.35625 0 0 1 0 0 0 0 0.98125
1 0 1 0 0 1 1 1.35000 0 0 1 0 0 1 1 0.97500
1 0 1 0 0 1 0 1.34375 0 0 1 0 0 1 0 0.96875
1 0 1 0 1 0 1 1.33750 0 0 1 0 1 0 1 0.96250
1 0 1 0 1 0 0 1.33125 0 0 1 0 1 0 0 0.95625
1 0 1 0 1 1 1 1.32500 0 0 1 0 1 1 1 0.95000
1 0 1 0 1 1 0 1.31875 0 0 1 0 1 1 0 0.94375
1 0 1 1 0 0 1 1.31250 0 0 1 1 0 0 1 0.93750
1 0 1 1 0 0 0 1.30625 0 0 1 1 0 0 0 0.93125
1 0 1 1 0 1 1 1.30000 0 0 1 1 0 1 1 0.92500

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L6714 VID Tables

Table 7. Voltage identifications (VID) for Intel VR10 mode + 6.25mV (See Note).
Output Output
VID VID VID VID VID VID VID VID VID VID VID VID VID VID
voltage voltage
4 3 2 1 0 5 6 (1) 4 3 2 1 0 5 6 (1)

1 0 1 1 0 1 0 1.29375 0 0 1 1 0 1 0 0.91875
1 0 1 1 1 0 1 1.28750 0 0 1 1 1 0 1 0.91250
1 0 1 1 1 0 0 1.28125 0 0 1 1 1 0 0 0.90625
1 0 1 1 1 1 1 1.27500 0 0 1 1 1 1 1 0.90000
1 0 1 1 1 1 0 1.26875 0 0 1 1 1 1 0 0.89375
1 1 0 0 0 0 1 1.26250 0 1 0 0 0 0 1 0.88750
1 1 0 0 0 0 0 1.25625 0 1 0 0 0 0 0 0.88125
1 1 0 0 0 1 1 1.25000 0 1 0 0 0 1 1 0.87500
1 1 0 0 0 1 0 1.24375 0 1 0 0 0 1 0 0.86875
1 1 0 0 1 0 1 1.23750 0 1 0 0 1 0 1 0.86250
1 1 0 0 1 0 0 1.23125 0 1 0 0 1 0 0 0.85625
1 1 0 0 1 1 1 1.22500 0 1 0 0 1 1 1 0.85000
1 1 0 0 1 1 0 1.21875 0 1 0 0 1 1 0 0.84375
1 1 0 1 0 0 1 1.21250 0 1 0 1 0 0 1 0.83750
1 1 0 1 0 0 0 1.20625 0 1 0 1 0 0 0 0.83125
1. According to VR10.x specs, the device automatically regulates output voltage 19mV lower to avoid any
external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage
is than what extracted from the table lowered by 19mVbuilt-in offset. VID7 doesn’t care.

5.4 Mapping for the AMD 6BIT mode

Table 8. Voltage identifications (VID) mapping for AMD 6BIT mode

VID4 VID3 VID2 VID1 VID0

400mV 200mV 100mV 50mV 25mV

5.5 Voltage identifications (VID) codes for AMD 6BIT mode

Table 9. Voltage identifications (VID) codes for AMD 6BIT mode (See Note).
Output Output
VID VID VID VID VID VID VID VID VID VID VID VID
Voltage Voltage
5 4 3 2 1 0 (1) 5 4 3 2 1 0 (1)

0 0 0 0 0 0 1.5500 1 0 0 0 0 0 0.7625
0 0 0 0 0 1 1.5250 1 0 0 0 0 1 0.7500
0 0 0 0 1 0 1.5000 1 0 0 0 1 0 0.7375
0 0 0 0 1 1 1.4750 1 0 0 0 1 1 0.7250

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VID Tables L6714

Table 9. Voltage identifications (VID) codes for AMD 6BIT mode (See Note).
Output Output
VID VID VID VID VID VID VID VID VID VID VID VID
Voltage Voltage
5 4 3 2 1 0 (1) 5 4 3 2 1 0 (1)

0 0 0 1 0 0 1.4500 1 0 0 1 0 0 0.7125
0 0 0 1 0 1 1.4250 1 0 0 1 0 1 0.7000
0 0 0 1 1 0 1.4000 1 0 0 1 1 0 0.6875
0 0 0 1 1 1 1.3750 1 0 0 1 1 1 0.6750
0 0 1 0 0 0 1.3500 1 0 1 0 0 0 0.6625
0 0 1 0 0 1 1.3250 1 0 1 0 0 1 0.6500
0 0 1 0 1 0 1.3000 1 0 1 0 1 0 0.6375
0 0 1 0 1 1 1.2750 1 0 1 0 1 1 0.6250
0 0 1 1 0 0 1.2500 1 0 1 1 0 0 0.6125
0 0 1 1 0 1 1.2250 1 0 1 1 0 1 0.6000
0 0 1 1 1 0 1.2000 1 0 1 1 1 0 0.5875
0 0 1 1 1 1 1.1750 1 0 1 1 1 1 0.5750
0 1 0 0 0 0 1.1500 1 1 0 0 0 0 0.5625
0 1 0 0 0 1 1.1250 1 1 0 0 0 1 0.5500
0 1 0 0 1 0 1.1000 1 1 0 0 1 0 0.5375
0 1 0 0 1 1 1.0750 1 1 0 0 1 1 0.5250
0 1 0 1 0 0 1.0500 1 1 0 1 0 0 0.5125
0 1 0 1 0 1 1.0250 1 1 0 1 0 1 0.5000
0 1 0 1 1 0 1.0000 1 1 0 1 1 0 0.4875
0 1 0 1 1 1 0.9750 1 1 0 1 1 1 0.4750
0 1 1 0 0 0 0.9500 1 1 1 0 0 0 0.4625
0 1 1 0 0 1 0.9250 1 1 1 0 0 1 0.4500
0 1 1 0 1 0 0.9000 1 1 1 0 1 0 0.4375
0 1 1 0 1 1 0.8750 1 1 1 0 1 1 0.4250
0 1 1 1 0 0 0.8500 1 1 1 1 0 0 0.4125
0 1 1 1 0 1 0.8250 1 1 1 1 0 1 0.4000
0 1 1 1 1 0 0.8000 1 1 1 1 1 0 0.3875
0 1 1 1 1 1 0.7750 1 1 1 1 1 1 0.3750
1. VID6 Not Applicable, need to be left unconnected.

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L6714 Reference schematic

6 Reference schematic

Figure 3. Reference schematic - Intel VR10.x, VR11 inductor sense

VIN LIN
to BOOT1
to BOOT2
GNDIN
62 2 CIN to BOOT3
VCCDR1 BOOT1 VIN
56 to BOOT4
VCCDR2
57 1
VCCDR3 UGATE1 HS1

63,64 L1
51 PHASE1
VCCDR4
61 R
15 LGATE1 LS1
VCC
60
PGND1 C
19,50
SGND 31 Rg
CS1-
33 30
OVP CS1+
10
16 BOOT2 VIN
DAC / CS_SEL
32
OFFSET 9
UGATE2 HS2
37
OSC/FAULT 7,8 L2
PHASE2
18
SSOSC / REF
55 R
LGATE2 LS2
38
VID7 / DVID
39 54
VID6 PGND2 C
40
VID bus from CPU

VID5 27 Rg
41 CS2-
VID4
L6714

42 26
VID3 CS2+
43
VID2 6 Vcc_core
44 BOOT3 VIN
VID1
45
VID0 5 COUT
UGATE3 HS3 LOAD
34
VID_SEL VID_SEL
17 3,4 L3
OUTEN OUTEN PHASE3

58 R
LGATE3 LS3
23
COMP
59
PGND3 C
CF
29 Rg
CS3-
RF
22 28
FB CS3+
21
DROOP 14
BOOT4 VIN

RFB 13
20 UGATE4 HS4
VSEN
11,12 L4
PHASE4
47
VR_HOT
48 52 R
VR_FAN LGATE4 LS4

+5V
NTC 53
49 PGND4 C
TM
25 Rg
CS4-
24
CS4+
46 SS_END
SS_END / PGOOD
FBR FBG
L6714 REF. SCH. (INDUCTOR - Intel Mode)
35 36

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Reference schematic L6714

Figure 4. Reference schematic - Intel VR10.x, VR11 LS MOSFET sense

VIN LIN
to BOOT1
to BOOT2
GNDIN
62 2 CIN to BOOT3
VCCDR1 BOOT1 VIN
56 to BOOT4
VCCDR2
57 1
VCCDR3 UGATE1 HS1

63,64 L1
51 PHASE1
VCCDR4
61
15 LGATE1 LS1
VCC
60
PGND1
19,50
SGND 31 Rg
CS1-
33 30 Rg
OVP CS1+
10
170k 15 BOOT2 VIN
DAC / CS_SEL
32
OFFSET 9
UGATE2 HS2
37
OSC/FAULT 7,8 L2
PHASE2
18
SSOSC / REF
55
LGATE2 LS2
38
VID7 / D-VID
39 54
VID6 PGND2
40
VID bus from CPU

VID5 27 Rg
41 CS2-
VID4
L6714

42 26 Rg
VID3 CS2+
43
VID2 6 Vcc_core
44 BOOT3 VIN
VID1
45
VID0 5 COUT
UGATE3 HS3 LOAD
34
VID_SEL VID_SEL
17 3,4 L3
OUTEN OUTEN PHASE3

58
LGATE3 LS3
23
COMP
59
PGND3
CF
29 Rg
CS3-
RF
22 28 Rg
FB CS3+
21
DROOP 14
BOOT4 VIN

RFB 13
20 UGATE4 HS4
VSEN
11,12 L4
PHASE4
47
VR_HOT
48 52
VR_FAN LGATE4 LS4

+5V
NTC 53
49 PGND4
TM
25 Rg
CS4-
24 Rg
CS4+
46 PGOOD
SSEND / PGOOD
FBR FBG
L6714 REF. SCH. (MOSFET - Intel Mode)
35 36

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L6714 Reference schematic

Figure 5. Reference schematic - AMD 6BIT inductor sense

VIN LIN
to BOOT1
to BOOT2
GNDIN
62 2 CIN to BOOT3
VCCDR1 BOOT1 VIN
56 to BOOT4
VCCDR2
57 1
VCCDR3 UGATE1 HS1

63,64 L1
51 PHASE1
VCCDR4
61 R
15 LGATE1 LS1
VCC
60
PGND1 C
19,50
SGND 31 Rg
CS1-
33 30
OVP CS1+
10
270k 16 BOOT2 VIN
DAC / CS_SEL
32
OFFSET 9
UGATE2 HS2
37
OSC/FAULT 7,8 L2
PHASE2
18
SSOSC / REF
55 R
LGATE2 LS2
38
VID7 / DVID
39 54
VID6 PGND2 C
40
VID5 27 Rg
41 CS2-
VID bus from CPU

VID4
42 26
L6714

VID3 CS2+
43
VID2 6 Vcc_core
44 BOOT3 VIN
VID1
45
VID0 5 COUT
UGATE3 HS3 LOAD
34
VID_SEL
17 3,4 L3
OUTEN OUTEN PHASE3

58 R
LGATE3 LS3
23
COMP
59
PGND3 C
CF
29 Rg
CS3-
RF
22 28
FB CS3+
21
DROOP 14
BOOT4 VIN

RFB 13
20 UGATE4 HS4
VSEN
11,12 L4
PHASE4
47
VR_HOT
48 52 R
VR_FAN LGATE4 LS4

+5V
NTC 53
49 PGND4 C
TM
25 Rg
CS4-
24
CS4+
46 SS_END
SS_END / PGOOD
FBR FBG
L6714 REF. SCH. (INDUCTOR - AMD 6BIT Mode)
35 36

25/70
Reference schematic L6714

Figure 6. Reference schematic - AMD 6BIT LS MOSFET sense

VIN LIN
to BOOT1
to BOOT2
GNDIN
62 2 CIN to BOOT3
VCCDR1 BOOT1 VIN
56 to BOOT4
VCCDR2
57 1
VCCDR3 UGATE1 HS1

63,64 L1
51 PHASE1
VCCDR4
61
15 LGATE1 LS1
VCC
60
PGND1
19,50
SGND 31 Rg
CS1-
33 30 Rg
OVP CS1+
10
15 BOOT2 VIN
DAC / CS_SEL
32
OFFSET 9
UGATE2 HS2
37
OSC/FAULT 7,8 L2
PHASE2
18
SSOSC / REF
55
LGATE2 LS2
38
VID7 / D-VID
39 54
VID6 PGND2
40
VID5 27 Rg
41 CS2-
VID bus from CPU

VID4
L6714

42 26 Rg
VID3 CS2+
43
VID2 6 Vcc_core
44 BOOT3 VIN
VID1
45
VID0 5 COUT
UGATE3 HS3 LOAD
34
VID_SEL
17 3,4 L3
OUTEN OUTEN PHASE3

58
LGATE3 LS3
23
COMP
59
PGND3
CF
29 Rg
CS3-
RF
22 28 Rg
FB CS3+
21
DROOP 14
BOOT4 VIN

RFB 13
20 UGATE4 HS4
VSEN
11,12 L4
PHASE4
47
VR_HOT
48 52
VR_FAN LGATE4 LS4

+5V
NTC 53
49 PGND4
TM
25 Rg
CS4-
24 Rg
CS4+
46 PGOOD
SSEND / PGOOD
FBR FBG
L6714 REF. SCH. (MOSFET - AMD 6BIT Mode)
35 36

26/70
L6714 Device description

7 Device description

L6714 is four-phase PWM controller with embedded high current drivers that provides
complete control logic and protections for a high performance step-down DC-DC voltage
regulator optimized for advanced microprocessor power supply. Multi phase buck is the
simplest and most cost-effective topology employable to satisfy the increasing current
demand of newer microprocessors and modern high current VRM modules. It allows
distributing equally load and power between the phases using smaller, cheaper and most
common external power MOSFET and inductors. Moreover, thanks to the equal phase shift
between each phase, the input and output capacitor count results in being reduced. Phase
interleaving causes in fact input RMS current and output ripple voltage reduction and show
an effective output switching frequency increase: the 150kHz free-running frequency per
phase, externally adjustable through a resistor, results multiplied on the output by the
number of phases.
L6714 permits easy and flexible system design by allowing current reading across either
inductor or low side MOSFET in fully differential mode simply selecting the desired way
through apposite pin. In both cases, also a sense resistor in series to the related element
can be considered to improve reading precision. The current information read corrects the
PWM output in order to equalize the average current carried by each phase limiting the error
at ±3% over static and dynamic conditions unless considering the sensing element spread.
The controller includes multiple DACs, selectable through an apposite pin, allowing
compatibility with both Intel VR10,VR11 and AMD 6BIT processors specifications, also
performing D-VID transitions accordingly.
Low-Side-Less start-up allows soft start over pre-biased output avoiding dangerous current
return through the main inductors as well as negative spike at the load side.
L6714 provides programmable Over-Voltage protection to protect the load from dangerous
over stress. It can be externally set to a fixed voltage through an apposite resistor, or it can
be set internally, latching immediately by turning ON the lower driver and driving high the
FAULT pin. Furthermore, preliminary OVP protection also allows the device to protect load
from dangerous OVP when VCC is not above the UVLO threshold.
The Over-Current protection provided, with an OC threshold for each phase, causes the
device to enter in constant current mode until the latched UVP.
L6714 provides system Thermal Monitoring: through an apposite pin the device senses the
temperature of the hottest component in the application driving the Warning and the Alarm
signal as a consequence.
A compact 10x10mm body TQFP64 package with exposed thermal pad allows dissipating
the power to drive the external MOSFET through the system board.

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Configuring the device L6714

8 Configuring the device

Multiple DACs and different current reading methodologies need to be configured before the
system starts-up by programming the apposite pin DAC/CS_SEL.
The configuration of this pin identifies two main working areas (See Table 10) distinguishing
between compliancy with Intel VR10,VR11 or AMD 6BIT specifications. According to the
main specification considered, further customs can be done: main differences are regarding
the DAC table, soft-start implementation, protection management and Dynamic VID
Transitions. Of course, the Current Reading method can be still selected through DAC /
CS_SEL pin.
See Table 11 and See Table 12 for further details about the device configuration.

8.1 DAC selection

L6714 embeds a selectable DAC (through DAC/CS_SEL, See Table 10) that allows to
regulate the output voltage with a tolerance of ±0.5% (±0.6% for AMD DAC) recovering from
offsets and manufacturing variations. In case of selecting Intel Mode, the device
automatically introduces a -19mV (both VRD10.x and VR11) offset to the regulated voltage
in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a
consequence, the calculated system TOB.

Table 10. DAC / CS_SEL settings (See Note).

DAC / CS_SEL Current sense
DAC OVP UVP
Resistance vs. SGND method

0 (Short) Inductor DCR VID + 150mV

Intel (typ) or -750mV (typ)
170kΩ MOSFET RdsON Programmable
270kΩ Inductor DCR 1.800V (typ) or
AMD -750mV (typ)
OPEN MOSFET RdsON Programmable

Note: Filter DAC/CS_SEL pin with 100pF(max) vs. SGND.

Output voltage is programmed through the VID pins: they are inputs of an internal DAC that
is realized by means of a series of resistors providing a partition of the internal voltage
reference. The VID code drives a multiplexer that selects a voltage on a precise point of the
divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the
set-point of the error amplifier, VREF).

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L6714 Configuring the device

Table 11. Intel mode configuration (See Note).

Pin Function Typical connection

It allows selecting the Intel Mode and, SGND: Inductor Sense;

furthermore, between Inductor or LS MOSFET 170kΩ to SGND: LS MOSFET
DAC / CS_SEL current reading. Sense.
Static info, no dynamic changes allowed. Filter with 100pF(max).
It allows programming the soft-start time TSS.
SSOSC / REF Resistor RSSOSC vs. SGND.
See “Soft start” Section for details.
It allows selecting between VR11 DAC or Open: VR11 (Table 6).
VID_SEL VR10.x + 6.25mV extended DAC. Short to SGND: VR10.x
Static info, no dynamic changes allowed. (Table 7).
They allow programming the Output Voltage
according to Table 6 and Table 7. Open: Logic “1” (25µA pull-up)
VID7 to VID0
Dynamic transitions managed, See “Dynamic Short to SGND: “0”
VID transitions” Section for details.
SSEND / Soft Start end signal set free after soft-start has Pull-up to anything lower than
PGOOD finished. It only indicates soft-start has finished. 5V.

Note: VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes
according to the selected DAC: See Table 4 for details.

Table 12. AMD mode configuration (See Note).

Pin Function Typical connection

It allows selecting the AMD mode and, 270kΩ to SGND: Inductor

furthermore, between Inductor or LS MOSFET Sense;
DAC / CS_SEL current reading. OPEN: LS MOSFET Sense;
Static info, no dynamic changes allowed. Filter with 100pF(max).
The reference used for the regulation is Filter with 47Ω - 4.7nF vs.
SSOSC / REF
available on this pin. SGND.
VID_SEL Not Applicable Need to be shorted to SGND.
Pulled high when performing a D-VID transition.
VID7 / DVID Not Applicable
The pin is kept high with a 32 clock cycles delay.
VID6 Not Applicable Needs to be shorted to SGND
They allow programming the Output Voltage
according to Table 9. Open: “0” (12.5µA pull-down)
VID5 to VID0
Dynamic transitions managed, See “Dynamic Pull-up to V > 1.4V: “1”
VID transitions” Section for details.
Power Good signal set free after soft-start has
SSEND / Pull-up to anything lower than
finished whenever the output voltage is within
PGOOD 5V.
limits.

Note: VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes
according to the selected DAC: See Table 4 for details.

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Power dissipation L6714

9 Power dissipation

L6714 embeds high current MOSFET drivers for both high side and low side MOSFET: it is
then important to consider the power the device is going to dissipate in driving them in order
to avoid overcoming the maximum junction operative temperature. In addition, since the
device has an exposed pad to better dissipate the power, the thermal resistance between
junction and ambient consequent to the layout is also important: thermal pad need to be
soldered to the PCB ground plane through several VIAs in order to facilitate the heat
dissipation.
Two main terms contribute to the device power dissipation: bias power and drivers' power.
The first one (PDC) depends on the static consumption of the device through the supply pins
and is simply quantifiable as follows (assuming to supply HS and LS drivers with the same
VCC of the device):
P DC = V CC ⋅ ( I CC + N ⋅ I CCDRx + N ⋅ I BOOTx )

where N is the number of phases.

Drivers' power is the power needed by the driver to continuously switch on and off the
external MOSFET; it is a function of the switching frequency and total gate charge of the
selected MOSFET. It can be quantified considering that the total power PSW dissipated to
switch the MOSFET (easy calculable) is dissipated by three main factors: external gate
resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This
last term is the important one to be determined to calculate the device power dissipation.
The total power dissipated to switch the MOSFET results:
P SW = N ⋅ F SW ⋅ ( Q GHS ⋅ V BOOT + Q GLS ⋅ V CCDRx )

External gate resistors help the device to dissipate the switching power since the same
power PSW will be shared between the internal driver impedance and the external resistor
resulting in a general cooling of the device. When driving multiple MOSFET in parallel, it is
suggested to use one gate resistor for each MOSFET.

30/70
L6714 Power dissipation

Figure 7. L6714 dissipated power (Quiescent + switching).

L6714; Rgate=0; Rmosfet=0

5000
HS=1xSTD38NH02L; LS=1xSTD90NH02L

Controller Dissipated Power [mW]

4500 HS=2xSTD38NH02L; LS=2xSTD90NH02L
4000 HS=1xSTD55NH22L; LS=1xSTD95NH02L
HS=2xSTD55NH22L; LS=2xSTD95NH02L
3500 HS=3xSTD55NH22L; LS=3xSTD95NH02L
3000

2500

2000

1500

1000

500

0
50 100 150 200 250 300 350 400 450 500 550
Switching frequency [kHz] per phase

L6714; Rhs=2.2; Rls=3.3; Rmosfet=1

7000
HS=1xSTD38NH02L; LS=1xSTD90NH02L
Controller Dissipated Power [mW]

6000 HS=2xSTD38NH02L; LS=2xSTD90NH02L

HS=1xSTD55NH2LL; LS=1xSTD95NH02L
HS=2xSTD55NH2LL; LS=2xSTD95NH02L
5000
HS=3xSTD55NH2LL; LS=3xSTD95NH02L

4000

3000

2000

1000

0
50 100 150 200 250 300 350 400 450 500 550
Switching Frequency per phase [kHz]

31/70
Current reading and current sharing loop L6714

10 Current reading and current sharing loop

L6714 embeds a flexible, fully-differential current sense circuitry that is able to read across
both low side or inductor parasitic resistance or across a sense resistor placed in series to
that element. The fully-differential current reading rejects noise and allows placing sensing
element in different locations without affecting the measurement's accuracy. The kind of
sense element can be simply chosen through the DAC/CS_SEL pin according to See
Table 10.
Current sharing control loop reported in Figure 8: it considers a current IINFOx proportional to
the current delivered by each phase and the average current I AVG = ΣI INFOx ⁄ ( N ). The error
between the read current IINFOx and the reference IAVG is then converted into a voltage that
with a proper gain is used to adjust the duty cycle whose dominant value is set by the
voltage error amplifier in order to equalize the current carried by each phase. Details about
connections are shown in Figure 9.

Figure 8. Current sharing loop.

IINFO1
PWM1 Out

AVG IAVG
IINFO2
PWM2 Out
From EA

IINFO3
PWM3 Out

IINFO4
PWM4 Out

32/70
L6714 Current reading and current sharing loop

10.1 Low side current reading

When reading current across LS, the current flowing trough each phase is read using the
voltage drop across the low side MOSFET RdsON or across a sense resistor in its series and
it is internally converted into a current. The trans-conductance ratio is issued by the external
resistor Rg placed outside the chip between CSx- and CSx+ pins toward the reading points.
The current sense circuit tracks the current information for a time TTRACK centered in the
middle of the LS conduction time and holds the tracked information during the rest of the
period.
L6714 sources a constant 25µA bias current from the CSx+ pin: the current reading circuitry
uses this pin as a reference and the reaction keeps the CSx- pin to this voltage during the
reading time (an internal clamp keeps CSx+ and CSx- at the same voltage sinking from the
CSx- pin the necessary current during the hold time; this is needed to avoid absolute
maximum rating overcome on CSx- pin). The current that flows from the CSx- pin is then
given by (See Figure 9):
R dsON
I CSx- = 25µA + ----------------- ⋅ I PHASEx = 25µA + I INFOx
Rg

where RdsON is the ON resistance of the low side MOSFET and Rg is the trans-conductance
resistor used between CSx- and CSx+ pins toward the reading points; IPHASEx is the current
carried by the relative phase and IINFOx is the current information signal reproduced
internally.
25µA offset allows negative current reading, enabling the device to check for dangerous
returning current between the phases assuring the complete current equalization.

10.2 Inductor current reading

When reading current across the inductor DCR, the current flowing trough each phase is
read using the voltage drop across the output inductor or across a sense resistor in its
series and internally converted into a current. The trans-conductance ratio is issued by the
external resistor Rg placed outside the chip between CSx- pin toward the reading points.
The current sense circuit always tracks the current information, no bias current is sourced
from the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this voltage. To
correctly reproduce the inductor current an R-C filtering network must be introduced in
parallel to the sensing element.
The current that flows from the CSx- pin is then given by the following equation (See
Figure 9):
RL 1 + s ⋅ L ⁄ RL
I CSx- = -------- ⋅ ------------------------------------- ⋅ I
Rg 1 + s ⋅ R ⋅ C PHASEx

Where IPHASEx is the current carried by the relative phase.

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Current reading and current sharing loop L6714

Figure 9. Current reading connections.

IPHASEx
IPHASEx
Lx RLx
PHASEx
LGATEx
R
CSx- Rg CSx+ C
ICSx- NO Bias
25µA ICSx-=IINFOx
CSx+ Rg CSx- Rg

LS Mosfet RdsON Current Sense Inductor DCR Current Sense

Considering now to match the time constant between the inductor and the R-C filter applied
(Time constant mismatches cause the introduction of poles into the current reading network
causing instability. In addition, it is also important for the load transient response and to let
the system show resistive equivalent output impedance), it results:
L- = R ⋅ C RL RL
------ ⇒ I CSx- = -------- ⋅ I PHASEx = I INFOx ⇒ I INFOX = -------- ⋅ I PHASEx
RL Rg Rg

Where IINFOx is the current information reproduced internally.

34/70
L6714 Remote voltage sense

11 Remote voltage sense

The device embeds a Remote Sense Buffer to sense remotely the regulated voltage without
any additional external components. In this way, the output voltage programmed is regulated
between the remote buffer inputs compensating motherboard or connector losses. It senses
the output voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage
sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin
with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded
by a power plane results in common mode coupling for any picked-up noise.
If remote sense is not required, it is enough connecting the resistor RFB directly to the
regulated voltage: VSEN becomes not connected and still senses the output voltage
through the remote buffer. In this case the FBG and FBR pins must be connected anyway to
the regulated voltage (See Figure 10).

Warning: The remote buffer is included in the trimming chain in order

to achieve ±0.5% accuracy (0.6% for the AMD DAC) on the
output voltage when the RB is used: eliminating it from the
control loop causes the regulation error to be increased by
the RB offset worsening the device performances.

Figure 10. Remote buffer connections

64k 64k

VREF VREF
64k

64k

64k

64k
64k 64k

FB COMP VSEN FBR FBG FB COMP VSEN FBR FBG

RF CF RF CF
To Vcore
(Remote Sense)
RFB RFB
To Vcore
Remote Buffer Used (Up to 0.5% Accuracy) Remote Buffer NOT Used (Precision Worsened)

35/70
Voltage positioning L6714

12 Voltage positioning

Output voltage positioning is performed by selecting the reference DAC and by

programming the Droop Function and Offset to the reference (See Figure 11). The currents
sourced from DROOP and FB pins cause the output voltage to vary according to the
external RFB resistor.
In addition, the embedded Remote Buffer allows to precisely programming the output
voltage offsets and variations by recovering the voltage drops across distribution lines.
The output voltage is then driven by the following relationship:
V OUT = V REF – R FB ⋅ ( I DROOP – I OFFSET )

where
⎧
V REF = ⎨ VID – 19mV VR10 - VR11
⎩ VID AMD 6BIT

DROOP function can be disabled as well as the OFFSET: connecting DROOP pin and FB
pin together implements the load regulation dependence while, if this effect is not desired,
by shorting DROOP pin to SGND it is possible for the device to operate as a classic Voltage
Mode Buck converter. The DROOP pin can also be connected to SGND through a resistor
obtaining a voltage proportional to the delivered current usable for monitoring purposes.
OFFSET can be disabled by shorting the relative pin to SGND.

36/70
L6714 Voltage positioning

12.1 Droop function (Optional)

This method "recovers" part of the drop due to the output capacitor ESR in the load
transient, introducing a dependence of the output voltage on the load current: a static error
proportional to the output current causes the output voltage to vary according to the sensed
current.
As shown in Figure 11, the ESR drop is present in any case, but using the droop function
the total deviation of the output voltage is minimized. Moreover, more and more high-
performance CPUs require precise load-line regulation to perform in the proper way.
DROOP function is not then required only to optimize the output filter, but also beacomes a
requirement of the load.
Connecting DROOP pin and FB pin together, the device forces a current IDROOP,
proportional to the read current, into the feedback resistor RFB implementing the load
regulation dependence. Since IDROOP depends on the current information about the three
phases, the output characteristic vs. load current is then given by:
R SENSE
V OUT = V REF – R FB ⋅ I DROOP = V REF – R FB ⋅ --------------------- ⋅ I OUT = V REF – R DROOP ⋅ I OUT
Rg

Where RSENSE is the chosen sensing element resistance (Inductor DCR or LS RdsON) and
IOUT is the output current of the system.
The whole power supply can be then represented by a "real" voltage generator with an
equivalent output resistance RDROOP and a voltage value of VREF. RFB resistor can be also
designed according to the RDROOP specifications as follow:
Rg
R FB = R DROOP ⋅ ---------------------
R SENSE

Droop function is optional, in case it is not desired, the DROOP pin can be disconnected
from the FB and an information about the total delivered current becomes available for
debugging, and/or current monitoring. When not used, the pin can be shorted to SGND.

Figure 11. Voltage positioning (left) and droop function (right)

64k
ESR Drop
IOFFSET
IDROOP

VREF
VMAX
64k

64k

64k
VNOM

DROOP FB COMP VSEN FBR FBG

VMIN

RF CF RESPONSE WITHOUT DROOP

To Vcore RESPONSE WITH DROOP
(Remote Sense)
RFB

37/70
Voltage positioning L6714

12.2 Offset (Optional)

The OFFSET pin allows programming a positive offset (VOS) for the output voltage by
connecting a resistor ROFFSET vs. SGND; this offset has to be considered in addition to the
one already introduced during the production stage for the Intel VR10,VR11 Mode.
The OFFSET pin is internally fixed at 1.240V (See Table 4) a current is programmed by
connecting the resistor ROFFSET between the pin and SGND: this current is mirrored and
then properly sunk from the FB pin as shown in Figure 12. Output voltage is then
programmed as follow:

V OUT = V REF – R FB ⋅ ( I DROOP – I OFFSET )

Offset resistor can be designed by considering the following relationship (RFB is fixed by the
Droop effect):
1.240V
R OFFSET = ------------------- ⋅ R FB
V OS

Offset automatically given by the DAC selection differs from the offset implemented through
the OFFSET pin: the built-in feature is trimmed in production and assures ±0.5% error
(±0.6% for the AMD DAC) over load and line variations.

Figure 12. Voltage positioning with offset

64k
IOFFSET
IDROOP

VREF
1.240V
IOFFSET

64k

64k
64k

OFFSET DROOP FB COMP VSEN FBR FBG

ROFFSET
RF CF
To Vcore
(Remote Sense)
RFB

38/70
L6714 Dynamic VID transitions

13 Dynamic VID transitions

The device is able to manage Dynamic VID Code changes that allow Output Voltage
modification during normal device operation. OVP and UVP signals (and PGOOD in case of
AMD Mode) are masked during every VID transition and they are re-activated after the
transition finishes with a 32 clock cycles delay to prevent from false triggering due to the
transition.
When changing dynamically the regulated voltage (D-VID), the system needs to charge or
discharge the output capacitor accordingly. This means that an extra-current ID-VID needs to
be delivered, especially when increasing the output regulated voltage and it must be
considered when setting the over current threshold. This current can be estimated using the
following relationships:
dV OUT
I D – VID = C OUT ⋅ ------------------
dT VID

where dVOUT is the selected DAC LSB (6.25mV for VR11 and VR10 Extended DAC or 25mV
for AMD DAC) and TVID is the time interval between each LSB transition (externally driven).
Overcoming the OC threshold during the dynamic VID causes the device to enter the
constant current limitation slowing down the output voltage dV/dt also causing the failure in
the D-VID test.
L6714 checks for VID code modifications (See Figure 13) on the rising edge of an internal
additional DVID-clock and waits for a confirmation on the following falling edge. Once the
new code is stable, on the next rising edge, the reference starts stepping up or down in LSB
increments every VID-clock cycle until the new VID code is reached. During the transition,
VID code changes are ignored; the device re-starts monitoring VID after the transition has
finished on the next rising edge available. VID-clock frequency (FDVID) depends on the
operative mode selected: for Intel Mode it is in the range of 1MHz to assure compatibility
with the specifications while, for AMD Mode, this frequency is lowered to about 250kHz.
When L6714 performs a D-VID transition in AMD Mode, DVID pin is pulled high as long as
the device is performing the transition (also including the additional 32clocks delay)

Warning: If the new VID code is more than 1 LSB different from the
previous, the device will execute the transition stepping the
reference with the DVID-clock frequency FDVID until the new
code has reached: for this reason it is recommended to
carefully control the VID change rate in order to carefully
control the slope of the output voltage variation especially in
Intel Mode.

39/70
40/70
Vout
Int. Reference
VID [0,7]
VID Clock
VID Sampled
VID Sampled

TDVID

Tsw
VID Sampled
Dynamic VID transitions

VID Stable
Ref Moved (1)
Ref Moved (2)
Ref Moved (3)
Ref Moved (4)
Figure 13. Dynamic VID transitions

VID Sampled

DVID-Clock Oscillator
x 4 Step VID Transition
VID Sampled

Vout Slope Controlled by internal

VID Sampled
VID Sampled
VID Sampled
VID Stable

TVID
Ref Moved (1)
VID Sampled
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
driving circuit (TVID)
4 x 1 Step VID Transition

VID Sampled
VID Stable
Vout Slope Controlled by external

Ref Moved (1)

VID Sampled
VID Sampled
VID Sampled
t
t
t
t
L6714
L6714 Enable and disable

14 Enable and disable

L6714 has three different supplies: VCC pin to supply the internal control logic, VCCDRx to
supply the low side drivers and BOOTx to supply the high side drivers.
If the voltage at pins VCC and VCCDRx are not above the turn on thresholds specified in the
Electrical characteristics, the device is shut down: all drivers keep the MOSFET off to show
high impedance to the load.
Once the device is correctly supplied, proper operation is assured and the device can be
driven by the OUTEN pin to control the power sequencing.
Setting the pin free, the device implements a soft start up to the programmed voltage.
Shorting the pin to SGND, it resets the device (SS_END/PGOOD is shorted to SGND in this
condition) from any latched condition and also disables the device keeping all the MOSFET
turned off to show high impedance to the load.

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Soft start L6714

15 Soft start

L6714 implements a soft-start to smoothly charge the output filter avoiding high in-rush
currents to be required to the input power supply. The device increases the reference from
zero up to the programmed value in different ways according to the selected Operative
Mode and the output voltage increases accordingly with closed loop regulation.
The device implements Soft-Start only when all the power supplies are above their own turn-
on thresholds and the OUTEN pin is set free.
At the end of the digital Soft-Start, SS_END/PGOOD signal is set free. Protections are
active during this phase; Under Voltage is enabled when the reference voltage reaches 0.6V
while Over Voltage is always enabled with a threshold dependent on the selected Operative
Mode or with the fixed threshold programmed by ROVP (See “Over voltage and
programmable OVP” Section).

Figure 14. Soft start

Intel Mode AMD 6BIT Mode

OUTEN OUTEN

VOUT OVP t VOUT t

SS_END t PGOOD t

T1 T2 T3 T4 t t
TSS

TSS

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L6714 Soft start

15.1 Intel mode

Once L6714 receives all the correct supplies and enables, and Intel Mode has been
selected, it initiates the Soft-Start phase with a T1 = 1ms(min) delay. After that, the reference
ramps up to VBOOT = 1.081V (1.100V - 19mV) in T2 according to the SSOSC settings and
waits for T3 = 75µsec(typ) during which the device reads the VID lines. Output voltage will
then ramps up to the programmed value in T4 with the same slope as before (See
Figure 14).
SSOSC defines the frequency of an internal additional Soft-Start-oscillator used to step the
reference from zero up to the programmed value; this oscillator is independent from the
main oscillator whose frequency is programmed through the OSC pin. SSOSC sets then the
Output Voltage dV/dt during Soft-Start according to the resistor RSSOSC connected vs.
SGND. In particular, it allows to precisely programming the start-up time up to VBOOT (T2)
since it is a fixed voltage independent by the programmed VID. Total Soft-Start time
dependence on the programmed VID results (See Figure 15):
–2
R SSOSC [ kΩ] = T 2 [ µs ] ⋅ 4.9783 ⋅ 10

⎧ R SSOSC [ kΩ]
⎪ - ⋅ V SS
------------------------------------ if ( V SS > V BOOT )
⎪ 5.3816 ⋅ 10
–2
T SS [ µs ] = 1075 [ µs ] + ⎨
⎪ R SSOSC [ kΩ]
⎪ - ⋅ [ V BOOT + ( V BOOT – V SS ) ]
------------------------------------ if ( V SS < V BOOT )
–2
⎩ 5.3816 ⋅ 10

where TSS is the time spent to reach the programmed voltage VSS and RSSOSC the resistor
connected between SSOSC and SGND in kΩ.
Protections are active during Soft-Start, UVP is enabled after the reference reaches 0.6V
while OVP is always active with a fixed 1.24V threshold before VBOOT and with the threshold
coming from the VID (or the programmed VOVP) after VBOOT (See red-dashed line in
Figure 14).
Note: If during T3 the programmed VID selects an output voltage lower than VBOOT, the output
voltage will ramp to the programmed voltage starting from VBOOT.

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Soft start L6714

Figure 15. Soft-start time for Intel mode.

8

7
Time to Vboot

Soft Start Time Tss [ms]

6 Time to 1.6000V

0
1 10 100 1000
Rssosc [kOhms] vs. SGND

15.2 AMD mode

Once L6714 receives all the correct supplies and enables, and AMD Mode has been
selected, it initiates the Soft-Start by stepping the reference from zero up to the programmed
VID code (See Figure 14); the clock now used to step the reference is the same as the main
oscillator programmed by the OSC pin, SSOSC pin is not applicable in this case. The Soft-
Start time results then (See Figure 16):
dV OUT V SS
- = 3.125 ⋅ F SW [ kkHz ] ⇒ TSS = -------------------------------------------------
----------------- -
dT 3.125 ⋅ F SW [ kHz ]

where TSS is the time spent to reach VSS and FSW is the main switching frequency
programmed by OSC pin. Protections are active during Soft-Start, UVP is enabled after the
reference reaches 0.6V while OVP is always active with the fixed 1.800V threshold (or the
programmed VOVP).

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L6714 Soft start

Figure 16. Soft-start time for AMD mode

4 550

3.5 500

SoftStart Time Tss [msec]

Switching Freqency [kHz]

3 450

2.5 400

2 350

1.5 Time to 1.6000V 300

Time to 1.1000V
1 250
Switching Frequency per phase
0.5 200

0 150
0 200 400 600 800 1000
Rosc [kOhms] to SGND

4 550

3.5 500
SoftStart Time Tss [msec]

Switching Freqency [kHz]

3 450

2.5 400

2 350

1.5 Time to 1.6000V 300

Time to 1.1000V
1 250
Switching Frequency per phase
0.5 200

0 150
0 200 400 600 800 1000
Rosc [kOhms] to SGND

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Soft start L6714

15.3 Low-Side-Less startup

In order to avoid any kind of negative undershoot on the load side during start-up, L6714
performs a special sequence in enabling LS driver to switch: during the soft-start phase, the
LS driver results disabled (LS=OFF) until the HS starts to switch. This avoid the dangerous
negative spike on the output voltage that can happen if starting over a pre-biased output
(See Figure 17).
This particular feature of the device masks the LS turn-on only from the control loop point of
view: protections are still allowed to turn-ON the LS MOSFET in case of over voltage if
needed.

Figure 17. Low-Side-Less start-up comparison

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L6714 Output voltage monitor and protections

16 Output voltage monitor and protections

L6714 monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP
and PGOOD (when applicable) conditions. The device shows different thresholds when
programming different operation mode (Intel or AMD, See Table 10) but the behavior in
response to a protection event is still the same as described below.
Protections are active also during soft-start (See “Soft start” Section) while are masked
during D-VID transitions with an additional 32 clock cycle delay after the transition has
finished to avoid false triggering.

16.1 Under voltage

If the output voltage monitored by VSEN drops more than -750mV below the programmed
reference for more than one clock period, L6714 turns off all MOSFET and latches the
condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the
selected operative mode.

16.2 Preliminary over voltage

To provide a protection while VCC is below the UVLOVCC threshold is fundamental to avoid
damage to the CPU in case of failed HS MOSFET. In fact, since the device is supplied from
the 12V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLOVCC). In
order to give full protection to the load, a preliminary-OVP protection is provided while VCC
is within UVLOVCC and UVLOOVP.
This protection turns-on the low side MOSFET as long as the FBR pin voltage is greater
than 1.800V with a 350mV hysteresis. When set, the protection drives the LS MOSFET with
a gate-to-source voltage depending on the voltage applied to VCCDRx and independently
by the turn-ON threshold across these pins (UVLOVCCDR). This protection depends also on
the OUTEN pin status as detailed in Figure 18.
A simple way to provide protection to the output in all conditions when the device is OFF
(then avoiding the unprotected red region in Figure 18-Left) consists in supplying the
controller through the 5VSB bus as shown in Figure 18-Right: 5VSB is always present before
+12V and, in case of HS short, the LS MOSFET is driven with 5V assuring a reliable
protection of the load. Preliminary OVP is always active before UVLOVCC for both Intel and
AMD Modes.

Figure 18. Output voltage protections and typical principle connections

+5V
SB

(OUTEN = 0) (OUTEN = 1)
Vcc
Preliminary OVP Programmable OVP +12V VCC
FBR Monitored VSEN Monitored
UVLOVCC

Preliminary OVP Enabled VCCDR1

FBR Monitored
UVLOOVP VCCDR2

No Protection
VCCDR3
Provided

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Output voltage monitor and protections L6714

16.3 Over voltage and programmable OVP

Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), L6714
provides an Over Voltage Protection: when the voltage sensed by VSEN overcomes the
OVP threshold, the controller permanently switches on all the low-side MOSFET and
switches off all the high-side MOSFET in order to protect the load. The OSC/ FAULT pin is
driven high (5V) and power supply or OUTEN pin cycling is required to restart
operations.The OVP Threshold varies according to the operative mode selected (See
Table 10).
The OVP threshold can be also programmed through the OVP pin: leaving the pin floating, it
is internally pulled-up and the OVP threshold is set according to Table 10. Connecting the
OVP pin to SGND through a resistor ROVP, the OVP threshold becomes the voltage present
at the pin. Since the OVP pin sources a constant IOVP = 12.5µA current(See Table 10), the
programmed voltage becomes:
OVP TH
OVP TH = R OVP ⋅ 12.5µA ⇒ R OVP = -------------------
-
12.5µA

Filter OVP pin with 100pF(max) vs. SGND.

16.4 PGOOD (Only for AMD mode)

It is an open-drain signal set free after the soft-start sequence has finished. It is pulled low
when the output voltage drops below -300mV of the programmed voltage.

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L6714 Maximum Duty-cycle limitation

17 Maximum Duty-cycle limitation

The device limits the maximum duty cycle and this value is not fixed but it depends on the
delivered current given by the following relationship:
R SENSE
D ( max ) = 0.80 – ( I DROOP × 2.857k ) = 0.80 – ⎛ --------------------- × I × 2.857k⎞
⎝ Rg OUT
⎠

From the previous relationships the maximum duty cycle results:

⎧ 80% I DROOP = 0µA

D ( max ) = ⎨
⎩ 40% I DROOP = 140µA

If the desired output characteristic crosses the limited-DMAX maximum output voltage, the
output resulting voltage will start to drop after the cross-point. In this case the output voltage
starts to decrease following the resulting characteristic (dotted in Figure 19) until UVP is
detected or anyway until IDROOP=140µA.

Figure 19. Maximum Duty-Cycle (left) and limited DMAX output voltage (right)

Maximum Duty Cycle Limited DMAX Output Voltage

DMAX VOUT

80 % 0.80 VIN

40 % 0.40 VIN
Limted-DMAX Output Char.
Desired output Char.
Resulting Output Char.
UVP Threshold

IDROOP IOUT
IDROOP = 140µA IOCP = N x IOCPx
(IOCP = N x IOCPx ) (IDROOP = 140µA)

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Over current protection L6714

18 Over current protection

Depending on the current reading method selected, the device limits the peak or the bottom
of the inductor current entering in constant current until setting UVP as below explained.
The Over Current threshold has to be programmed, by designing the Rg resistors, to a safe
value, in order to be sure that the device doesn't enter OCP during normal operation of the
device. This value must take into consideration also the extra current needed during the
Dynamic VID Transition ID-VID and, since the device reads across MOSFET RdsON or
inductor DCR, the process spread and temperature variations of these sensing elements.
Moreover, since also the internal threshold spreads, the Rg design has to consider the
minimum value IOCTH(min) of the threshold as follow:
I OCPx ( max ) ⋅ R SENSE ( max )
Rg = -----------------------------------------------------------------------
I OCTH ( min )

where IOCPx is the current measured by the current reading circuitry when the device enters
Quasi-Constant-Current. IOCPx must be calculated starting from the corresponding output
current value IOUT(OCP) as follow (ID-VID must also be considered when D-VID are
implemented) considering that the device performs Track & Hold only for the LS sense
mode:
⎧I
OUT ( OCP ) ∆I PP I D – VID
⎪ --------------------------
- – ------------ + ------------------ LowSideMosfetSense
⎪ N 2 N
I OCPx = ⎨
I
⎪ OUT ( OCP ) ∆I PP I D – VID
⎪ --------------------------
- + ------------ + ------------------ InductorDCRSense
⎩ N 2 N

where IOUT(OCP) is still the output current value at which the device enters Quasi-Constant-
Current, IPP is the inductor current ripple in each phase ID-VID is the additional current
required by D-VID (when applicable) and N the number of phases. In particular, since the
device limits the peak or the valley of the inductor current (according to DAC/CS_SEL
status), the ripple entity, when not negligible, impacts on the real OC threshold value and
must be considered.

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L6714 Over current protection

18.1 Low side MOSFET sense over current

The device detects an Over Current condition for each phase when the current information
IINFOx overcomes the fixed threshold of IOCTH (35µA Typ,). When this happens, the device
keeps the relative LS MOSFET on, also skipping clock cycles, until the threshold is crossed
back and IINFOx results being lower than the IOCTH threshold. After exiting the OC condition,
the LS MOSFET is turned off and the HS is turned on with a duty cycle driven by the PWM
comparator.
Keeping the LS on, skipping clock cycles, causes the on-time subsequent to the exit from
the OC condition, driven by the control loop, to increase. Considering now that the device
has a maximum on-time dependence with the delivered current given by the following
relationship:

⎧ 0.80 ⋅ T SW I DROOP = 0µA

T ON ( max ) = ⎨
⎩ 0.40 ⋅ T SW I DROOP = 140µA

Where IOUT is the output current ( I OUT = ΣI PHASEx ) and TSW is the switching period
(TSW=1/FSW). This linear dependence has a value at zero load of 0.80·TSW and at maximum
current of 0.40·TSW typical.
When the current information IINFOx overcomes the fixed threshold of IOCTH (35µA Typ), the
device enters in Quasi-Constant-Current operation: the low-side MOSFET stays ON until
the current read becomes lower than IOCPx (IINFOx < IOCTH) skipping clock cycles. The high
side MOSFET can be then turned ON with a TON imposed by the control loop after the LS
turn-off and the device works in the usual way until another OCP event is detected.
This means that the average current delivered can slightly increase in Quasi-Constant-
Current operation since the current ripple increases. In fact, the ON time increases due to
the OFF time rise because of the current has to reach the IOCPx bottom. The worst-case
condition is when the ON time reaches its maximum value.
When this happens, the device works in Constant Current and the output voltage decrease
as the load increase. Crossing the UVP threshold causes the device to latch (Figure 20
shows this working condition).
It can be observed that the peak current (IPEAK) is greater than IOCPx but it can be
determined as follow:
V IN – V OUT ( min ) V IN – V OUT ( min )
I PEAK = I OCPx + ------------------------------------------ ⋅ T ON ( max ) = I OCPx + ------------------------------------------ ⋅ 0.40 ⋅ T SW
L L

Where VoutMIN is the UVP threshold, (inductor saturation must be considered). When that
threshold is crossed, all MOSFET are turned OFF and the device stops working. Cycle the
power supply or the OUTEN pin to restart operation.
The maximum average current during the Constant-Current behavior results:
I PEAK – I OCPx⎞
I MAX, = N ⋅ I MAX = N ⋅ ⎛ I OCPx + ------------------------------------
tot ⎝ 2 ⎠

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Over current protection L6714

in this particular situation, the switching frequency for each phase results reduced. The ON
time is the maximum allowed TON(max) while the OFF time depends on the application:
I PEAK – I OCPx 1
T OFF = L ⋅ ------------------------------------ f = --------------------------------------------
-
V OUT T ON ( max ) + T OFF

Figure 20. Constant current

Constant Current (Exploded)

IPEAK VOUT

0.40 VIN
IMAX
Droop Effect

IOCPx

Quasi-Const.
Current
Limted-TON Char.
TON(max) LS ON Skipping TON(max) Resulting Out. Char.
Clock Cycles
UVP Threshold

IOUT
IOCP = 4 x IOCPx IMAX,tot
TSW TSW (IDROOP = 140µA)

The trans-conductance resistor Rg can be designed considering that the device limits the
bottom of the inductor current ripple and also considering the additional current delivered
during the quasi-constant-current behavior as previously described in the worst case
conditions.
Moreover, when designing D-VID compatible systems, the additional current due to the
output filter charge during dynamic VID transitions must be considered.
I OCPx ( max ) ⋅ R SENSE ( max )
Rg = -----------------------------------------------------------------------
I OCTH ( min )

where
I OUT ( OCP ) ∆I PP I D – VID
I OCPx = --------------------------
- – ------------ + ------------------
N 2 N

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L6714 Over current protection

18.2 Inductor sense over current

The device detects an over current when the IINFOx overcome the fixed threshold IOCTH.
Since the device always senses the current across the inductor, the IOCTH crossing will
happen during the HS conduction time: as a consequence of OCP detection, the device will
turn OFF the HS MOSFET and turns ON the LSMOSFET of that phase until IINFOx re-cross
the threshold or until the next clock cycle. This implies that the device limits the peak of the
inductor current.
In any case, the inductor current won't overcome the IOCPx value and this will represent the
maximum peak value to consider in the OC design.
The device works in Constant-Current, and the output voltage decreases as the load
increase, until the output voltage reaches the UVP threshold. When this threshold is
crossed, all MOSFETs are turned off and the device stops working. Cycle the power supply
or the OUTEN pin to restart operation.
The transconductance resistor Rg can be designed considering that the device limits the
inductor current ripple peak. Moreover, when designing D-VID systems, the additional
current due to the output filter charge during dynamic VID transitions must be considered.
I OCPx ( max ) ⋅ R SENSE ( max )
Rg = -----------------------------------------------------------------------
I OCTH ( min )

where
I OUT ( OCP ) ∆I PP I D – VID
I OCPx = --------------------------
- + ------------ + ------------------
N 2 N

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Oscillator L6714

19 Oscillator

L6714 embeds four phase oscillator with optimized phase-shift (90º phase-shift) in order to
reduce the input rms current and optimize the output filter definition.
The internal oscillator generates the triangular waveform for the PWM charging and
discharging with a constant current an internal capacitor. The switching frequency for each
channel, FSW, is internally fixed at 150kHz so that the resulting switching frequency at the
load side results in being multiplied by N (number of phases).
The current delivered to the oscillator is typically 25µA (corresponding to the free running
frequency FSW = 150kHz) and it may be varied using an external resistor (ROSC) connected
between the OSC pin and SGND or VCC (or a fixed voltage greater than 1.24V). Since the
OSC pin is fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced)
from (into) the pin considering the internal gain of 6KHz/µA.
In particular connecting ROSC to SGND the frequency is increased (current is sunk from the
pin), while connecting ROSC to VCC = 12V the frequency is reduced (current is forced into
the pin), according the following relationships:
ROSC vs. SGND
3
1.240V kHz 7.422 ⋅ 10 ·
F SW = 150 ( kHz ) + --------------------------- ⋅ 6 ----------- = 150 ( kHz ) + ------------------------------- ⇒R OSC ( kΩ) = -----------
R OSC ( kΩ) µA R OSC ( kΩ) F SW

3 3
Hz- 7.422 ⋅ 10 · 7.422 ⋅ 10
-------- = 150 ( kHz ) + ------------------------------- ⇒R OSC ( kΩ) = -----------------------------------------------------------
- [ kΩ]
µA R OSC ( kΩ) F SW ( kHz ) – 150 ( kHz )

ROSC vs. +12V

4
12V – 1.240V kHz 6.456 ⋅ 10 ⇒R
F SW = 150 ( kHz ) – ------------------------------------ ⋅ 6 ----------- = 150 ( kHz ) – ------------------------------- OSC ( kΩ) = -----
R OSC ( kΩ) µA R OSC ( kΩ) 15

4 4
kHz ⋅ 10 ⇒R 6.456 ⋅ 10
6 ----------- = 150 ( kHz ) – 6.456
------------------------------- ( kΩ) = -----------------------------------------------------------
- [ kΩ]
µA R OSC ( kΩ) OSC
150 ( kHz ) – F SW ( kHz )

When using the Low-Side MOSFETs current sense, the maximum programmable switching
frequency per phase must be limited to 500kHz to avoid current reading errors causing, as a
consequence, current sharing errors.
Anyway, device power dissipation must be checked prior to design high switching frequency
systems.

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L6714 Oscillator

Figure 21. ROSC vs. switching frequency

7000

6000

Rosc [kOhms] to +12V

5000

4000

3000

2000

1000

0
25 50 75 100 125 150
Fsw [kHz] Selected

550
500

450
Rosc [kOhms] to SGND

400
350

300
250

200
150
100

50
0
150 250 350 450 550 650 750 850 950 1050
Fsw [kHz] Programmed

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Driver section L6714

20 Driver section

The integrated high-current drivers allow using different types of power MOS (also multiple
MOS to reduce the equivalent RdsON), maintaining fast switching transition.
The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for
return. The drivers for the low-side MOSFETs use VCCDRx pin for supply and PGNDx pin
for return. A minimum voltage at VCCDRx pin is required to start operations of the device.
VCCDRx pins must be connected together.
The controller embodies a sophisticated anti-shoot-through system to minimize low side
body diode conduction time maintaining good efficiency saving the use of Schottky diodes:
when the high-side MOSFET turns off, the voltage on its source begins to fall; when the
voltage reaches 2V, the low-side MOSFET gate drive is suddenly applied. When the low-
side MOSFET turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the
high-side MOSFET gate drive is suddenly applied.
If the current flowing in the inductor is negative, the source of high-side MOSFET will never
drop. To allow the turning on of the low-side MOSFET even in this case, a watchdog
controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side
MOSFET is switched on so allowing the negative current of the inductor to recirculate. This
mechanism allows the system to regulate even if the current is negative.
The BOOTx and VCCDRx pins are separated from IC's power supply (VCC pin) as well as
signal ground (SGND pin) and power ground (PGNDx pin) in order to maximize the
switching noise immunity. The separated supply for the different drivers gives high flexibility
in MOSFET choice, allowing the use of logic-level MOSFET. Several combination of supply
can be chosen to optimize performance and efficiency of the application.
Power conversion input is also flexible; 5V, 12V bus or any bus that allows the conversion
(See maximum duty cycle limitations) can be chosen freely.

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L6714 System control loop compensation

21 System control loop compensation

The control loop is composed by the Current Sharing control loop (See Figure 8) and the
Average Current Mode control loop. Each loop gives, with a proper gain, the correction to
the PWM in order to minimize the error in its regulation: the Current Sharing control loop
equalize the currents in the inductors while the Average Current Mode control loop fixes the
output voltage equal to the reference programmed by VID. Figure 22 shows the block
diagram of the system control loop.
The system Control Loop is reported in Figure 23. The current information IDROOP sourced
by the DROOP pin flows into RFB implementing the dependence of the output voltage from
the read current.

Figure 22. Main control loop

L4
PWM4
1/5
L3
PWM3
1/5
L2
PWM2 COUT ROUT
1/5
L1
PWM1
1/5
ERROR AMPLIFIER
VREF

4/5

IDROOP
IINFO1
CURRENT SHARING IINFO2
DUTY CYCLE IINFO3 COMP FB DROOP
CORRECTION
IINFO4
ZF(s) ZFB(s)

The system can be modeled with an equivalent single phase converter which only difference
is the equivalent inductor L/N (where each phase has an L inductor).The Control Loop gain
results (obtained opening the loop after the COMP pin):
PWM ⋅ Z F ( s ) ⋅ ( R DROOP + Z P ( s ) )
G LOOP ( s ) = – ------------------------------------------------------------------------------------------------------------------------
-
ZF ( s ) ⎛
+ 1 + ------------⎞ ⋅ R FB
1
[ Z P ( s ) + Z L ( s ) ] ⋅ --------------
A( s) ⎝ A ( s )⎠

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System control loop compensation L6714

Where:
● RSENSE is the MOSFET RdsON or the Inductor DCR depending on the sensing element
selected;
R SENSE
● R DROOP = --------------------- ⋅ R FB is the equivalent output resistance determined by the droop
Rg
function;
● ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR)
and the applied load RO;
● ZF(s) is the compensation network impedance;
● ZL(s) is the parallel of the N inductor impedance;
● A(s) is the error amplifier gain;
4 V IN
● PWM = --- ⋅ ------------------- is the PWM transfer function where ∆VOSC is the oscillator ramp
5 ∆V OSC

amplitude and has a typical value of 4V.

Removing the dependence from the Error Amplifier gain, so assuming this gain high
enough, and with further simplifications, the control loop gain results:

4 V IN Z F ( s ) R O + R DROOP 1 + s ⋅ C O ⋅ ( R DROOP //R O + ESR )

G ( s ) = – --- ⋅ ---------------------- ⋅ --------------- ⋅ -------------------------------------------- ⋅ -------------------------------------------------------------------------------------------------------------------------------------------------------------
LOOP 5 ∆V R R 2 R
OSC FB L L L L
R + -------
O N s ⋅ C O ⋅ ----- + s ⋅ ---------------------- + C O ⋅ ESR + C O ⋅ ------- + 1
N N ⋅ RO N

The system Control Loop gain (See Figure 23) is designed in order to obtain a high DC gain
to minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the
desired crossover frequency ωT. Neglecting the effect of ZF(s), the transfer function has one
zero and two poles; both the poles are fixed once the output filter is designed (LC filter
resonance ωLC) and the zero (ωESR) is fixed by ESR and the Droop resistance.

Figure 23. Equivalent control loop block diagram (left) and bode diagram (right).

d VOUT L / N VOUT
PWM dB
ESR
RO
CO
REMOTE BUFFER
GLOOP(s)
64k
IDROOP

VID 64k
VOUT FBG K
ZF(s)
FBR RF[dB]
64k
DROOP FB COMP

RF CF VSEN
ZF(s) ωLC = ωF ω
ωT
ωESR
RFB
ZFB(s)

To obtain the desired shape an RF - CF series network is considered for the ZF(s)
implementation. A zero at ωF = 1/RFCF is then introduced together with an integrator. This
integrator minimizes the static error while placing the zero ωF in correspondence with the L-
C resonance assures a simple -20dB/dec shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.

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L6714 System control loop compensation

Compensation network can be simply designed placing ωF=ωLC and imposing the cross-over
frequency ωT as desired obtaining (always considering that ωT might be not higher than
1/10th of the switching frequency FSW):
R FB ⋅ ∆V OSC 5 L
R F = ------------------------------------- ⋅ --- ⋅ ωT ⋅ -----------------------------------------------------------
V IN 4 N ⋅ ( R DROOP + ESR )

L
C O ⋅ ----
N
CF = ------------------------
RF

21.1 Compensation network guidelines

The Compensation Network design assures to having system response according to the
cross-over frequency selected and to the output filter considered: it is anyway possible to
further fine-tune the compensation network modifying the bandwidth in order to get the best
response of the system as follow (See Figure 24):
● Increase RF to increase the system bandwidth accordingly;
● Decrease RF to decrease the system bandwidth accordingly;
● Increase CF to move ωF to low frequencies increasing as a consequence the system
phase margin.
Having the fastest compensation network gives not the confidence to satisfy the
requirements of the load: the inductor still limits the maximum dI/dt that the system can
afford. In fact, when a load transient is applied, the best that the controller can do is to
“saturate” the duty cycle to its maximum (dMAX) or minimum (0) value. The output voltage
dV/dt is then limited by the inductor charge / discharge time and by the output capacitance.
In particular, the most limiting transition corresponds to the load removal since the inductor
results being discharged only by VOUT (while it is charged by dMAXVIN-VOUT during a load
appliance).
Referring to Figure 24-left, further tuning the Compensation network cannot give any
improvements unless the output filter changes: only modifying the main inductors ot the
output capacitance improves the system response.

Figure 24. RF-CF impact on bandwidth.

dB

CF

GLOOP(s)

RF[dB] ZF(s)

RF

ωLC = ωF ω
ωT
ωESR

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Thermal monitor L6714

22 Thermal monitor

L6714 continuously senses the system temperature through TM pin: depending on the
voltage sensed by this pin, the device sets free the VR_FAN pin as a warning and, after
further temperature increase, also the VR_HOT pin as an alarm condition.
These signals can be used to give a boost to the system fan (VR_FAN) and improve the VR
cooling, or to initiate the CPU low power state (VR_HOT) in order to reduce the current
demand from the processor so reducing also the VR temperature. In a different manner,
VR_FAN can be used to initiate the CPU low power state so reducing the processor current
requirements and VR_HOT to reset the system in case of further dangerous temperature
increase.
Thermal sensors is external to the PWM control IC since the controller is normally not
located near the heat generating components: it is basically composed by a NTC resistor
and a proper biasing resistor RTM. NTC must be connected as close as possible at the
system hot-spot in order to be sure to control the hottest point of the VR.
Typical connection is reported in Figure 25 that also shows how the trip point can be easily
programmed by modifying the divider values in order to cross the VR_FAN and VR_HOT
thresholds at the desired temperatures.
Both VR_HOT and VR_FAN are active high and open drain outputs. Thermal Monitoring
Output are enabled if Vcc > UVLOVCC.

Figure 25. System thermal monitor typical connections.

+5V

Sense Element
(Place remotely, near Hot Spot)

TM

RTM

TM Voltage - NTC=3300/4250K
4.00
3.80

3.60
3.40
TM Voltage[V]

3.20

3.00
2.80
2.60 Rtm = 330
2.40 Rtm = 390
2.20 Rtm = 470
2.00
80 85 90 95 100 105 110 115 120
Temperature [degC]

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L6714 Tolerance band (TOB) definition

23 Tolerance band (TOB) definition

Output voltage load-line varies considering component process variation, system

temperature extremes, and age degradation limits. Moreover, individual tolerance of the
components also varies among designs: it is then possible to define a Manufacturing
Tolerance Band (TOBManuf) that defines the possible output voltage spread across the
nominal load line characteristic.
TOBManuf can be sliced into different three main categories: Controller Tolerance, External
Current Sense Circuit Tolerance and Time Constant Matching Error Tolerance. All these
parameters can be composed thanks to the RSS analysis so that the manufacturing
variation on TOB results to be:
2 2 2
TOB Manuf = TOB Controller + TOB CurrSense + TOB TCMatching

Output voltage ripple (VP = VPP/2) and temperature measurement error (VTC) must be
added to the Manufacturing TOB in order to get the system Tolerance Band as follow:

TOB = TOB Manuf + V P + V TC

All the component spreads and variations are usually considered at 3σ. Here follows an
explanation on how to calculate these parameters for a reference L6714 application.

23.1 Controller tolerance (TOB controller)

It can be further sliced as follow:
● Reference tolerance. L6714 is trimmed during the production stage to ensure the
output voltage to be within kVID = ±0.5% (±0.6% for AMD DAC) over temperature and
line variations. In addition, the device automatically adds a -19mV offset (Only for Intel
Mode) avoiding the use of any external component. This offset is already included
during the trimming process in order to avoid the use of any external circuit to generate
this offsets and, moreover, avoiding the introduction of any further error to be
considered in the TOB calculation.
● Current Reading Circuit. The device reads the current flowing across the MOSFET
RdsON or the inductor DCR by using its dedicated differential inputs. The current
sourced by the VRD is then reproduced and sourced from the DROOP pin scaled down
by a proper designed gain as follow:
R SENSE
I DROOP = --------------------- ⋅ I OUT
Rg

This current multiplied by the RFB resistor connected from FB pin vs. the load allows
programming the droop function according to the selected RL/Rg gain and RFB resistor.
Deviations in the current sourced due to errors in the current reading, impacts on the output
voltage depending on the size of RFB resistor. The device is trimmed during the production
stage in order to guarantee a maximum deviation of kIFB = ±1µA from the nominal value.
Controller tolerance results then to be:

2 2
TOB Controller = [ ( VID – 19mV ) ⋅ k VID ] + ( k IDROOP ⋅ R FB )

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Tolerance band (TOB) definition L6714

23.2 Ext. current sense circuit tolerance

(TOB CurrSense - Inductor Sense)
It can be further sliced as follow:
● Inductor DCR Tolerance (kDCR). Variations in the inductor DCR impacts on the output
voltage since the device reads a current that is different from the real current flowing
into the sense element. As a results, the controller will source a IDROOP current different
from the nominal. The results will be an AVP different from the nominal in the same
percentage as the DCR is different from the nominal. Since all the sense elements
results to be in parallel, the error related to the inductor DCR has to be divided by the
number of phases (N).
● Trans-conductance resistors tolerance (kRg). Variations in the Rg resistors impacts in
the current reading circuit gain and so impacts on the output voltage. The results will be
an AVP different from the nominal in the same percentage as the Rg is different from
the nominal. Since all the sense elements results to be in parallel, and so the three
current reading circuits, the error related to the Rg resistors has to be divided by the
number of phases (N).
● NTC Initial Accuracy (kNTC_0). Variations in the NTC nominal value at room
temperature used for the thermal compensation impacts on the AVP in the same
percentage as before. In addition, the benefit of the division by the number of phases N
cannot be applied in this case.
● NTC Temperature Accuracy (kNTC). NTC variations from room to hot also impacts on
the output voltage positioning. The impact is bigger as big is the temperature variation
from room to hot (∆T).
● All these parameters impacts the AVP, so they must be weighted on the maximum
voltage swing from zero load up to the maximum electrical current (VAVP). Total error
from external current sense circuit results:

2 2
k DCR k Rg α ⋅ ∆T ⋅ k NTC 2
- + --------- + k NTC0 + ⎛⎝ ---------------------------------------⎞⎠
2 2
TOB CurrSense = V AVP ⋅ -------------
N N DCR

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L6714 Tolerance band (TOB) definition

23.3 Time constant matching error tolerance (TOB TCMatching)

● Inductance and capacitance Tolerance (kL, kC). Variations in the inductance value and
in the value of the capacitor used for the Time Constant Matching causes over/under
shoots after a load transient appliance. This impacts the output voltage and then the
TOB. Since all the sense elements results to be in parallel, the error related to the time
constant mismatch has to be divided by the number of phases (N).
● Capacitance Temperature Variations (kCt). The capacitor used for time constant
matching also vary with temperature (∆TC) impacting on the output voltage transients
ad before. Since all the sense elements results to be in parallel, the error related to the
time constant mismatch has to be divided by the number of phases (N).
● All these parameters impact the Dynamic AVP, so they must be weighted on the
maximum dynamic voltage swing (Idyn). Total error due to time constant mismatch
results:
2 2
2 k L + k C + ( k Ct ⋅ ∆TC )
TOB TCMatching = V AVPDyn ⋅ ---------------------------------------------------------
N

23.4 Temperature measurement error (VTC)

Error in the measured temperature (for thermal compensation) impacts on the output
regulated voltage since the correction form the compensation circuit is not what required to
keep the output voltage flat.
The measurement error (ε Temp) must be multiplied by the copper temp coefficient (α) and
compared with the sensing resistance (RSENSE): this percentage affects the AVP voltage as
follow:
α ⋅ ε Temp
V TC = -------------------------- ⋅ V AVP
R SENSE

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Layout guidelines L6714

24 Layout guidelines

Since the device manages control functions and high-current drivers, layout is one of the
most important things to consider when designing such high current applications. A good
layout solution can generate a benefit in lowering power dissipation on the power paths,
reducing radiation and a proper connection between signal and power ground can optimize
the performance of the control loops.
Two kind of critical components and connections have to be considered when layouting a
VRM based on L6714: power components and connections and small signal components
connections.

24.1 Power components and connections

These are the components and connections where switching and high continuous current
flows from the input to the load. The first priority when placing components has to be
reserved to this power section, minimizing the length of each connection and loop as much
as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections
must be a part of a power plane and anyway realized by wide and thick copper traces: loop
must be anyway minimized. The critical components, i.e. the power transistors, must be
close one to the other. The use of multi-layer printed circuit board is recommended.
Figure 26 shows the details of the power connections involved and the current loops. The
input capacitance (CIN), or at least a portion of the total capacitance needed, has to be
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
Connect output bulk capacitor as near as possible to the load, minimizing parasitic
inductance and resistance associated to the copper trace also adding extra decoupling
capacitors along the way to the load when this results in being far from the bulk capacitor
bank.
Gate traces must be sized according to the driver RMS current delivered to the power
MOSFET. The device robustness allows managing applications with the power section far
from the controller without losing performances. External gate resistors help the device to
dissipate power resulting in a general cooling of the device. When driving multiple
MOSFETs in parallel, it is suggested to use one resistor for each MOSFET.

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L6714 Layout guidelines

24.2 Small signal components and connections

These are small signal components and connections to critical nodes of the application as
well as bypass capacitors for the device supply (See Figure 26). Locate the bypass
capacitor (VCC, VCCDRx and Bootstrap capacitor) close to the device and refer sensible
components such as frequency set-up resistor ROSC, offset resistor ROFFSET and OVP
resistor ROVP to SGND. Star grounding is suggested: connect SGND to PGND plane in a
single point to avoid that drops due to the high current delivered causes errors in the device
behavior.
VSEN pin filtered vs. SGND helps in reducing noise injection into device and OUTEN pin
filtered vs. SGND helps in reducing false trip due to coupled noise: take care in routing
driving net for this pin in order to minimize coupled noise.

Warning: Boot Capacitor Extra Charge. Systems that do not use

Schottky diodes might show big negative spikes on the
phase pin. This spike can be limited as well as the positive
spike but has an additional consequence: it causes the
bootstrap capacitor to be over-charged. This extra-charge
can cause, in the worst case condition of maximum input
voltage and during particular transients, that boot-to-phase
voltage overcomes the abs. max. ratings also causing device
failures. It is then suggested in this cases to limit this extra-
charge by adding a small resistor in series to the boot diode
(one resistor can be enough for all the three diodes if placed
upstream the diode anode, See Figure 26) and by using
standard and low-capacitive diodes.

Figure 26. Power connections and related connections layout (same for all phases).

To limit C Extra-Charge
BOOT
VIN VIN

BOOTx
CBOOT

UGATEx CIN CIN

PHASEx
L PHASEx L

VCC
LGATEx LOAD LOAD
PGNDx SGND
+Vcc

Remote Buffer Connection must be routed as parallel nets from the FBG/FBR pins to the
load in order to avoid the pick-up of any common mode noise. Connecting these pins in
points far from the load will cause a non-optimum load regulation, increasing output
tolerance.
Locate current reading components close to the device. The PCB traces connecting the
reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up
of any common mode noise. It's also important to avoid any offset in the measurement and,
to get a better precision, to connect the traces as close as possible to the sensing elements.
Symmetrical layout is also suggested. Small filtering capacitor can be added, near the
controller, between VOUT and SGND, on the CSx- line when reading across inductor to allow
higher layout flexibility.

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Embedding L6714 - Based VR L6714

25 Embedding L6714 - Based VR

When embedding the VRD into the application, additional care must be taken since the
whole VRD is a switching DC/DC regulator and the most common system in which it has to
work is a digital system such as MB or similar. In fact, latest MB has become faster and
powerful: high speed data bus are more and more common and switching-induced noise
produced by the VRD can affect data integrity if not following additional layout guidelines.
Few easy points must be considered mainly when routing traces in which high switching
currents flow (high switching currents cause voltage spikes across the stray inductance of
the trace causing noise that can affect the near traces):
Keep safe guarding distance between high current switching VRD traces and data buses,
especially if high-speed data bus to minimize noise coupling.
Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that
must walk near the VRD.
Possible causes of noise can be located in the PHASE connections, MOSFET gate drive
and Input voltage path (from input bulk capacitors and HS drain). Also PGND connections
must be considered if not insisting on a power ground plane. These connections must be
carefully kept far away from noise-sensitive data bus.
Since the generated noise is mainly due to the switching activity of the VRM, noise
emissions depend on how fast the current switches. To reduce noise emission levels, it is
also possible, in addition to the previous guidelines, to reduce the current slope by properly
tuning the HS gate resistor and the PHASE snuber network.

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L6714 Package mechanical data

26 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

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Package mechanical data L6714

Table 13. TQFP64 mechanical data

mm. inch
Dim.
Min Typ Max Min Typ Max

A 1.20 0.0472
A1 0.05 0.15 0.002 0.006
A2 0.95 1.00 1.05 0.0374 0.0393 0.0413
b 0.17 0.22 0.27 0.0066 0.0086 0.0086
c 0.09 0.20 0.0035 0.0078
D 11.80 12.00 12.20 0.464 0.472 0.480
D1 9.80 10.00 10.20 0.386 0.394 0.401
D2 3.50 6.10 0.1378 0.2402
D3 7.50 0.295
E 11.80 12.00 12.20 0.464 0.472 0.480
E1 9.80 10.00 10.20 0.386 0.394 0.401
E2 3.50 6.10 0.1378 0.2402
E3 7.50 0.295
e 0.50 0.0197
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0393
k 0° 3.5° 7° 0° 3.5° 7°
ccc 0.080 0.0031

Figure 27. Package dimensions

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L6714 Revision history

27 Revision history

Table 14. Revision history

Date Revision Changes

16-Mar-2006 1 Initial release.

Updated KIDROOP, KIOFFSET values in Table 4: Electrical
02-Aug-2006 2
characteristics on page 14.
Updated D2 and E2 exposed tab measures in Table 13:
07-Nov-2006 3
TQFP64 mechanical data.

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Revision history L6714

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