Thanks to visit codestin.com
Credit goes to www.scribd.com

Scribd
Upload
44 views8 pages

Lec 6

This document discusses cache coherence in multiprocessor systems with shared memory. It begins by describing shared memory multiprocessors and how caching can reduce memory bandwidth demands but introduces the problem of cache coherence when multiple caches are present. It defines what it means for a memory system to be coherent, including that reads must return the most recently written value and writes must be serialized. Maintaining cache coherence is critical for writing correct shared memory programs.

Uploaded by

Sayantani Dutta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
44 views8 pages

Lec 6

This document discusses cache coherence in multiprocessor systems with shared memory. It begins by describing shared memory multiprocessors and how caching can reduce memory bandwidth demands but introduces the problem of cache coherence when multiple caches are present. It defines what it means for a memory system to be coherent, including that reads must return the most recently written value and writes must be serialized. Maintaining cache coherence is critical for writing correct shared memory programs.

Uploaded by

Sayantani Dutta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 8

• Shared memory Processor

Distributed memory processor


Basic structure of centralized shared memory
multiprocessor
• The use of large multilevel caches can substantially reduce memory
bandwidth demands of a processor.

• This has made it possible for several (micro)processors to share the same
memory through a shared bus.

• Caching supports both private and shared data.


– For private data, once cached, it's treatment is identical to that of a
uniprocessor.
– For shared data, the shared value may be replicated in many caches.

• it also introduces a problem: Cache coherence


Cache Coherence
• With multiple caches, one CPU can modify memory at locations that other
CPUs have cached.

• For example:
• CPU A reads location x, getting the value N .
• Later, CPU B reads the same location, getting the value N .
• Next, CPU A writes location x with the value N - 1 .
• At this point, any reads from CPU B will get the value N ,
while reads from CPU A will get the value N - 1 .

• This problem occurs both with write-through caches and (more seriously)
with write-back caches.
Another example…
Multiprocessor Cache Coherence
• Memory system is coherent, if any read of a data item returns the most
recently written value of that data item.
• This definition, is vague and simplistic; the reality is much more complex.
• This simple definition contains two different aspects of memory system
behaviour, which are critical to writing correct shared-memory programs.
– The first aspect, called coherence, defines what values can be
returned by a read.
– The second aspect, called consistency, determines when a written
value will be returned by a read.
A memory system is coherent if
1. A read by a processor P to a location X that follows a write by P to X,
with no writes of X by another processor occurring between the write and
the read by P, always returns the value written by P.

2. A read by a processor to location X that follows a write by another


processor to X returns the written value if the read and write are
sufficiently separated in time and no other writes to X occur between the
two accesses.

3. Writes to the same location are serialized; that is, two writes to the same
location by any two processors are seen in the same order by all
processors.

4. For example: If the values 1 and then 2 are written to a location,


processors can never read the value of the location as 2 and then later
read it as 1.

You might also like