BOOLEAN ALGEBRA

❑ Developed by George Boole, an English mathematician.

❑ Called the Algebra of Logic – True or False

❑ Used to analyze and simplify digital circuits

❑ It provides a framework for working with binary variables and logical operations, forming the
foundation of modern digital electronics.

❑ Cost of the circuits is an important aspect and finding simpler and cheaper equivalent circuits helps in
reducing the cost.

❑ Boolean algebra aids in designing and optimizing digital circuits by simplifying complex expressions.
 LOGICAL OPERATORS
❑ Binary Variables:
In digital electronics, information is represented using binary variables: 0 (False) and 1 (True). Boolean
algebra operates on these binary variables to derive logical outcomes.

❑ Logical Operations:
Fundamental logical operators:
AND: Represents logical conjunction, denoted by ∧.
OR: Represents logical disjunction, denoted by ∨.
NOT: Represents logical negation, denoted by ¬.

AND operator

A B X A.B or AB or A∧B
0 0 0
0 1 0
1 0 0
1 1 1
 LOGICAL OPERATORS
OR operator

A B X A + B or A ∨ B
0 0 0
0 1 1
1 0 1
1 1 1

NOT operator

A X A’ or A or ¬A
0 1
1 0

❑ Truth table enlists all possible values of variables in a Boolean expression.

❑ No. of possible combinations = 2n where n – no. of variables

TRUTH TABLE
Truth Table for A’ + BC
A B C A’ BC A’ + BC

0 0 0 1 0 1
Using truth table verify that (A + B)’ = A’ + B’.
0 0 1 1 0 1

0 1 0 1 0 1

0 1 1 1 1 1

1 0 0 0 0 0

1 0 1 0 0 0

1 1 0 0 0 0

1 1 1 0 1 1

❑ If the output of a Boolean expression is always TRUE it is called a Tautology and if its always FALSE it is
called a FALLACY.
Tautology
❑ Boolean Expression – A + A’, A + (AB)’
A.A’ Fallacy
 BOOLEAN ALGEBRA - BASICS
0+A=A, 0. A = 0

1 + A = 1, 1.A = A

DUALITY PRINCIPLE

❑ If a particular Boolean expression is true its dual is also true.

❑ To obtain the dual of a Boolean expression, interchange AND OR operators and 0 1.

❑ Examples A + 1 = 1, Dual - A.0 = 0

A.B + C = 1, Dual – (A + B).C = 0

 BOOLEAN ALGEBRA BASIC THEOREMS
❑ Commutative Law
i) A + B = B + A
ii) A.B = B.A

❑ Associative Law
i) (A + B) + C = A + (B + C)
ii) (A.B).C = A.(B.C)

❑ Distributive Law
i) A.(B + C) = A.B + A.C
ii) A + B.C = (A + B).(A + C) R.H.S = (A + B).(A + C) = A.A + A.C + B.A + B.C
iii) A + A’B = A + B = A .(1 + C) + B.A + B.C
L.H.S = A + A’B = (A + A’).(A + B)
= 1. (A + B) = A += B
A + B.A + B.C
= A.(1 + B) + B.C
❑ Idempotence (Identity) Law = A + B.C
i) A + A = A
ii) A.A = A
 BOOLEAN ALGEBRA BASIC THEOREMS
❑ Absorption (Redundance) Law
i) A + A.B = A A.(1 + B) = A.1 = A
ii) A.(A + B) = A A.A + A.B = A + A.B = A

❑ Complementary Law
i) A + A’ = 1
ii) A.A’ = 0

❑ Involution Law
A” = A

❑ Minimum no. of Logic gates required to implement i) A + A.B

ii) A + A’.B
 DE MORGAN’S THEOREMS
❑ The complement of a product of variables is equal to the sum of the complements of the variables.

(A.B)’ = A’ + B’

❑ The complement of a sum of variables is equal to the product of the complements of the variables.

(A + B)’ = A’.B’

❑ De Morgan’s Theorems also apply to expressions with more than two variables.

❑ Apply De-Morgan’s Theorem to the expressions i) (XYZ)’

ii) (X + Y + Z)’
iii) (X’ + Y’ + Z’)’
iv) (AB’ + C’D + EF)’
v) ((A’ + B) + CD)’
 DE MORGAN’S THEOREMS PROOF
❑ (A + B)’ = A’.B’

We know that X + X’ = 1
If X = A + B then (A + B) + (A + B)’ should be equal to 1
and if (A + B)’ = A’.B’ then (A + B) + A’.B’ should also be equal to 1.

(A + B) + A’.B’ = (A + B + A’).(A + B + B’)

= (1 + B).(1 + A) = 1.1 = 1

❑ (A.B)’ = A’ + B’
We know that X.X’ = 0
If X = A.B then (A.B).(A.B)’ should be equal to 0
and if (A.B)’ = A’ + B’ then (A.B).(A’ + B’) should also be equal to 0.

(A.B).(A’ + B’) = A.B.A’ + A.B.B’ = 0 + 0 = 0

OPERATOR PRECEDENCE
❑ Operator Precedence for evaluating Boolean expressions:
i) Parentheses
ii) NOT
iii) AND
iv) OR

Example - A.B + C.D

A.B + (C.D’ + A).C
(A + B)’

❑ Literal – A literal is a single variable within a term in a Boolean expression/function in

complemented or uncomplemented form.

Example – A’.B + A.C.B’ + B.C has 3 terms and 7 literals.

X.Y’ + X’.Z – 2 terms and 4 literals
BOOLEAN EXPRESSION REPRESENTATION
❑ Standard forms for representing Boolean Functions:

- Sum of Products (SOP) form

- Product of Sums (POS) form

❑ SOP form - AND OR Logic

Product – Multiplication of literals, one or more products

Sum – Two or more products are added
Example – AB + A’C
Convert ((A + B)’ + C)’ into SOP form.

❑ POS form - OR AND Logic

Sum – Boolean addition of literals

Product – Two or more sum terms are multiplied
Example – (A + B’)(A’ + C)
CANONICAL FORM OF BOOLEAN EXPRESSION
❑ Each term in the Boolean expression must contain all the literals used in the Boolean
expression.

❑ For a particular Boolean expression you can only have one canonical form.

❑ To convert SOP into canonical form, multiply each non-standard product term by a term
summing the missing variable and its complement.

❑ Consider AB + AC - Non-canonical
Canonical - AB(C + C’) + A(B + B’)C
= ABC + ABC’ + ABC + AB’C
= ABC + ABC’ + AB’C

❑ Convert AB’C + A’B’ + ABC’D into standard SOP form.

CANONICAL FORM OF BOOLEAN EXPRESSION
❑ To convert POS into canonical form, add a term multiplying the missing variable and its
complement to each non-standard product term.

❑ Consider (A + B)(A + C) – Non canonical

Canonical – (A + B + CC’)(A + BB’ + C)
= (A + B + C)(A + B + C’) (A + C + B)(A + C +B’)
= (A + B +C)(A + B + C’)(A + B’ + C)

❑ Convert (A + B)’(B + C) to standard POS form.

 MINTERM AND MAXTERM
❑ Individual term of Canonical SOP is called Minterm.

❑ Individual term of Canonical POS is called Maxterm.

❑ Consider two variables – A and B

SOP – A’B’ + A’B + AB’ + AB POS – (A’ + B’)(A’ + B)(A + B’)(A + B)

A B Term Minterm A B Term Maxterm

0 0 A’B’ m0 0 0 A+B M0
0 1 A’B m1 0 1 A + B’ M1
1 0 AB’ m2 1 0 A’ + B M2
1 1 AB m3 1 1 A’ + B’ M3
Maxterm is the complement of minterm.
MINTERMS AND MAXTERMS FOR THREE VARIABLES
❑ Boolean Function can be expressed as sum of minterms or product of maxterms.

❑ Consider f1 = x’y’z + xy’z’ + xyz

x y z x’ y’ z’ x’y’z xy’z’ xyz f1

0 0 0 1 1 1 0 0 0 0

0 0 1 1 1 0 1 0 0 1 m1
0 1 0 1 0 1 0 0 0 0

0 1 1 1 0 0 0 0 0 0

1 0 0 0 1 1 0 1 0 1 m4
1 0 1 0 1 0 0 0 0 0

1 1 0 0 0 1 0 0 0 0

1 1 1 0 0 0 0 0 1 1 m7

f1 = m1 + m4 + m7 = ∑(1, 4, 7)

❑ Find the minterm designation of xy’z’.

MINTERMS AND MAXTERMS FOR THREE VARIABLES
❑ Consider f2 = (a + b)(a’ + c)(b’ + c’)
a b c a’ b’ c’ a+b a’ + c b’ + c’ f2

0 0 0 1 1 1 0 1 1 0 M0

0 0 1 1 1 0 0 1 1 0 M1
0 1 0 1 0 1 1 1 1 1

0 1 1 1 0 0 1 1 0 0 M3

1 0 0 0 1 1 1 0 1 0 M4

1 0 1 0 1 0 1 1 1 1
M6
1 1 0 0 0 1 1 0 1 0

1 1 1 0 0 0 1 1 0 0 M7

f2 = M0M1M3M4M6M7 = π(0,1,3,4,6,7)
MINIMIZATION OF BOOLEAN EXPRESSION
❑ Canonical forms are usually not minimal.

❑ Minimization of Boolean expressions is required to reduce the circuit complexity.

❑ Methods – Algebraic Simplification

Karnaugh map (K map) Simplification

❑ Karnaugh Maps, often referred to as K-maps, are a graphical method used in Boolean Algebra
for simplifying Boolean expressions.

❑ They provide a visual and systematic approach to reducing complex Boolean expressions into
simpler forms.

❑ These are employed to simplify logical expressions that involve multiple variables and logic
gates.
GROUPING IN K-MAP GRID
❑ Once the Karnaugh Map (K-map) is populated with output values from the truth table, the next
step is to identify adjacent cells with a value of 1 (For SOP).

❑ Group these adjacent cells by drawing circles around them. These circles should encompass
cells that share common variables and differ by only one bit.

❑ Groups must be a rectangle — although this rectangle can wrap around the top or bottom of
the table.

❑ The sides of the rectangle must be a power of two: 1, 2, or 4.

❑ We must also ensure that:

i) Every 1 (in SOP) is covered by at least one group.
ii) 1s and 0s are not grouped.
iii) There are as few groups as possible. Overlapping is allowed.
iv) Each group is as large as possible.
GROUPING IN K-MAP GRID - EXAMPLES
K-MAP FOR TWO VARIABLES - SOP
Boolean expression = A’B’ + A’B + AB

Truth Table

A B Y Minterms are represented by 1 in the corresponding K-Map.

0 0 1
0 1 1 B B’ B
1 0 0 A 0 1
1 1 1
1 1
A’ 0
1
A 1
Any variable which is both 1 and 0 in this pairing can be eliminated. O/P – A’ + B

Simplify i) F(X,Y) = XY’ + X’Y + X’Y’.

ii) F (A,B) = A’B’ + AB’ + A’B + AB
iii) F (A,B) = A’B’ + AB
iv) F (X,Y) = ∑(1, 2)
K-MAP FOR TWO VARIABLES - POS
❑ Maxterms are represented by 0 in corresponding places.

❑ 0s are paired in place of 1s.

Example - F (x,y) = π(0, 2)

y
x 0 1
0 0
1 0

Output – y

Example - y = (A’ + B’)(A’ + B)(A + B)

B 0 1
A
Output - A’B
0 0
1 0 0
K-MAP FOR THREE VARIABLES
BC C BC
AB 0 1 A 00 01 11 10
A 00 01 11 10
m0 m1
m0 m1 m3 m2 00 A’B’C’ A’B’C A’BC A’BC’
0 0
1 m4 m5 m7 m6 m2 m3 1 AB’C’ AB’C ABC ABC’
01
m6 m7
11
BC
m4 m5 A 00 01 11 10
10 A+B+C A + B + C’ A + B’ + C’ A + B’ + C
0
❑ Simplify the Boolean function F(x,y,z) = ∑(2, 3, 4, 5) 1 A’ + B + C A’ + B + C’ A’ + B’ + C’ A’ + B’ + C
yz
x 00 01 11 10
1 1
0
1 1 1

Output - x’y + xy’

3 VARIABLE K-MAP

1. F(x,y,z) = ∑(3,4,6,7) 2. F(x,y,z) = ∑(0,2,4,5,6)

yz yz
x 00 01 11 10 x 00 01 11 10
0 1 0 1 1
1 1 1 1 1
1 1 1

yz + xz’ z’ + xy’

3. F(x,y,z) = ∑(1,2,4,7) 4. F(a,b,c) = ab’c + a’bc + a’b’c + a’b’c’ + ab’c’

bc
yz a 00 01 11 10
x 00 01 11 10
1 1 0 1 1 1
0
1 1 1
1 1 1

xy’z’ + x’y’z + xyz + x’yz’ b’ + a’c

4 VARIABLE K-MAP
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 m0 m1 m3 m2 00 A’B’C’D’ A’B’C’D A’B’CD A’B’CD’

m4 m5 m7 m6 A’BC’D’ A’BC’D A’BCD A’BCD’

01 01
m12 m13 m15 m14 ABC’D’ ABC’D ABCD ABCD’
11 11
m8 m9 m11 m10 AB’C’D’ AB’C’D AB’CD AB’CD’
10 10

CD
AB 00 01 11 10
00 A+B+C+D A + B + C + D’ A + B + C’ + D’ A + B + C’ + D

01 A + B’ + C + D A + B’ + C + D’ A + B’ + C’ + D’ A + B’ + C’ + D

A’ + B’ + C + D A’ + B’ + C + D’ A’ + B’ + C’ + D’ A’ + B’ + C’ + D
11
A’ + B + C + D A’ + B + C + D’ A’ + B + C’ + D’ A’ + B + C’ + D
10
4 VARIABLE K-MAP
F(A,B,C,D) = ∑(4,5,8,13) F(A,B,C,D) = ∑(0,2,4,8,10,12)

CD CD
AB 00 01 11 10 AB 00 01 11 10
00 00 1 1

01 1 1 1 01 1

11 1 11 1

10 10 1 1

BC’D + A’BD’ C’D’ + B’D’

4 VARIABLE K-MAP - POS
F(A,B,C,D) = π(4,5,7,13,14,15) F(A,B,C,D) = π(0,1,2,4,5,7,10,15)

CD CD
AB 00 01 11 10 AB 00 01 11 10
00 00 0 0 0

01 0 0 0 01 0 0 0

11 0 0 0 11 0

10 10 0

(B’ + D’)(A + B’ + C)(A’ + B’ + C’) (A + C)(B’ + C + D)(B + C’ + D)

DON’T CARE CONDITION
❑ Don't Care conditions are inputs for which the output is not important or undefined in certain
scenarios.

❑ These conditions can arise due to unspecified states or conditions that are not expected to occur.
Example – States 1010, 1011, 1100, 1101, 1110, 1111 in BCD code

❑ These states can be treated as don’t care since these do not have any effect on the output.

❑ Represented by X in K-map.

❑ We can treat their value as 0 or 1 as per our pairing convenience for simplifying the circuit.

❑ Consider f(x,y,z) = ∑(1,4) + ∑d(0,7)

yz
x 00 01 11 10
0 X 1
1 1 X
DON’T CARE CONDITION
F(w,x,y,z) = ∑(1,3,10) + ∑d(0,2,8,12)

yz
wx 00 01 11 10
00 X 1 1 X

01

11 X

10 X 1

w’x’ + x’z’

Simplify F(w,x,y,z) = ∑(1,3,7,11,15) + ∑d(0,2,5)

 5 VARIABLE K-MAP
❑ 5 Variable K-map can be constructed using two 4 variable K-maps.

❑ If our input variables are A,B,C,D and E then there would be two K-maps with inputs B,C,D and E
and A would be 0 for one K-map and 1 for second K-map.

DE DE
BC 00 01 11 10 BC 00 01 11 10
00 00

01 01

11 11

10 10
A=0 A=1

❑ The cell adjacencies can be understood by visualizing that the A = 0 map is placed on top of the A= 1
map.
 5 VARIABLE K-MAP
❑ F(A,B,C,D,E) = ∑(2,5,6,7,8,9,10,12,13,14,18,21,22,23,25,26,30)

DE DE
BC 00 01 11 10 BC 00 01 11 10
00 1 Grouping -3 00 1

01 1 1 1 01 1 1 1 Group 1 – DE’
Group 2 – A’BD’
1 1 1 1 Group 3 – B’CE
11 11
Group 4 – BC’D’E
1 1 1 1 1
10 10
Grouping -4

A=0 A=1
Grouping -2
Grouping -1

DE’ + A’BD’ + B’CE + BC’D’E

IMPLICANTS
❑ Implicant is a product term/minterm in Sum of Products (SOP) or sum term/maxterm in Product of
Sums (POS) of a Boolean function. E.g., consider a boolean function, F = AB + ABC + BC.
Implicants are AB, ABC, and BC.

❑ Prime Implicants: All possible groups formed in K-Map.

1 1
1 1 Prime Implicants = 3

❑ Essential Prime Implicants: Subcubes(groups) that cover at least one minterm that can’t be covered
by any other prime implicant. In the above example EPI = 2

❑ Redundant Prime Implicants: Each term in the pairing is covered in some EPI. In above example
RPI = 1
1 1
❑ Selective Prime Implicants: Neither essential nor redundant
SPI = 2 1 1 1
 Quine-McCluskey (QM) METHOD
❑ K-map simplification is not very convenient for large number of inputs.

❑ For larger number of inputs, QM method is preferred for simplification.

❑ Basic Procedure:

1. Arrange the given minterms according to the number of ones present in their binary representation
(Index) in ascending order.

2. Consider the minterms from adjoining groups, if there is only a one-bit change to make their pair.
Place the ‘-‘ symbol where there is a bit change accordingly and keep the remaining bits the same.

3. Repeat step 2 until we get all prime implicants (when all the bits present in the table are different).

4. Make a prime implicant table that consists of the prime implicants (obtained minterms) as rows and
the given minterms (given in problem) as columns.
 Quine-McCluskey (QM) METHOD
5. Place ‘X’ in the minterms (cell) which are covered by each prime implicant.

6. Observe the table, if the minterm is covered by only one prime implicant then it is an essential to
prime implicant.

7. Add the essential prime implicants.

8. After the essential prime implicants are, delete the dominated rows and dominating columns to find
selective prime implicants.
 Quine-McCluskey (QM) METHOD
F(w,x,y,z) = ∑(0,5,7,8,9,10,11,14,15)

Index Decimal Binary

0 0 0000
1 8 1000
2 5 0101
9 1001
10 1010
3 7 0111
11 1011
14 1110
4 15 1111
 Quine-McCluskey (QM) METHOD
F(w,x,y,z) = ∑(0,5,7,8,9,10,11,14,15)

Index Decimal Binary First Reduction

Decimal Binary

0 0✓ 0000 0,8 _000

1 8✓ 1000
2 5✓ 0101 8,9 100_
8,10 10_0
9✓ 1001
10✓ 1010
3 7✓ 0111 5,7 01_1
9,11 10_1
11✓ 1011
10,11 101_
14✓ 1110 10,14 1_10

4 15✓ 1111 7,15 _111

11,15 1_11
14,15 111_
 Quine-McCluskey (QM) METHOD
F(w,x,y,z) = ∑(0,5,7,8,9,10,11,14,15)

Index Decimal Binary First Reduction Second Reduction

Decimal Binary Decimal Binary

0 0 0000✓ 0,8 _000 A

1 8 1000✓
2 5 0101✓ 8,9 100_✓ 8,9,10,11 10_ _ D
8,10 10_0✓
9 1001✓
10 1010✓ B

3 7 0111✓ 5,7 01_1 10,11,14,15 1_1_ E

9,11 10_1✓
11 1011✓
10,11 101_✓
14 1110✓ 10,14 1_10✓

4 15 1111✓ 7,15 _111 C

11,15 1_11✓
14,15✓ 111_✓
 Quine-McCluskey (QM) METHOD
F(w,x,y,z) = ∑(0,5,7,8,9,10,11,14,15)

Prime Minterms
Implicants
0 5 7 8 9 10 11 14 15

A X X
B X X
C X X
D X X X X
E X X X X
 Quine-McCluskey (QM) METHOD
F(w,x,y,z) = ∑(0,5,7,8,9,10,11,14,15)

Prime Minterms
Implicants
0 5 7 8 9 10 11 14 15

A X X
B X X
C X X
D X X X X
E X X X X

A + B + D + E = x’y’z’ + w’xz + wx’ + wy

 Quine-McCluskey (QM) METHOD
F(v,w,x,y,z) = ∑(5,7,11,12,27,29) + ∑d(14,20,21,22,23)

Index Decimal Binary First Reduction Second Reduction

Decimal Binary Decimal Binary

2 5 00101✓ 5,7✓ 001_1 5,7,21,23 _01_1 D

5,21✓ _0101 20,21,22,23 101_ _
12 01100✓ 12,14 A 011_0
20,21✓ 1010_
20 10100✓
20,22✓ 101_0
3 7 00111✓ 7,23✓ _0111
11,27B _1011
11 01011✓ 21,23✓ 101_1
21,29 C 1_101
14 01110✓
22,23✓ 1011_
21 10101✓

22 10110✓

4 23 10111✓

27 11011✓

29 11101✓
 Quine-McCluskey (QM) METHOD
F(v,w,x,y,z) =∑(5,7,11,12,27,29) + ∑d (14,20,21,22,23)

Prime Minterms
Implicants
5 7 11 12 27 29

A X
B X X
C X
D X X

A+B+C+D v’wxz’ + wx’yz + vx’yz + w’xz

NAND AND NOR IMPLEMENTATION
❑ A universal gate is a logic gate which can implement any Boolean function without using any other type of logic
gate.

❑ The NOR and NAND gates are universal gates. We can create any logical Boolean expression using only NOR
gates or only NAND gates.

❑ In practice, this is advantageous since NOR and NAND gates are economical and easier to fabricate than other
logic gates.

❑ An AND gate is typically implemented as a NAND gate followed by an inverter. Similarly, an OR gate is typically
realized as a NOR gate followed by an inverter.

❑ Other logical gates – such as AND gates, NOT gates and OR gates – do not have this property of universality.
NAND GATE AS A UNIVERSAL GATE
Y = AB

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

1. NAND Gate as NOT Gate

NAND Gate O/P if A = B Y = AA or BB

A B Y
A Y
0 0 1
0 1
1 1 0
1 0
NAND GATE AS A UNIVERSAL GATE
2. NAND Gate as AND Gate
A B Y Y or Z
Y = AB, Y = AB = AB 0 0 1 0
0 1 1 0
1 0 1 0
1 1 0 1

3. NAND Gate as OR Gate

OR Gate O/P Z = A + B = A + B = A B A B A B Y
0 0 1 1 0
A 0 1 1 0 1
AB 1 0 0 1 1
1 1 0 0 1

B
NAND GATE AS A UNIVERSAL GATE
4. NAND Gate as NOR Gate

NOR Gate O/P – OR Gate O/P - OR + NOT

A
A+B
A+B

B A B A B A+B O/P

0 0 1 1 0 1

0 1 1 0 1 0

1 0 0 1 1 0

1 1 0 0 1 0
NAND GATE AS A UNIVERSAL GATE
5. NAND Gate as XOR Gate

Y= AB+AB

Y= AB+AB = AB.AB A B A B AB AB Y
0 0 1 1 1 1 0

0 1 1 0 0 1 1
A
AB 1 0 0 1 1 0 1

1 1 0 0 1 1 0
B

AB
NAND GATE AS A UNIVERSAL GATE
NAND Gate as XOR Gate

Y = A B +A B +AA + B B A (AB)

Y = A (A + B) + B (A + B) AB

Y = A (AB) + B (AB)

B (AB)
Y = A (AB) + B (AB)

A B AB A (AB) B (AB) Y
Y = A (AB) . B (AB) 0 0 1 1 1 0

0 1 1 1 0 1

1 0 1 0 1 1

1 1 0 1 1 0
NAND GATE AS A UNIVERSAL GATE
6. NAND Gate as XNOR Gate
A
Y= AB+AB AB

B
Y= AB+AB

Y= AB. AB AB

A B AB A B AB Q
0 0 1 1 1 0 1

0 1 1 1 0 1 0

1 0 1 0 1 1 0

1 1 0 0 0 1 1
NOR GATE AS A UNIVERSAL GATE
Y = A+ B

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

1. NOR Gate as NOT Gate

NOR Gate O/P if A = B Y = A + A or B + B

A Y
A B Y
0 1
0 0 1
1 0
1 1 0
NOR GATE AS A UNIVERSAL GATE
2. NOR Gate as OR Gate
A B R X
Y = A + B, Y = A+B=A+B 0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1

3. NOR Gate as AND Gate

AND Gate O/P Z = AB = AB = A + B A B A B Q

0 0 1 1 0
A
0 1 1 0 0
1 0 0 1 0
1 1 0 0 1

B
NAND GATE AS A UNIVERSAL GATE
4. NOR Gate as NAND Gate

NAND Gate O/P – AND Gate O/P - AND + NOT

A
AB
AB

A B A B AB O/P

0 0 1 1 0 1

0 1 1 0 0 1

1 0 0 1 0 1

1 1 0 0 1 0
COMBINATIONAL LOGIC
❑ When logic gates are connected together to produce a specified output for certain specified combinations of
input variables, with no storage involved, the resulting circuit is a combinational circuit.

❑ In combinational logic, the output at all given times is only dependent on present the input combinations.

❑ Combinational circuits lack feedback loops, which means they don't have memory elements and don't store data.

❑ Applications: Arithmetic Operations: Addition, subtraction, multiplication, etc.

Data Encoding and Decoding: Conversion of data from one format to another.
Multiplexing and Demultiplexing: Switching between multiple inputs/outputs.
Code Conversion: Conversion between binary, Gray code, BCD, etc.
Comparators: Determining the relationship between two binary numbers.
DESIGN PROCEDURE
1. From the specifications of the circuit, determine the required number of inputs and outputs and assign a symbol
to each.
2. Derive the truth table that defines the required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a function of the input variables.
4. Draw the logic diagram and verify the correctness of the design. x
y
Design a 3-bit even parity generator.
G = ∑(0,3,5,6) z
x y z G
0 0 0 0 yz
x 00 01 11 10
0 0 1 1
0 1 1
0 1 0 1
1 1 1
0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0
x’y’z + x’yz’ + xy’z’ + xyz = x’(y’z + yz’) + x(y’z’ + yz)
1 1 1 1
= x’(y⊕z) + x(y⊕z)’ = x⊕y⊕z
4-BIT BCD TO EXCESS-3 CODE CONVERTER
BCD Code Excess-3 Code BCD Code Excess-3 Code

b3 b2 b1 b0 e3 e2 e1 e0 b3 b2 b1 b0 e3 e2 e1 e0

0 0 0 0 0 0 1 1 1 1 0 1 X X X X

0 0 0 1 0 1 0 0 1 1 1 0 X X X X

0 0 1 0 0 1 0 1 1 1 1 1 X X X X

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 X X X X

1 0 1 1 X X X X

1 1 0 0 X X X X
 4-BIT BINARY TO EXCESS-3 CODE CONVERTER
b1b0 b1b0 b1b0
b3b2 00 01 11 10 b3b2 00 01 11 10 b3b2 00 01 11 10
00 00 1 1 1 00 1 1

1 1 1 01 1 01 1 1
01
11 X X X X 11 X X X X 11 X X X X

10 1 1 X X 10 1 X X 10 1 X X

e3 e2 e1

e0
b1b0
b3b2 00 01 11 10 b0
e3 = b3 + b2b0 + b2b1 b1 e1
00 1 1
e2 = b2’b1 + b2’ b0 + b2 b1’ b0’
01 1 1 e1 = b1’ b0’ + b1b0 b2
e0 = b0’ e2
11 X X X X

10 1 X X
e3
e0 b3
3-BIT BINARY TO GRAY CODE CONVERTER
B1 B0
B2 00 01 11 10
BINARY CODE GRAY CODE
B2 B1 B0 G2 G1 G0 0
1 1 1 1 1
0 0 0 0 0 0
0 0 1 0 0 1 G2 = B2
B1 B0
0 1 0 0 1 1 B2 00 01 11 10
0 1 1 0 1 0 1 1
0
1 0 0 1 1 0 1 1 1

1 0 1 1 1 1
G1 = B2B1’ + B2’B1
1 1 0 1 0 1
B1 B0
1 1 1 1 0 0 B2 00 01 11 10
0 1 1
1 1 1

G1 = B1B0’ + B1’B0
 Binary Adder
• A combinational circuit that performs the addition of two bits is
called a half adder.
• The truth table for the half adder is listed below:

S: Sum
C: Carry

S = x’y + xy’
C = xy
56
Implementation of Half-Adder

57
 Full-Adder
• Full adder performs the addition of three bits(two
significant bits and a previous carry).

58
 Full adder implemented in SOP
S = x’y’z + x’yz’ + xy’z’ + xyz
C = xy + xz + yz

59
 Another implementation
• Full-adder can also implemented with two half adders and one OR
gate (Carry Look-Ahead adder).
S = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= xy’z’ + x’yz’ + xyz + x’y’z
C = z(xy’ + x’y) + xy = xy’z + x’yz + xy

60
 Binary adder
• This is also called Ripple
Carry Adder ,because of
the construction with full
adders are connected in
cascade.

• The signal from Ci to the

output carry Ci+1,
propagates through AND
and OR gates, so, for an n-
bit RCA, there are 2n gate
levels for the carry to
propagate from input to
output. 61
 Carry Propagation
• The most widely used technique employs the principle of carry look-ahead to
improve the speed of the algorithm.

62
 Boolean functions
Pi = Ai ⊕ Bi
Gi = AiBi
Output sum and carry
Si = Pi ⊕ Ci
Ci+1 = Gi + PiCi
Gi : carry generate Pi : carry propagate
C0 = input carry
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

• C3 does not have to wait for C2 and C1 to propagate.

63
 Carry look-ahead generator

• C3 is propagated at the same time as C2 and C1.

64
 4-bit adder with carry lookahead
• Delay time of n-bit CLAA = AND Gates = n (n + 1)/2
OR Gates = n

65
HALF SUBTRACTOR

Input Output
Difference = A’B + AB’ = A ⊕ B
A B Difference Borrow
0 0 0 0 Borrow = A’B
0 1 1 1
1 0 1 0
1 1 0 0
FULL SUBTRACTOR

Input Output
A B C Difference BorrowOUT
(BorrowIN)
Difference = A’B’C + A’BC’ + AB’C’ + ABC
0 0 0 0 0
= A’(B’C + BC’) + A(B’C’ + BC)
0 0 1 1 1 = A’(B ⊕ C) + A (B ⊕ C)’
0 1 0 1 1 =A⊕B⊕C
0 1 1 0 1
BorrowOUT = A’B’C + A’BC’ + A’BC + ABC
1 0 0 1 0
= A’C + BC + A’B
1 0 1 0 0
1 1 0 0 0 A’B’ A’B AB A’B
1 1 1 1 1 C’ 1

C 1 1 1
FULL SUBTRACTOR
4-BIT ADDER-SUBTRACTOR WITH OVERFLOW DETECTION
4-BIT ADDER-SUBTRACTOR WITH OVERFLOW DETECTION
❑ Mode input, M controls the operation.

❑ When M = 0, circuit is an adder and when M = 1, circuit is a subtractor.

❑ When M = 0, B ⊕ 0 = B, full adder receives the value of B, input carry = 0, and output = A + B

❑ When M = 1, B ⊕ 1 = B’, circuit receives the value of B’, input carry = 1, and output = A + 2s complement of B

❑ For signed numbers, V bit detects an overflow. If V = 0, no overflow occurred and the result is correct. If V =1,
overflow occurred.

❑ Overflow example - + 15 01111

+ 14 01110
+ 29 1 1101
BCD ADDER
❑ The digital systems handles the decimal number in the form of binary coded decimal numbers (BCD).

❑ A BCD Adder Circuit adds two BCD digits and produces a sum digit also in BCD.

❑ The addition of two BCD numbers can be best understood by considering the three cases:

1. Sum is less than or equal to 9 with 0 carry

3 + 6 in BCD
0 1 1 0
+ 0 0 1 1
1 0 0 1
BCD ADDER
2. Sum is greater than 9 with 0 carry
8 + 6 in BCD
1 0 0 0
+ 0 1 1 0
1 1 1 0 - Invalid BCD number, 0110 is added to rectify
1 1 1 0
+ 0 1 1 0
0001 0 1 0 0

3. Sum equals 9 or less with carry 1

8 + 9 in BCD 1 0 0 0 0001 0001
+ 1 0 0 1 0110
0 0 0 1 0 0 0 1 - Invalid BCD number, 0110 is added to rectify 0001 0111
BCD ADDER
❑ Add two BCD numbers using ordinay binary addition.

❑ If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD form.

❑ If the four-bit sum is greater than 9 or if a carry is generated from the four-bit sum, the sum is invalid.

❑ To correct the invalid sum, add 0110 to the four-bit sum. If a carry results from this addition, add it to the next
higher-order BCD digit.
BCD ADDER

C = K + Z8 Z4 + Z8 Z 2
When C = 1, 0110 is
added to the binary
sum.
BCD ADDER
BINARY MULTIPLIER
❑ Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers.

❑ Multiplicand is multiplied by each bit of the multiplier , starting from LSB.

❑ Each of these multiplications form a partial product and successive partial products are shifted one position to
the left.

❑ The final product is obtained from the sum of the partial products.

B1 B0
A1 A0
A0B1 A0B0
A1B1 A1B0
C3 C2 C1 C0
TWO-BIT BY TWO-BIT BINARY MULTIPLIER
FOUR-BIT BY THREE-BIT BINARY MULTIPLIER

For J multiplier bits and K multiplicand bits we need (J x K) - AND Gates, (J – 1) – K-bit adders to produce a
product of (J + K) bits.
MAGNITUDE COMPARATOR
❑ Magnitude comparator compares two numbers A and B and determines their relative magnitudes i.e. possible
outcomes are A > B, A = B or A < B.

❑ 1-bit magnitude comparator

1-BIT MAGNITUDE COMPARATOR
4- BIT MAGNITUDE COMPARATOR

X
4- BIT MAGNITUDE COMPARATOR