Operating System Fundamentals
Prof. Santanu Chattopadhyay
IIT Kharagpur
Assignment 1 (Week 1)
Q1.
Which of the following is inappropriate for operating system in a computer system?
(A) Manages the system’s resources
(B) Solves user computing problems
(C) Controls execution of programs
(D) Controls Input/Output devices
(E) Handels interrupts
Ans: (B) Solves user computing problems
Q2.
An Operating system executes the privileged instructions in
(A) User mode
(B) User and Kernel modes
(C) Kernel mode
(D) System Mode
(E) Restricted mode
Ans: (C) Kernel mode
Q3.
Which of the following is not a privileged instruction?
(A) Execution of system calls
(B) Interrupt handling
(C) Execution of Input/Output operations
(D) Shut down the system
(E) Execution of Library routines
Ans: (E) Execution of Library routines
Q4.
A bootstrap program
(A) Initializes the operating system
(B) Resides on the EPROM
(C) Invoked at reboot
(D) Invoked at power-up
(E) All of the above
Ans: (E) All of the above
Q5.
Which of the following instruction leads to an interrupt?
(A) Arithmetic overflow
(B) Division by zero
(C) illegal machine instruction execution
(D) Ctrl+Z
(E) All of the above
Ans: (E) All of the above
Q6.
Random Access Memory (RAM)
(A) is a non-volatile memory
(B) holds part of the user program during execution
(C) is slower than secondary storage
(D) is less costly than secondary storage
(E) is completely dedicated to user programs
Ans: (B) holds part of the user program during execution
Q7.
Which of the following is not appropriate for SSD (solid-state drive)?
(A) slower than magnetic disk
(B) volatile memory
(C) contains a hidden magnetic hard disk and a battery for backup power
(D) stores persistent data on solid-state flash memory
(E) costlier than cache memory
Ans: (B) contains a hidden magnetic hard disk and a battery for backup power
Q8.
A multicore system
(A) supports on-chip communication
(B) includes multiple computing cores
(C) is energy efficient
(D) provides increased performance
(E) All of the above
Ans: (E) All of the above
Q9.
Device controller is
(A) a hardware unit attached to the I/O bus
(B) a software unit
(C) an interface between a device and the main memory
(D) is inbuilt into the CPU
(E) interacts with the OS via ROM
Ans: (A) a hardware unit attached to the I/O bus
Q10.
Which of the following statement is true for a dual-core (L1 and L2 caches) CUP?
(A) L1 cache larger than L2 cache
(B) L2 cache is faster than L1 cache
(C) L1 cache is private to the CPU core
(D) L2 cache is private to the CPU core
(E) main memory is accessed if the requested data is not found in the L1 cache
Ans: (C) L1 cache is private to the CPU core
Q11.
Which of the following command to be issued by the process to the DMA controller if the
processor wishes to read/write a data
(A) read/write operation to be performed
(B) address of the I/O device involved
(C) starting location in the main memory to read data from or write data to
(D) number of words to be read or written
(E) All of the above
Ans: (E) All of the above
Q12.
Which of the following is not true for a multi-processor system?
(A) increased throughput
(B) increased reliability
(C) fault-tolerant
(D) each processor shares equal load
(E) costly
Ans: (D) each processor shares equal loads
Q13.
Which of the following is incorrect
(A) An interrupt is a signal to the processor
(B) interrupt decreases the system performance in a multiprogramming environment
(C) interrupt service routine (ISR) is a part of the kernel
(D) a CPU can issue an interrupt to another CPU in a multi-processor system
(E) an interrupt is handled in kernel mode
Ans: (B) interrupt decreases the system performance in a multiprogramming environment
Q14.
The kernel is the core of an operating system, and it manages
(A) random access memory
(B) secondary storage
(C) I/O devices
(D) Processor
(E) All of the above
Ans: (E) All of the above
Q15.
An interrupt vector table holds
(A) the addresses of the different interrupt handlers
(B) the list of interrupts that occurred in the system
(C) all the available interrupts
(D) the return address where the interrupt has occurred
(E) the identity of the process, which is interrupted
Ans: (A) the addresses of the different interrupt handlers
