CSE-2103
Computer Architecture
Lecture – 1, 2
Text Books
Computer Architecture and Organization
Hayes J.P., McGraw-Hill.
Computer organization and design: The
hardware/software interface
Patterson D.A., Hennessy J.L., Morgan Kaufmann.
Reference Book
Computer Architecture: A Quantitative Approach
Patterson D.A., Hennessy J.L., Morgan Kaufmann.
Fixed-Point Arithmetic
Addition
Subtraction
Multiplication
Division
Half Adder
X0 Y0 S0 C0
X0 0 0 0 0
S0 0 1 1 0
1 0 1 0
Y0 C0 1 1 1 1
S0 = X 0 ⊕ Y0
C0 = X 0Y0
Full Adder
S0 = X 0 ⊕ Y0 ⊕ C−1
C0 = X 0Y0 + X 0C−1 + Y0C−1
Full Adder
Serial Binary Adder
Least expensive
circuit in terms of
hardware cost.
It adds the numbers bit
by bit and so requires
n clock cycle to
compute the sum of
two n-bit numbers.
Circuit size
independent of n.
Ripple Carry Adder
A 1 appearing on the carry in line of a 1-bit adder cause
it to generate a 1 on its carry out line. So, the carry
signal propagate through the adder from right to left.
The maximum signal propagation delay is nd, where d is
the delay of a full-adder stage.
The amount of hardware increase linearly with n.
2’s Complement Adder-Subtracter
When s =0, then X ⊕ s = X
When s=1, then X ⊕ s = X
2’s Complement Adder-
Subtracter
Overflow
When the result of an arithmetic operation exceeds the
standard word size n, overflow occurs.
Example: let n=8, X=11101011=23510 and Y=00101010=4210
Z = X+Y = 11101011 + 0101010 = 00010101 = 2110
with Cn-1 = C7 = 1.
C7Z = 100010101 = 27710 = 25610 + 2110
The result of an addition simply wraps around when the
largest number 2n-1 is exceeds.
For n, the number range for unsigned number is 0 to 2n-1
Overflow
We can never have overflow on adding a negative and
positive number.
Example: let n=8 X=11101011=-2110 and
Y=00101010=+4210
Z = X+Y = 00010101 = 2110 and C7 = 1.
So, Cn-1 = 1 does not indicate overflow.
Overflow in 2’s complement addition can result from adding
1) two positive numbers or
2) two negative numbers.
Overflow
Case 1: Two numbers are positive.
Let n = 4, 7 + 3 = 0111+0011 = 1010 so, cn-2 = 1
Cn-2 =1 indicates that the magnitude of the sum exceeds the n-1 bits
allocated to it.
Case 2: Two numbers are negative.
Let n=4, -7 = 1001, -3 = 1101
so, 1001+1101 = 10110 so, cn-2 = 0
Cn-2 =0 indicates the overflow.
Overflow
Xn-1 Yn-1 Cn-2 Zn-1 v
Z n −1Z n −2 ......Z0 := X n −1 X n −2 ...... X 0 + Yn −1Yn −2 ......Y0 0 0 0 0 0
v = X n −1Yn −1Cn −2 + X n −1Yn −1Cn −2 0 0 1 0 1
v = Cn −1 ⊕ Cn −2 0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 0
Carry-Lookahead Adder
It reduce the time required to form carry signals.
It computes the input carry needed b y stage I directly from
carrylike signals obtained from all the preceding stages i-1,
i-2, ….., 0, rather than waiting for normal carries to ripple
slowly from stage to stage.
Adders that use this principle are called carry-lookahead
adders.
Carry-Lookahead Adder
Two signals:
generate signal, gi = xiyi
propagate signal, pi = xi + yi
ci = xiyi + xici-1 + yici-1
ci = gi + pici-1
ci-1 = gi-1 + pi-1ci-2
ci = gi + pigi-1 + pipi-1ci-2
4-bit Carry-Lookahead Adder
ci = gi + pigi-1 + pipi-1ci-2
c0 = g0 + p0cin
c1 = g1 + p1g0 + p1p0cin
c2 = g2 + p2g1 + p2p1g0 + p2p1p0cin
c3 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0cin
zi = xi ⊕ yi ⊕ ci-1 can be written as zi = pi ⊕ gi ⊕ ci-1
4-bit Carry-Lookahead Adder
4-bit Carry-Lookahead Adder
Maximum delay is 4d, where d is the average gate delay.
It is independent of number of input n.
The number of gates grows in proportion to n2 as n
increases.
The complexity of the carry generation logic in the carry
lookahead adder, including its gate count, its maximum
fan-in, and its maximum fan-out, increase steadily with n.
It limits n to 4.
Adder Expansion
If we replace n 1-bit adder stages in the n-bit ripple carry adder
with n k-bit adders, we obtain an nk-bit adder.
16-bit adder composed of 4-bit adders linked by ripple-carry propagation
Adder Expansion
If we replace n 1-bit adder stages in the n-bit carry look-ahead adder
with n k-bit adders, we obtain an nk-bit adder.
16-bit adder composed of 4-bit adders linked by carry look-ahead
Complete 2’s Complement Adder-Subtracter
Complete 2’s Complement Adder-Subtracter
Carry-Save Adder
Carry-Save Adder
One of the major speed enhancement techniques used in modern
digital circuits is the ability to add numbers with minimal carry
propagation.
The basic idea is that three numbers can be reduced to 2, in a 3:2
compressor, by doing the addition while keeping the carries and the
sum separate.
10111001
00101010
00111001
Sum: 10101010
Carry: 00111001
Result: 100011100
The sum and carry can then be recombined in a normal addition to
form the correct result.
