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Designers Perspective SI PI

This document provides an overview of a program on PCB design methodology with a focus on signal integrity and power integrity. The objectives are to understand why signal integrity is important, learn about six common signal integrity issues, the importance of PCB stack design, modeling differential signaling, high-speed signaling, and an overview of power integrity. Key topics covered include how interconnects now behave as transmission lines due to faster rise times, the goals of signal integrity including controlled impedance and low reflections, the relationship between rise time and bandwidth, and when a trace acts as a transmission line.

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smtplvikas
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0% found this document useful (0 votes)
502 views149 pages

Designers Perspective SI PI

This document provides an overview of a program on PCB design methodology with a focus on signal integrity and power integrity. The objectives are to understand why signal integrity is important, learn about six common signal integrity issues, the importance of PCB stack design, modeling differential signaling, high-speed signaling, and an overview of power integrity. Key topics covered include how interconnects now behave as transmission lines due to faster rise times, the goals of signal integrity including controlled impedance and low reflections, the relationship between rise time and bandwidth, and when a trace acts as a transmission line.

Uploaded by

smtplvikas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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IEP On PCB Design Methodology June 10,2019

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Signal Integrity & Power Integrity


A Designer’s Perspective
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Objectives of This Program


►Understand Why is Signal Integrity (SI) is important.
►An insight in to SI background.
►SIX Signal Integrity Issues.
►Importance of PCB stack design.
►A look at modeling and differential signaling.
►High-speed signaling – a cursory look.
►Overview of Power Integrity (PI).
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Signal and Power Integrity – Why?


► Driven by progress in Semiconductor Technologies.
• Smaller IC geometries results in fast rise times .
• Faster devices and higher device count, more power.
► Device rise times define interconnect behavior
► Interconnects now behave like transmission lines.
► Signals distort due based on interconnect characteristics.
► Signal Integrity focuses on interconnect behavior.
► Power Integrity focuses on power delivery in a PCB.
• Chips are switching currents at higher frequencies.
• Lower Operating voltages – lower tolerance.

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Interconnects are not Transparent

Source: SI Academy Class– Dr.Eric Bogatin

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Interconnect – Electrical Equivalent

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Interconnects with Parasitics


Interconnect in addition to its path also has packages parasitics at driver
and receiver ports.

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Digital Signal as Envisaged and as it is !

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What is Goal of Signal Integrity?

► Controlled Impedance Environment


► Low Reflections
► Minimum Crosstalk
► Low Attenuation
► Low Skew
► Reduced Jitter

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Time Domain & Frequency Domain

► Digital signals are square waves - represented as a sum of fundamental


frequencies – Fourier Theorem
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Harmonics and Bandwidth

► Amplitude of “nth” harmonic is given by: =


► More harmonics we add, we get better approximation.
► Higher harmonics would also mean faster rise time.
► Bandwidth defines range of frequencies to be addressed.

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Harmonics and Rise Time

► Importance for Digital engineers is “Rise time”


► Rise time is faster as more harmonics are added
► Faster rise time signals have higher harmonics.
Source: Signal Integrity Simplified – Dr.Eric Bogatin

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Harmonic Content & Signal Fidelity


► Points to Note:
• Spectrum of nearly square
wave signal has a simple
behavior.
• Poorly terminated signal will
develop ringing.
• Spectrum will have peaks at
the ringing frequency.
• Amplitude of a signal that has
ringing could be nearly 10
times that of a signal without
ringing.
Source: Signal Integrity Simplified – Dr.Eric Bogatin

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When a Trace acts as a Tx Line?


► Behaves as “transmission line”, if it’s length ≅
► Wave length = ∶ is in Mtrs and
► We need to consider highest frequency of the signal.
► Signal states change – LOW to HIGH and HIGH to LOW.
► This state change happens in a finite time.
► These times are called Rise / Fall times.
► Rise Time is ≈ 7% of Signal Period.
► CMOS technology has Rise time is > fall time.

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Knee Frequency or Bandwidth


► Empirical Relationship to Rise Time is given by:
.
= BW in GHz and in nSecs
► The amplitudes of harmonic frequency will fall off faster than what is in an
ideal square wave.
► Bandwidth is the frequency at which the amplitude of a higher harmonics
drops by 70% (power by 50%) from that of an ideal square wave.
► This is referred to as “Knee frequency”.

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Digital and µWave Signals Spectrum

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Signal Propagation Path

► Signal propagates from Driver to Receiver.


► Signal Velocity depends on the medium.
► Time for signal to reach receiver end depends
on:
• Propagation velocity of signal
• Length of the interconnect
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Signal Propagation Velocity


►Propagation velocity is:
.
=
►Propagation Delay is:

= .

29.87 cms/nSec is Propagation


Velocity of electrons in air
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Signal Flight Time

► Flight time is the round trip propagation time..


► For example the flight time for 15cm trace is:
• 2x0.827 nSec for outer trace.
• 2x1.063 nSec for inner trace.
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Critical Length of Trace


► Critical length is defined as the distance travelled by the signal in the time
equivalent to 50% of Rise Time.
► Signal propagation delay in FR4 is:

► Critical Length is: L = = = 9.07cms (Outer)


.

L = = 7.05cms (Inner)
.

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Impact of Signal Path on


►Bandwidth of a interconnect
depicted alongside is 8GHz.
►This bandwidth:
= . ⁄ = 0.04375nS.
►Input =100pS, then output
is degraded by 43.75pS.

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Rise time & Drive Strength

► LVTTL – 3.3V, Slow, 6mA


► LVTTL – 3.3V, Fast, 6mA
► LVTTL - 3.3V, Fast, 24mA

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Key Signal Integrity Issues


1. Signal Reflections
2. Crosstalk between nets
3. Ground Bounce
4. EMI
5. Interconnect Losses
6. PDN – Design Issues

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Noise Margin of Logic Families

HCTTL = 850 mV

HCTTL = 500 mV

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Noise Margin Definition

► Digital logic switches between two states – HIGH & LOW


► It has high-and low-voltage input thresholds- Vih and Vil
► It has high-and low-voltage output thresholds- Voh and Vol
► It is important to ensure that signal distortions generated, do not violate the
Noise Margin limits for the specific logic family used.

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Waveform Transitions & Importance

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Signal Path – Schematic/Topology

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Topology of a NET on PCB

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Signal Integrity Issues Below 1Gbps


► Higher clock speeds
► Faster signal edge rates.
• Impedance mismatch
• Reflection manifesting as:
 Overshoot / Undershoot
 Ringing
 Timing delays
 Threshold error
• Crosstalk
• EMI Issues

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Signal Integrity Issues Above 1GHz

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Signal Integrity – Terminology Maze

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Summarizing
► Interconnect behaves as a transmission line.
► Signal topology can have one or multiple paths.
► Signal propagates due to its changing states.
► Signals see instantaneous impedance during propagation.
► Signal has a return path and important as the signal path.
► Signal has a Forward and Return conductive path separated by dielectric.
► Signal path has conductor and dielectric loss.
► Both losses are frequency dependent.

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Propagation in Transmission Line

► The electrical signal travels interconnect line in a finite time.


► The voltage Vi is the initial voltage applied to this line at node A.
► Vs and Zs are Thevenin's equivalent representation of the source.
► When the signal reaches any point “X” along the transmission line, the signal path
conductor will be at a potential of Vi volts and ground return conductor at 0 volts.
Source: AHandbook of Interconnect Theory and Design Practices – By Stephen H Hall et al (2000)

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Propagation Along Transmission Line

Conductive
Path

Return
Path

► Distributed capacitance exists between the conductors.


► Current flows only when voltage changes across Capacitor.
► Voltage change happens during rise and fall time.
► “Displacement current” flows through the capacitors.
► Signal wave front progresses in forward direction.
Animation : Mr. Yoshi Tsuji, Teledyne Lecroy, Japan

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TEM Mode in Transmission Line

► The electric and magnetic fields will be orthogonal.


► Known as transverse electro-magnetic mode (TEM).
► Transmission lines will propagate in TEM mode.
► Good approximation up to relatively high frequencies.
Source: AHandbook of Interconnect Theory and Design Practices – By Stephen H Hall et al (2000)

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Reflection Coefficient

► Signal sees an instantaneous impedance along its path.


• When signal sees an impedance change, portion of signal is reflected, balance is transmitted.
• In a controlled Impedance design, there is no reflection.
• Reflected signal depends on the magnitude of the impedance change.
► This magnitude is given by Reflection coefficient:
=

Source: Signal Integrity AND Power Integrity Simplified – Dr.Eric Bogatin

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Reflection Coefficient - Derivation


= = =

- =

- =

- =

- = +

= = =
Source: Signal Integrity AND Power Integrity Simplified – Dr.Eric Bogatin

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Reflection Coefficients – Load, Source


► We can derive reflection coefficients as under:

► At the Load end: =

► At the Source End: =

► At the load end, we can have ZO as impedance.


► At the load end, we can have an OPEN or SHORT
► Reflection coefficients is: 0, +1 (open) and -1 (short).

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Transmission Line – Special Cases

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Single Net – Impact of Reflection

Voltage
Rist Time in nSecs

Signal
Time
Rise Time Tr
90%
Voltage

Propagation delay/2
Signal Transition Time

Voltage
10%

Time in nSecs

Signal Parameters Time


Rise Time Tr

Propagation delay/2

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Impedance Changes – PCB Level


► Zo changes at discontinuity
► Common discontinuities are:
• A line-width change
• A layer change
• A gap in return-path plane
• A connector
• A branch, tee, or stub
• The end of a net
► Common discontinuity is at the end of a
trace.
• Usually either a high-impedance open or a
low impedance at the output driver.

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Signal Current Return Paths

► Return current changes reference planes, inter-plane capacitance is not enough to be


effective.
► Hence flows through nearest decoupling capacitor.
► This obviously increases the loop area. May aid EMI aspect.
► Add a decoupling capacitor adjacent to the signal via to aid current flow. Adds 5-10nH
inductance

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Return Path – Layer Transitions

► If both planes are at same potential, GND or PWR, then:


• Return path for SIGNAL 1 and SIGNAL 2 is Ground Plane.
► If planes are at different potential - GND and PWR, then:
• Return path for SIGNAL 1 is Ground Plane.
• Return path for SIGNAL 2 is Power Plane.
• Return path from Ground Plane to Power plane is through inter-plane capacitance.
Source: Signal Integrity AND Power Integrity Simplified – Dr.Eric Bogatin

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When Termination is Required?


► In a digital system: < <
• =Driver Source Impedance,
• =Interconnect Impedance,
• = Receiver Input impedance
► Reflections results in ringing and stair-stepping.
• False triggering in clock lines, Erroneous bits on data, address, and control lines;
Increased Jitter and enhanced EM radiations.
► As rule of thumb, no termination required if transmission Line length
propagation time is < 0.2xTr

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Termination Schema - Common


Series Thevinin Termination
Termination

Parallel AC Termination
Termination

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Multi layer PCB Build


► PCB core material is a thin dielectric with
copper clad foils bonded to both sides.
► Core’s dielectric is a cured fiberglass weave
material with epoxy resin as insulator.
► Prepreg is an uncured fiberglass-epoxy
resin weave that acts as the insulation
between core layers and is the gluing agent
for cores.
► Multilayer PCB are built with multiple core
and prepreg layers, combined with a top
and bottom copper foil and hot -pressed
together to build the PCB.

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PCB Material
►Resin and Reinforcement make up base material.
►Copper foil bonded to base material is laminate.
►Copper clad laminates thus has three parts:
• Resin - natural or synthetic resinous material
• Reinforcement –provides mechanical stability to the
laminate. This can be paper, matte glass, woven glass.
• Copper foil – The conductive element

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Building a Multilayer PCB Stack?


► Standard thickness of rigid base material are:
• 0.75mm (0.030”), 1.50mm (0.060”), 2.40mm (0.090”)
• 0.05mm (0.002”) – Minimum thickness
► Multilayer PCB, is built using laminates and prepreg material.
► Different thickness of laminates and prepregs are available.
► Combinations of laminates and prepregs is used to build.
► Choosing the right combination of laminate and prepreg thickness to
build a multilayer PCB is governed by manufacturer guidelines.
Impedance requirements, end user cost drivers.

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Standard Laminate / Prepreg Thickness


Laminate Thickness Prepreg Thickness
1x106 50μ (2 mil) 106 50μ (2 mil)
1x1080 75μ (3 mil) 1060 63μ (2.7 mil)
1x2116 100μ (4 mil) 1080 75μ (3 mil)
1x1501 150μ (6 mil) 2116 100μ (4 mil)
1x7628 200μ (8 mil) 2125 105μ (4 mil)
2x1504 250μ (10 mil) 1501 150μ (6 mil)
2x1501 300μ (12 mil) 7628 200μ (8 mil)
2x7628 360μ (15 mil)
3x7628 510μ (20 mil)
4x7628 760μ (30 mil)

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Copper Foils Used in PCB Laminates


► Copper used in rigid PCB’s is Electrodeposited.
► Copper used in flex PCB’s is rolled copper.

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How Do You Choose a Material?


► IPC 4101C has nearly 55 different material details
► What are the steps to select the right material?
• Determine the final application of the product
• Understand the operating conditions
• What is the cost impact?
• Ensure availability with your manufacturer
• Ensure that it is RoHS Compliant - Tg
• For Gbps Designs look at Dielectric Loss - Tanδ

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ISOLA Material Map

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Generic Material Selection Flow

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Comparison of Some ISOLA Materials

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8 Layer PCB Build – 1.6± 10% mm Thick

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Crosstalk
► Crosstalk is defined as the “noise” introduced in a quiet net by an
active net.
► Crosstalk happens between the signal and return paths of the
“active net” and the signal and return paths of the “quiet net”.
► Normally crosstalk margins acceptable as a rule of thumb is 5%
of the signal voltage swing.
► “Active net” is termed “Aggressor” and the “Quiet net” as
“Victim”.
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Crosstalk – Coupled Noise

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Phenomena of Crosstalk

► Signal propagation is TEM.


► Fringe fields, couples to neighboring signal lines.
► Cross talk Amplitude depends on position of “Victim” trace from the “Aggressor” trace.
► Increased separation between signals reduces crosstalk, while decreasing increases
cross talk.

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Inductively Coupled Crosstalk

► Signal in active line induces a voltage in the quiet line.


► Induced voltage is dependent on of active line signal.
► Induced voltage sees same impedance on forward and backward directions.
► The induced voltage is distributed equally.

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Crosstalk Induced Noise

Coupled Currents

► The near and far end victim line currents sum to produce the near and the
far end crosstalk noise
I near  I Cm  I Lm I far  I Cm  I Lm

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Near-end and Far-end Crosstalk

Injected Signal = 200mV with 50pS rise time

► Near-end noise (NEXT) rises up to a constant value and is valid for a time equal to 2.Td of the
coupling length.
► Far-end noise (FEXT) until one time of flight after the signal starts it has a time period equal to
rise time of signal.
► Ratio of coupled noise voltage to signal voltage is called NEXT and FEXT coefficient.
Source: Signal Integrity AND Power Integrity Simplified – Dr.Eric Bogatin

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Crosstalk – Induced Noise

Voltage Profile of Coupled Noise

► Near End Crosstalk is always positive.


• Current from Lm and Cm always add and flow into the node.
► For PCB’s Far End Crosstalk is usually negative.
• Current due to Lm is > current due to Cm
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NEXT /FEXT – Influencing Parameters

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Controlling Crosstalk
► Near-end
• Increase the spacing between Traces.
• Use strip line construction.
• Use guard traces to reduce cross talk.
► Far-end
• Increase the spacing.
• Use strip line construction.
• Decrease the coupled length.
• Increase dielectric thickness above the trace, this increase near-end
noise and decrease Z0.

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What is Ground Bounce


► This is a transient voltage
generated between two
different points on same
ground path.
► Appears on all signals using
same Ground.
► This is categorized as a form
of “crosstalk”
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Ground Bounce - Basics

►When Q2 turns “On” and Q1 turns “Off”, then it provides the path for the current
from output to ground. This is when the signal switches from “High” to “Low” .
►A current spike now flows from output through Q2 flows to ground. This current is
dependent on the number of loads connected at the out put.
►This current then flows through the lead inductance resulting in the voltage at “Ref
B” being elevated from the GND level.

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Ground Bounce - Basics

►When Q2 turns “Off” and Q1 turns “On”, then it provides the path for the current from
Vcc to output. This cuts off the current flowing through Q2 to ground.
►The negative current spike generates a voltage at “Ref B”, which propagates to the
output. This will be in addition to the voltage drop due to the lead inductance at “Ref
A”.
►These changes in the voltage level is called “Ground Bounce or SSN or SSO Noise”
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Impact of Ground Bounce


► Inductor is between external system
ground and internal device ground
► Induced voltage rises internal ground
level.
► This voltage rise can result in device
inputs and outputs to behave
differently .
► This is due to reference difference
between internal device ground, and
external system ground.

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Minimizing Ground Bounce


► Avoid many signals sharing the same GND pin.
• E.g.. Connectors – use more GND return pins.
► Examine if slower rise devices can be used.
► Reduce the inductance in the return path.
• Use wider signal return paths.
• Route multiple signal paths near return path.
 Induces opposing magnetic fields to GND loops.
► Avoid “via’s” puncturing planes near routed bus signals.
► Use of low ESL decoupling capacitors for such IC’s.

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Definition of EMI & EMC


► Electromagnetic Interference (EMI)
• Electromagnetic emissions from a device or system that interfere with the
normal operation of another device or system.
• Also referred as Radio Frequency Interference (RFI).
► Electromagnetic Compatibility (EMC)
• The ability of equipment or system to function satisfactorily in its
Electromagnetic Environment (EME) without introducing intolerable
electromagnetic disturbance to anything in that environment.

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EMC – Basic Requirements

► For an EMC problem to exist:


• System/Device that generates interference.
• System/Device that is susceptible to the interference.
• Coupling path.

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Schematic of EMC Paradigm

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EMC Standards - FCC


► Federal Communication Commission – FCC

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FCC and CISPR Limits

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Far and Near fields


► In far fields all become plane waves.
► Far field is when distance from point source d >

Impedance of plane
Characteristic Impedance of Air

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Signals paths and EMI


► All electrical signal are electromagnetic
waves
► Conductors are wave guides
► The “return” path is commonly ignored.
► Collectively, they act as antenna – loop
► EMI generated at a specific frequency
also makes unit susceptible at same
frequency

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Typical EMI Scenario

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EMI Coupling Mechanisms


► Radiated:
• The source radiates a signal which may be wanted or unwanted, and the victim
receives it in a way that disrupts its performance.
► Conducted :
• Conducted emissions through conduction path along which the signals can travel.
• This could be power cables or other interconnection cabling.
► The filtering techniques required will vary according to the type of EMI
coupling experienced.

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PCB Layout and EMC


► Layout is 3 Dimensional
• Component placement (X & Y)
• Signal and Power Routing (X & Y)
• PWB Stack Up (Z)
► Dedicate layer(s) to ground
• Forms reference planes for signals
• EMI Control (high speed, fast slew rate, critical analog/RF)
• Simpler impedance control
► Dedicate layer(s) to Supply Voltages
• In addition to dedicated ground layers
• Low ESL/ESR power distribution

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Solid Ground Planes and EMI

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Split Ground Planes and EMI

If the ground plane is not continuous underneath the signal trace,


crosstalk, reflections and EMI increase because of the impedance
mismatch and larger current return loop area.

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Differential Signaling and EMI

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EMI Reduction – 20h Rule


► RF Currents fringing between the Power and the Ground planes at the
board edge result in RF emissions.
► Reducing the size of the Power plane with respect to the Ground plane will
reduce the emissions.
► Increases intrinsic self resonant frequency of the PCB.
► Ground Plane should extend the Power plane by 20h
• “h” is the distance between the Power and Ground planes.
► 20h rule reduces the fringing fields by 70%
► 100h rule reduces the fringing fields by 98%

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Some Examples of EMI in PCB

Minimizing EMI Caused by Radially Propagating Waves inside High Speed Digital Logic PCBs – By Franz Gisin et al - Mikrotalasna revija (2001)

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Some Examples of EMI in PCB

Minimizing EMI Caused by Radially Propagating Waves inside High Speed Digital Logic PCBs – By Franz Gisin et al - Mikrotalasna revija (2001)

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Some Examples of EMI in PCB

Minimizing EMI Caused by Radially Propagating Waves inside High Speed Digital Logic PCBs – By Franz Gisin et al - Mikrotalasna revija (2001)

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General Signaling Principles


► Signals propagate due to changing voltage levels.
► Every signal shall have return path – mandatory.
► Every signal behaves based on instantaneous impedance that it
sees.
► Change in electric field is responsible for current in the return
path – displacement current .
► Current in Tx line has two directions – direction of propagation
and direction of circulation.
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Single ended Signaling

► Here driver & receiver share same GND reference.


► Crosstalk noise can impact signal quality.
► Power/ground bounce can impact signal quality:
— Package pin inductance for power/ground
— Connector pin inductance for power/ground
— Gaps in power/ground planes

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Differential Signaling

► Differential signal is a set of paired signals with opposite polarity.


► Some current will still go through the common GND due to mismatches in
the differential signals. This is referred to as common mode current.

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Differential Pair / Differential Signaling


► Differential pair is pair of coupled transmission lines.
► Differential signaling :
• Uses two output drivers.
• Drives complementary bits.
• Drives coupled transmission lines – differential pair.
► Key drivers of differential signaling:
• Tightly coupled lines, reduces crosstalk.
• Reduced EMI due to noise cancellation if balanced.
• Drives impedance controlled differential pairs.

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Differential Pair – How it is configured?


► Two transmission lines make up a differential pair.
► Key features which optimizes performance are:
• Uniform cross section to ensure constant impedance
• Maintain symmetry – line width, dielectric spacing and geometry – no
imperfections
• Matched time delay between the two lines
• Maintain same length to minimize skew
• Coupling between the pair – not mandatory, but tight coupling ensures good
noise and SSN immunity

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Differential Signaling

Source: Signal Integrity AND Power Integrity Simplified – Dr.Eric Bogatin

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Tight Coupling & Loose Coupling

Generated using Si9000 – Polar Instruments

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Differential Signaling
►Key advantages:
• Higher noise margin at receiver. Higher data rate
• Can be operated at lower voltage and less power
• Less SSN noise impact at Transmitter end
• Less sensitivity to return path discontinuities
• Hence more adaptive to Gbps signaling
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Length matching in Differential Signals


► Equal return current on both signal

paths is important, say +i1, and –i2


► If i1 and i2 are similar, but i1 ≠ i2 in magnitude,
then return currents is (i1 –i2) 0, and this
returns through ground
► When path lengths are different, then the
signals are no longer equal and opposite
during their transition phase at the receiver

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IBIS – What it is?


► IBIS stands for
• Input / Output Buffer Information Specification
► Behavioural model for Signal Integrity issues
► EIA’s IBIS Open Forum has ownership of the IBIS
► IBIS has the advantages over SPICE of file size
► Does not reveal any intellectual property
► IBIS format is ASCII text
► Supports multiple simulator platforms

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IBIS Model - History


► Ver. 1.0 Released in April 1993
► Ver 2.1 Released in December 1995 – ANSI/EIA 656
• Basic SPICE IO behavior as tabular form.
► Ver 3.2 Released in September 1999
► Ver 4.2 Released in June 2006
• Enables encrypted SPICE, VHDL-AMS, Verilog-AMS
► Ver 5. 0 Released in August 2008
• Algorithmic Model (AMI) support added.
► Ver 6.1 Released in September 2015
• Modified AMI modeling support to include Jitter analysis, power pin modeling,
PAM4 support (>28Gbps data rates)

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Evolution of IBIS – Key Words


► Version 2.1
• [Define Package Model] (.ibs, .pkg)
• [End Package Model] (.ibs, .pkg), [End] (.pkg)
► Version 3.1
• [Model Selector], [Submodel]
• [Begin Board Description] (.ebd)
• [End Board Description] (.ebd), [End] (.ebd)
► Version 4.2
• [External Circuit], [End External Circuit]
► Version 5.1
• [Test Load] defined under [Model], [Test Data] defined under [Model]

Evolution of IBIS Model 6.1, Bob Ross

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Evolution of IBIS – Pin Out & Package


► Version 2.1
• [Pin Mapping], [Diff Pin]
► Version 3.1
• [Series Pin Mapping]
► Version 4.2
• [Alternate Package Models], [End Alternate Package Models]
• [Node Declaration], [End Node Declaration]
• [Circuit Call]. [End Circuit Call]
► Version 5.1
• [Begin EMI Component], [End EMI Component]
► Version 6.1
• [Repeater pin]

Evolution of IBIS Model 6.1, Bob Ross

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IBIS Modeling - AMI


► This is available from IBIS Ver 5.0 released in
• AMI stands for Algorithmic Model Interface
• IBIS-AMI is a standard for defining algorithm code to model the nonlinear
behaviour of the transmitter and receiver of multi-gigabit SERDES channels.
• AMI models define device parameters such as pre-emphasis and equalization
that standard IBIS buffer models cannot

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IBIS Modeling - AMI


► What does IBIS-AMI models has?
• Analog models for the transmitter and receiver
 Analog models helps to characterize the channel and generate an impulse response which
is a fundamental input for the algorithmic models.
• A parameter file (.ami) for the algorithmic models
 Parameter file is needed to vary the settings of the algorithmic model
• Compiled Algorithmic models (the DLL library for Windows, or SO library for
Linux/Unix)
 This is not complete model and only part of it

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S - Parameters
► S-Parameters used as the behavioural model of a network, translated into
terms of reflection and loss.
► For passive interconnect structures, like transmission lines and via's, as
the frequency increases dependency on loss.
► Standard methods of analysing and modelling these types of structures no
longer hold true when considering a wide range of frequency dependent
phenomena.

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S-Parameter - Representation
► Focus here will be on a simple 2-port network:
► Linear equations can be used to describe the network in terms of injected
and transmitted power waves.

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S-Parameter - Representation

S11= S21=

S22= S12=

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Signaling Technology Beyond 1GHz

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Two Distinct Architectures


► Parallel Data Transfer ► Serial Data transfer

I/O I/O

CORE
CORE

CORE
CORE
+ +
tx rx
- -

C1 C2
C1 C2

Synchronously clocked Asynchronously clocked


(primarily single-ended) (primarily differential-pair)

~ 10 MHz 0.5 GHz Multi-GHz

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Multi-Gigabit Design Challenges


I/O I/O

Architecture

CORE
CORE

CORE
CORE
+ +
tx rx
- -

C1 C2 C1 C2

Delay, Timing Requirements Jitter, Loss


Crosstalk Eye masks/% eye opening
Overshoot Bit Error Rate
C1 tPD
C2 tSU Analysis
U3 out

U7 in
tint

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Serial Data Transfer


► Embedded Clock Solution
• No Separate Clock
• Eliminates Clock Skew
• Greater Distance, Speed
• Receiver Recovers Clock From Data Transitions
• Clock & Data Recovery (CDR) Function
• Typically PLL-Based
• Encoding and/or Packet Formatting
• Can “Bond” Multiple Links For Greater Speed

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Serial Data Transfer Technologies


Technology Data Rate Comments
Serial ATA 1.0 1.25 Gbps CPU Bus interface to HDD
Hypertransport 1.6 Gbps Interconnection of host processors
AGP8x 2.1 Gbps For attaching video card to motherboard
PCI Express I 2.5 Gbps Serial computer expansion bus standard
Serial ATA 2.0 2.5 Gbps CPU Bus interface to HDD
XAUI 3.125 Gbaud 10 Gigabit Media Independent Interface) between
MAC and PHY layer of 10GbE
PCI Express II 5.0 Gbps Serial computer expansion bus standard
Serial ATA 3.0 6.0 Gbps Serial computer expansion bus standard
PCI Express III 8.0 Gbps Serial computer expansion bus standard
OC - 192 9.953 Gbps Optical Carrier signals over SONET
10 GbE 10.0 Gbps 10 Gigabit Ethernet
OC-768 39.81 Gbps Optical Carrier signals over SONET

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EYE Generation in Serial Data Trasfer

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What an EYE diagram Means?

deterministic jitter

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Key Properties of a Transmission Line


► The key properties that determines how well a transmission structure
functions, regardless of the physical appearance or configuration of its
conductors are:
• Characteristic impedance,
• Propagation Delay
• Crosstalk
• High-frequency loss,

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PCB Loss – Trace = 6mil, Tanδ= 0.02

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PCB Loss – Trace = 6mil, Tanδ= 0.003

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Why think of Power Integrity?


► Ensure that low-noise DC voltage and power is supplied to the active
devices on the PCB.
► Power Delivery Networks – Generally planes in multi-layer PCB’s act as
low-noise return path for the signals. Optimising this is the goal of PDN.
► Minimize the signal return path discontinuities to mitigate
electromagnetic interference (EMI).

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Power Delivery Network - Background


► Power Deliver during the 80’s used to be single pin for Power and Ground
– Eg. 74xx series
• Decap Put a cap across the IC to provide local current
► Then we had devices with two voltages 3.3V and 5V
• Each one gets its own plane
► Current day embedded system designs have:
• BGA Devices with hundreds of ground and power pins
• Multiple technologies – minimum 5 voltage rails
 Planes chopped up into separate islands
• Operating frequencies are higher than earlier

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What is Power Delivery Network (PDN)?

► PDN is the path from Power Input Point (Connector or VRM) all the way to the power pins of
Active devices (IC’s)
► PDN Includes PCBs and packages, Planes, Routed traces, and Decoupling capacitors
► PDN shall ensure that the voltage levels at the power points of all active devices is above the
minimum value.
► PDN also provides low-noise reference path for signals

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Why this interest in PDN Analysis?

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Power Delivery Points for an IC


Main Power Board Voltage Decoupling
t- Planes
Supply to the Regulator Capacitors Near
in the PCB
System Module to Devices

► Main power is farthest from a device.


• Path inductance impacting at higher frequencies.
► Decoupling Capacitors:
• Bulk Capacitors.
• High-frequency decoupling capacitors.
• Buried (inter-plane) capacitance of t-planes.

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Ideal Power Delivery Network

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PDN – DC Failure

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PDN Failure - Low DC Rail + AC Noise

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PDN Failure - Clean DC Rail + AC Noise

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Power Delivery Network – Eq. Cct.

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Power Delivery Network – Eq. Cct.

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Power Delivery Network – Eq. Cct.

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Power Delivery Network – Eq. Cct.

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Real PWB Scenario

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Objective of Power Integrity


► DC Analysis
• Review the plane geometry to examine the voltage drop and excess current
density area’s.
• Evaluate the current capacity of Via’s in power net.
► AC Analysis
• Study frequency dependant impedance behaviour.
• Study decoupling capacitor placement, mounting, quantity, type on
performance.
• Study noise propagation from power pins and via’s.

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DC Analysis – What does it Review?

► Impact of Anti-pads in increasing Inductance.


► Identify Current flow constraints and address.
► Define Solutions to address this:
• Minimise anti-pad webs.
• Use of Blind/HDI Via for Ground layer to minimise Power Plane inductance.
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PDN Impedance - Goal


%Ripple
VRail ×
ZTarget = 100
IMax Transient

Ref: Mentorgraphics U2U 2010

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PDN Targets - Frequency Domain

Ref: Ansoft – Fundamentals of SI,PI and EMI

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Addressing PDN Design


► TWO key contributors in the PDN
• Package parasitics.
• PCB Build and Decoupling Strategy.
► Key Design Parameters to Address
• PCB Stack Design.
• PCB Material Selection.
• Decoupling Capacitor choice and quantity.
• Proper review of PDN and Design.

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Objectives of Power Integrity Analysis


► Minimize DC Drop and AC Noise
► Maximize power delivery at all frequencies
► Challenges to address:
• FPGA, ASIC, Microprocessor, DSP etc., operate at lower voltage and higher
current
• Power issues cause signal integrity problems
• Choice of Capacitors and their placement
• Plane geometries and their disposition in PCB build

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Design Example - Voltage Levels

MentorGraphics Design Kit Example

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Design Example – Current Density

MentorGraphics Design Kit Example

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Design Example – Numeric Results

MentorGraphics Design Kit Example

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Design Example – Location Map

MentorGraphics Design Kit Example

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Design Example - 1.5V Plane

MentorGraphics Design Kit Example

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References
1. Signal Integrity & Power Integrity Simplified - 2nd Edition Dr.Eric Bogatin
2. Noise Reduction Techniques in Electronic Systems Dr.Henry Ott
3. High-Speed Digital Design – Advanced Black Magic Dr. Johnson H.W et al.
4. Digital Techniques for High speed design Dr. Tom Granberg
5. Printed Circuit Board Design Techniques for EMC compliance Mark Montrose
6. Signal Integrity & Radiated Emission of High Speed Digital Systems Spartaco Caniggia et al
7. A Handbook of Interconnect Theory & Design Practices Stephen Hall et al
8. Advanced Signal Integrity For High-speed Digital Designs Stephen Hall, et al
9. PCB Design for Real-World EMI Control Bruce R Archambeault
10.Electromagnetic Compatibility Engineering Dr.Henry W Ott
11.Base Materials for High Speed, High Frequency PC Boards Lee Ritchey 2002

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