DESIGN AND IMPLEMENTATION OF HALF ADDER AND
FULL ADDER
AIM:
To construct and test the performance of half adder and full adder using
digital IC’s.
APPARATUS REQUIRED:
S.NO DESCRIPTION RANGE QUANTITY
1. IC Trainer Board Digital 1
2. AND Gate IC7408 1
3. EX-OR Gate IC7486 1
4. OR Gate IC7432 1
5. Patch Cords - As required
THEORY:
HALF ADDER:
Half adder is a combinational circuit which consists of two binary input
variables called augend and addend and two binary output variables called
sum and carry. In the addition result, the lower significant bit is called as sum
and the higher significant bit is called as carry. The truth table of the half
adder is given below, in that the sum becomes logic ‘1’ when any one of the
input is maximum and it is equal to logic ‘0’ when both inputs are equal. The
carry is equal to logic ‘1’ when both inputs are equal to logic ‘1’unlessit is
equal tologic‘0’.
FULL ADDER:
Full adder is a combinational circuit which consists of three binary input
variables called augends and addends and two binary output variables called
HALF ADDER:
LOGIC DIAGRAM: TRUTH TABLE:
FULL ADDER:
LOGIC DIAGRAM: TRUTH TABLE
sum and carry out. In the addition result, the lower significant bit is called as
sum and the higher significant bit is called as carry out. The truth table of the
full adder describes all the eight possible input variations. The full adder
results the outputs are equal to logic ‘0’ when all the applied inputs are equal
to logic ‘0’ and the outputs are equal to logic ‘1’ when all the inputs are equal
to logic ‘1’. The sum is equal to 1 when odd numbers of inputs are equal to 1
from the applied three inputs. The carry out is equal to 1 if more than one
applied inputs are equal to 1.
PROCEDURE:
1. Make the connections as per the logic diagram.
2. Switch ON the IC trainer board.
3. Apply the input combinations as per the truth table.
4. Note its corresponding output level.
5. Repeat the above procedure for half adder and full adder.
6. Switch OFF the IC trainer kit.
7. Disconnect the components.
RESULT:
The half adder and full adder circuits are constructed by using Ics and
their performance is also tested.
DESIGN AND IMPLEMENTATION OF HALF
SUBTRACTOR AND FULL SUBTRACTOR
AIM:
To construct and test the performance of half subtractor and full
subtractor using digital IC’s.
APPARATUS REQUIRED:
S.NO DESCRIPTION RANGE QUANTITY
1. IC Trainer Board Digital 1
2. AND Gate IC7408 1
3. EX-OR Gate IC7486 1
4. OR Gate IC7432 1
5. NOT Gate IC 7404 1
6. Patch Cords - As required
THEORY:
HALF SUBTRACTOR:
Half subtractor is a combinational circuit which consists of two binary
input variables called minuend and subtrahend, and two binary output
variables called difference and borrow. In the two bit subtraction result, the
lower significant bit is called as difference and higher significant bit is called
as borrow. The truth table of the subtractor is given below in that the
difference becomes logic ‘1’ when both inputs are different each other and it
is equal to logic ‘0’ when both inputs are equal. And borrow is equal to logic
‘1’ when minuend is smaller than subtrahend.
FULL SUBTRACTOR:
Full subtractor is a combinational circuit which consists of three binary
input variables called minuend and subtrahend, and two binary output
HALF SUBTRACTOR:
LOGIC DIAGRAM: TRUTH TABLE:
FULL SUBTRACTOR:
LOGIC DIAGRAM: TRUTH TABLE
variables called difference and borrow out. In the subtraction result, the lower
significant bit is called as difference and the higher significant bit is called as
barrow out. The truth table of the full subtractor describes all the eight
possible input variations. The full subtractor results the outputs are equal to
logic ‘0’ when all the applied inputs are equal to logic ‘0’
PROCEDURE:
1. Make the connections as per the logic diagram.
2. Switch ON the IC trainer board.
3. Apply the input combinations as per the truth table.
4. Note its corresponding output level.
5. Repeat the above procedure for half subtractor and full subtractor.
6. Switch OFF the IC trainer kit.
7. Disconnect the components.
RESULT:
The half subtractor and full subtractor circuits are constructed by using
ICs and their performance is also tested.
DESIGN AND IMPLEMENTATION OF CODE
CONVERTER
AIM:
To design andimplement4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
APPARATUS REQUIRED:
S.NO DESCRIPTION RANGE QUANTITY
1. IC Trainer Board Digital 1
2. EX-OR Gate IC7486 1
3. Patch Cords - As required
THEORY:
BINARY CODES: A group of binary bits that used to represent the
characters, numbers and symbols is defined as binary codes. Binary codes are
used in the digital computer to represent, store and transmit various data.
BCD NUMBERS: BCD numbers are straight binary representation for
decimal numbers. The decimal numbers ate directly represented with the
weight ages of 8421 in BCD code. This is popularly used in decimal addition,
subtraction, etc. the BCD code represents the decimal number 0 to 9 with the
binary representation 0000 to 1001. In the 4-bit binary representation last six
assignments are discarded for BCD number representation.
EXCESS – 3 CODE: The 4-bit excess – 3 code is obtained by adding
3(0011) with BCD code. 8421 and 2421 weighted codes provide the self-
complement number of excess – 3 code in the binary representation. The self-
complement property of excess – 3 code helps to perform the arithmetic
operation in digital system design
CODE CONVERTER:
BINARY TO GRAY CODE:
LOGIC DIAGRAM:
TRUTH TABLE
Inputs(BINARYCODE) Outputs(GRAYCODE)
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
GRAY TO BINARY CODE:
LOGIC DIAGRAM:
TRUTH TABLE:
Inputs(GRAYCODE) Outputs(BINARYCODE)
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
GRAY CODE: This code is an un-weighted binary code. A gray code is
often used in the translation of an analog quantity, such as a shaft position in
to digital form. The four bit gray code can be used to represent the decimal
number from 0 to 15. In this representation the last and first entry of gray
code consequently differs only in one bit position (MSB bit). So this is also
called reflective code.
CODE CONVERTERS: The presence of different codes in digital
system for the same discrete elements of binary information results the
requirement of code conversion. Code converter is a logic circuit that converts
one type of binary code into another type of binary code.
PROCEDURE:
1. Make the connections as per the logic diagram.
2. Switch ON the IC trainer board.
3. Apply the input combinations as per the truth table.
4. Note its corresponding output level.
5. Repeat the above procedure.
6. Switch OFF the IC trainer kit.
7. Disconnect the components.
RESULT:
The Binary to Gray Code and Gray to Binary Code converter circuit has
been constructed and also implemented by using logic gates.
DESIGN AND IMPLEMENTATION OF MULTIPLEXER
AND DEMULTIPLEXER
AIM:
To construct and test the performance of multiplexer and demultiplexer
using digital IC’s.
APPARATUS REQUIRED:
S.NO DESCRIPTION RANGE QUANTITY
1. IC Trainer Board Digital 1
2. 3 I/P AND GATE IC 7411 2
3. OR Gate IC7432 1
4. NOT Gate IC 7404 1
5. Patch Cords - As required
THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units
over a smaller number of channels or lines. A digital multiplexer is a
combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of a particular input
line is controlled by a set of selection lines. Normally there are 2n input line
and n selection lines whose bit combination determine which input is
selected.
DEMULTIPLEXER:
A Demultiplexer is a circuit that receives information on a single line
and transmits this information on one of 2n possible output lines. The
selection of specific output line is controlled by the values of n selection lines.
The single input variable Din has a path to all four outputs, but the input
information is directed to only one of the output lines.
4:1 MULTIPLEXER:
BLOCK DIAGRAM:
LOGIC DIAGRAM:
TRUTH TABLE
Selection Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
1:4 DEMULTIPLEXER:
BLOCK DIAGRAM:
LOGIC DIAGRAM:
TRUTH TABLE
Selection
Outputs
Inputs
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
PROCEDURE:
1. Make the connections as per the logic diagram.
2. Switch ON the IC trainer board.
3. Apply the input combinations as per the truth table.
4. Note its corresponding output level.
5. Repeat the above procedure.
6. Switch OFF the IC trainer kit.
7. Disconnect the components.
RESULT:
Thus the 4:1 multiplexer and 1:4 demultiplexer circuit has been designed
and implemented using logic gates.
DESIGN AND IMPLEMENTATION OF ENCODER AND
DECODER
AIM:
To construct and test the performance of encoder and decoder using
digital IC’s.
APPARATUS REQUIRED:
S.NO DESCRIPTION RANGE QUANTITY
1. IC Trainer Board Digital 1
2. 3 I/P AND GATE IC 7411 2
3. OR Gate IC7432 1
4. NOT Gate IC 7404 1
5. Patch Cords - As required
THEORY:
ENCODER:
An encoder is a digital circuit that performs inverse operation of a
decoder. An encoder has 2n input lines and n output lines. In encoder the
output lines generates the binary code corresponding to the input value. In
octal to binary encoder it has eight inputs, one for each octal digit and three
output that generate the corresponding binary code. In encoder it is assumed
that only one input has a value of one at any given time otherwise the circuit
is meaningless. It has an ambiguity that when all inputs are zero the outputs
are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
Decoder is a multiple input multiple output combinational digital
circuit that converts n number of coded binary inputs in to 2n number of
coded binary
4 TO 2 ENCODER:
BLOCK DIAGRAM:
LOGIC DIAGRAM:
TRUTH TABLE
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
2 TO 4 DECODER:
BLOCK DIAGRAM:
LOGIC DIAGRAM:
TRUTH TABLE
Enable Inputs Outputs
E A1 A0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
outputs. In the decoder, the combination of input information lines define the
logic output of any one output line as logic high at a time and rest of the
output lines are being fixed to logic 0. When the combination of input binary
information changes the logic 1 output line also be changes. Usually decoder
produces unique output corresponding to each input pattern. Therefore, the n
to 2n decoder is also called as simple minterm generator with each output
corresponding to exactly one minterm. The enable input used in the diagram
acts as a controller of decoder. To operate the decoder the enable input must
set as active high.
PROCEDURE:
1. Make the connections as per the logic diagram.
2. Switch ON the IC trainer board.
3. Apply the input combinations as per the truth table.
4. Note its corresponding output level.
5. Repeat the above procedure.
6. Switch OFF the IC trainer kit.
7. Disconnect the components.
RESULT:
Thus the 4 to 2 encoder and 2 to 4 decoder circuit has been designed and
implemented using logic gates.
DESIGN AND IMPLEMENTATION OF MAGNITUDE
COMPARATOR
AIM:
To design and implement 2-bit magnitude comparator using logic
gates.
APPARATUS REQUIRED:
S.NO DESCRIPTION RANGE QUANTITY
1. IC Trainer Board Digital 1
2. AND Gate IC7408 1
3. EX-OR Gate IC7486 1
4. OR Gate IC7432 1
5. NOT Gate IC 7404 1
6. Patch Cords - As required
THEORY:
A magnitude digital Comparator is a combinational circuit
that compares two digital or binary numbers in order to find out whether
one binary number is equal, less than, or greater than the other binary number.
We logically design a circuit for which we will have two inputs one for A and
the other for B and have three output terminals, one for A > B condition, one
for A = B condition, and one for A < B condition
MAGNITUDE COMPARATOR:
LOGIC DIAGRAM:
TRUTH TABLE
INPUTS OUTPUTS
A B
A>B A=B A<B
A1 A0 B1 B0
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
PROCEDURE:
1. Make the connections as per the logic diagram.
2. Switch ON the IC trainer board.
3. Apply the input combinations as per the truth table.
4. Note its corresponding output level.
5. Repeat the above procedure.
6. Switch OFF the IC trainer kit.
7. Disconnect the components.
RESULT:
The two bit magnitude comparator circuit has been constructed and
implemented using logic gates.
DESIGN AND IMPLEMENTATION OF FOUR BIT
RIPPLE UP COUNTER
AIM:
To construct and test the performance of four bit binary ripple up
counter by using IC7473
APPARATUS REQUIRED:
S.NO DESCRIPTION RANGE QUANTITY
1. IC Trainer Board Digital 1
2. JKFF IC7473 2
3. Patch Cords - As required
THEORY:
UP COUNTER:
Asynchronous counters are the circuit that used to count the binary
numbers in prescribed sequence. In asynchronous counter the flip-flops are
not triggered with common clock pulse. Except the first (least significant) flip-
flop others are triggered by the output of previous flip-flop while the first one
is triggered by the clock pulse. Hence asynchronous counter is also called as
ripple counter. When inputs set into logic high the JK flip-flops are
continuously present in the toggle condition which complements the output
continuously. This cause to prevent the circuit from triggering of two adjacent
flip-flops simultaneously.
DOWN COUNTER:
Asynchronous down counter performs the reverse operation of up-
counter which counts the binary number by decreasing one when the flip-flops
are activated by the clock pulse. First flip-flop triggered by clock pulse the
remaining flip-flips are triggered by the inverted output of previous flip-flop.
It is an only difference from up-counter.
4-BIT RIPPLE UP COUNTER:
LOGIC DIAGRAM:
TRUTH TABLE:
PROCEDURE:
1. Make the connections as per the logic diagram.
2. Switch ON the IC trainer board.
3. Apply the input combinations as per the truth table.
4. Note its corresponding output level.
5. Repeat the above procedure.
6. Switch OFF the IC trainer kit.
7. Disconnect the components.
RESULT:
Thus the logic diagram of four bit binary ripple up counter is constructed
and its performance is tested.
DESIGN AND IMPLEMENTATION OF SHIFT
REGISTER
AIM:
To construct and test the performance of shift register using IC
7473.
APPARATUS REQUIRED:
S.NO DESCRIPTION RANGE QUANTITY
1. IC Trainer Board Digital 1
2. JKFF IC7473 2
3. Patch Cords - As required
THEORY:
SHIFT REGISTER: Shift register is a group of flip- flops that has the
capability of storing and shifting the binary information. In digital system the
binary datum are required to shift in the register from one position to next
position. Shift register performs the logic operation shifting of binary data
from one flip-flop to next flip-flop. In the shift register, the shifting operation
is controlled by common clock pulse. All the flip-flops employed with shift
register receive the clock pulse that helps to shift the data from one position to
next.
SERIAL-IN-SERIAL-OUT SHIFT REGISTER: This Shift register is
constructed in the way of connecting the output of one flip-flop to the input of
next flip –flop. All the flip-flops are connected with a common clock pulse.
The binary inputs are applied in the input terminal of first flip-flop in series
and the outputs are obtained from the output terminal of last flip-flop in series.
SHIFT REGISTER:
SERIAL IN PARALLEL OUT:
LOGIC DIAGRAM:
TRUTH TABLE:
PARALLEL IN PARALLEL OUT:
LOGIC DIAGRAM:
TRUTH TABLE:
SERIAL IN SERIAL OUT:
TRUTH TABLE:
Binary data stored in
Serial Input Serial Output
Clock Pulse Register
Data In Q1 Q2 Q3 Q4 Data out = Q4
Initial Vaue 1111 0 0 0 0 0
1st Clk 111 1 0 0 0 0
2nd Clk 11 1 1 0 0 0
3rd Clk 1 1 1 1 0 0
4th Clk - 1 1 1 1 1
SERIAL-IN-SERIAL-OUT SHIFT REGISTER: This register accepts
the binary data in series to provide the output in parallel. In logic diagram the
flip-flops are connected similar to SISO shift register that logic diagram is
constructed in the way of connecting the output of one flip-flop to the input of
next flip-flop. The binary inputs are applied in the input terminal of first flip-
flop in series and the outputs are obtained in parallel from the output terminal
of each flip-flop employed with register. Hence this configuration is called
serial-in-serial-out shift register.
PARALLEL-IN-PARALLEL-OUT SHIFT REGISTER: This
register accepts the binary input in parallel to provide the output in parallel.
All the flip-flops present in the register are triggered with common clock
pulse. The binary inputs are applied in parallel to all the flip-flops and the
outputs are obtained in parallel from the output terminal of each flip-flop
employed with register. Hence this configuration is called parallel-in-
parallel-out shift register.
PROCEDURE:
1. Make the connections as per the logic diagram.
2. Switch ON the IC trainer board.
3. Apply the input combinations as per the truth table.
4. Note its corresponding output level.
5. Repeat the above procedure.
6. Switch OFF the IC trainer kit.
7. Disconnect the components.
RESULT:
Thus the logic diagram of shift register is constructed and its performance
is tested.
