Field-Effect Transistors INTRODUCTION The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to a large extent, those of the BJT transistor. JFET transistor is a voltage-controlled device. For the FET the current Ip will be a function of the voltage V@g applied to the input circuit. The FET is a unipolar device depending solely on either electron (n- channel) or hole (p -channel) conduction. The term field effect in the name deserves some explanation, We are all familiar with the ability of a permanent magnet to draw metal filings to itself without the need for actual contact, The magnetic field of the permanent magnet envelopes the filings and attracts them to the magnet along the shortest path provided by the magnetic flux lines. For the FET an electric field is established by the charges present, which controls the conduction path of the output circuit without the need for direct contact between the controlling and controlled quantities. FIG. 1 voltage-controlled amplifiers. Comparison of some of the general characteristics of BJT with FET: ‘One of the most important characteristics of the FET is its high input impedance, ‘The variation in output current is typically a great deal more for BJT’ than for FETs for the same change in the applied voltage. FETs are more temperature stable than BJTs, and FETs are usually smaller than BJTs, making them particularly useful in integrated-circuit (IC) chips. ‘The construction characteristics of some FETs, however, can make them more sensitive to handling than BJTs. Type of FET: Three types of FETs : the junction field-effect transistor (JFET), the metal-oxide- semiconductor field-effect transistor (MOSFET), and the metal~ semiconductor field-effect transistor (MESFET). The MOSFET category is further broken down into depletion and enhancement types. The MOSFET transistor has become one of the most important devices used in the design and construction of integrated circuits for digital computers. Its thermal stability and other general characteristies make it extremely popular in computer circuit design.CONSTRUCTION AND CHARACTERISTICS OF JFETs JFET is a three-terminal device with one terminal capable of controlling the current between the other two. The major part of the structure is the n-type material, which forms the channel between the embedded layers of p-type material. In the absence of any applied potentials the IFET has two p-n junctions under no-bias conditions. The result is a depletion region at each junction, as shown in Fig, 2 that resembles the same region of a diode under no-bias conditions. en Obmie srchanel FIG.2 Junction field-effect transistor (IFT). Gue@) Depletion Depletion region 8 source(s) V6 =0V, Vos Some Positive Value A positive voltage Vps is applied across the channel and the gate is connected directly to the source to establish the condition VGg =0 V Under the conditions the flow of charge is relatively uninhibited and is limited solely by the resistance of the n-channel between drain and source. ‘The depletion region is wider near the top of both type materials. The current Ip will establish the voltage levels through the channel as indicated on the figure, The result is that the upper region of the p-type material will be reverse-biased by about. ‘As the voltage Vps is increased from 0 V to a few volts, the current will increase as determined by Ohm’s law and the plot of Ip versus Vps.As Vps increases and approaches a level referred to as Vp , the depletion regions will widen, causing a noticeable reduction in the channel width. The reduced path of conduction causes the resistance to increase. The more horizontal the curve, the higher the resistance, suggesting that the resistance is approaching “infinite” ohms in the horizontal region. If Vpg is increased to a level where it appears that the two depletion regions would touch” , a condition referred to as pinch-off will result.FIG3 JFETat Vgs 0 Vand Vpg 70V FIG 4 ID versus VDS for VGS=0 V. Fy g=09) ‘As Vps is increased beyond Vp, the region of close encounter between the two depletion regions. increases in length long the channel, but the level of Ip remains essentially the same, In essence, therefore, once Vos 7 Vp the JFET has the characteristics of a current source. As shown in Fig. 5, the current is fixed at Ip = Ipss, but the voltage Vps (for levels 7 Ve) is determined by the applied load The choice of notation Ipss is derived from the fact that itis the drain-to-source current with a short circuit connection from gate to source..pss is the maximum drain current for a JEET and is defined by the conditions Vgs =0 V and ‘Vps>| VP |. VGS<0V ‘The voltage from gate to source, denoted GS, is the controlling voltage of the JFET. Curves of Ip versus VpS for various levels of VGg can be developed for the JFET. For the n-channel device the controlling voltage VGs is made more and more negative from its VGs= 0 V level. The effect of the applied negative-bias VGg is to establish depletion regions similar to those obtained with VGs 0 V, but at lower levels of Vps. Therefore, the result of applying a negative bias to the gate is to reach the saturation level at a lower level of Vs, as shown in Fig. 6 for VGs ~~ 1 V. The resulting saturation level for [p has been reduced and in fact will continue to decrease as VGg is made more and more negative. Eventually, VGS when VGS ~ — Vp will be sufficiently negative to establish a saturation level that is essentially 0 mA, and for all practical purposes the device has been “turned off.” In summary: ‘The level of VGS that results in ID= 0 mA is defined by VGS =VP, with VP being a negative voltage for n-channel devices and a positive voltage for p-channel JFETs. FIGS FIG. 6 Application ofa negative voltage tothe gate of aJFET. ——n- (Channel JPET characteritis with IDSS= 8 mA and VP = 4 ¥.TRANSFER CHARACTERISTICS Derivation For the BJT transistor the output, /c current and the input controlling J, current are felated by beta, which was considered constant for the analysis to be performed. In equation rm, Ic = fp) = BIB ~(1) The squared term in the equation results in a nonlinear relationship between IT) and VGS, producing a curve that grows exponentially with decreasing magnitude of VGS fos ( vp } -2) ‘The squared term in the equation results in a nonlinear relationship between Ip and VGs, producing a curve that grows exponentially with decreasing magnitude of VGs. ‘The transfer characteristics defined by Shockley’s equation are unaffected by the network in Ip FIG.7 Obtaining the transfer curve from the drain characteristics. DEPLETION-TYPE MOSFET MOSFETs are further broken down into depletion type and enhancement type. The terms depletion and enhancement define their basic mode of operation; the name MOSFET stands for metal-oxide-semiconductor field-effect transistor Basic Constructio The basic construction of the n-channel depletion-type MOSFET is provided in Fig. A slab of p-type material is formed from a silicon base and is referred to as the substrate. It is the foundation ‘on which the device is constructed. In some cases the substrate is internally connected to the source terminal. The gate is also connected to a metal contact surface but remains insulated from the n-channel by a very thin silicon dioxide (SiO2) layer. SiO? is a type of insulator referred to as a dielectric, which sets up ‘opposing (as indicated by the prefix di+) electric fields within the dielectric when exposed fo an externally applied field,Basic Operation: The gate-to-source voltage is set to 0 V by the direct connection from one terminal to the other, and a voltage Vp is applied across the drain-to-source terminals. The result is an attraction of the free electrons of the n-channel for the positive voltage at the drain. The result is a current similar to that flowing in the channel of the JFET. In fact, the resulting current with Vgs_ 0 V continues to be labeled Ips. VG5 is set at a negative voltage such as -I V. The negative potential at the gate will tend to pressure electrons toward the p-type substrate (like charges repel) and attract holes from the p-type substrate (opposite charges attract), Depending on the magnitude of the negative bias established by VGS, a level of recombination between electrons and holes will occur that will reduce the number of free electrons in the n-channel available for conduction, The more negative the bias, the higher is the rate of recombination. The resulting level of drain current is therefore reduced with increasing negative bias for VGS, ENHANCEME! TYPE MOSFET The characteristics of the enhancement-type MOSFET are quite different from depletion type MOSFET. 50, Basie Constructio af ese ‘Avslab of p-type material is formed from a silicon base and is again referred to as the substrate. As with the depletion-type MOSFET, » the substrate. is, sometimes internally connected to the source terminal, whereas in other cases a fourth lead (labeled SS) made available for external control of its potential level. ‘The source and drain terminals ae again connected. through metallic contacts to n-doped regions, but note in Fig. the absence of a channel between the two n-doped regions. This is the primary difference between the construction of depletion-type and enhancement-type MOSFETs—the absence a channel as a constructed component of the device. In summary, therefore, — the. construction of an enhancement-type MOSFET is quite similar to that of A we the depletion-type MOSFET, except for the absence of a channel between the drain and source terminals, brian s \ \ Basic Operation: If VGg is set at 0 V and a voltage applied between the drain and the source of the device of Fig, the absence of an n-channel (with its generous number of free carricrs) will result in a current of effectively 0 A—quite different from the depletion-type MOSFET and JFET, where Ip = Ipss. It is not sufficient to have a large accumulation of carriers (electrons) at the drain and the source (due to the n-doped regions) iff path fails to exist between the two. With Vps some positive voltage, VGg at 0 V, and terminal SS directly connected to the source, there are in fact two reverse-biased p-n junctions between the nedoped regions and the p-substrate to oppose any significant flow between drain and source. The level of VGg that results in the significant increase in drain current is called the threshold voltage and is given the symbol Vr. On specification sheets it is referred to as VGS(Th), although V7 is less unwieldy and will be used in the analysis to follow. Since the channel is nonexistent with Vgs 0 V and “enhanced” by the application of a positive gate-to-source voltage, this type of MOSFET is called an enhancement-type MOSFETFET Biasing For the field-effect transistor, the relationship between input and output quantities is nonlinear due to the squared term in Shockley’s equation. Linear relationships result in straight lines when plotted ‘ona graph of one variable versus the other, whereas nonlinear functions result in curves as obtained for the transfer characteristics of a JFET. The nonlinear relationship between ID and Vs can complicate the mathematical approach to the de analysis of FET configurations. A graphical approach may limit solutions to tenths-place accuracy, but it is a quicker method for most FET amplifiers, Since the graphical approach is in general the most popular, the analysis of this chapter will have graphical solutions rather than mathematical solutions. FIXED-BIAS CONFIGURATION: The simplest of biasing arrangements for the n-channel JFET appears in Fig.1. Referred to as the fixed-bias configuration, FIG.1 Fixed-bias configuration Ry | ¢ For the de analysis, VRG = IGRG = (OA)RG = OV, I, The fact that the negative terminal of the battery is connected directly to the defined positive potential of MGs clearly reveals that the polarity of VGs is directly opposite to that of VGG. Applying Kirchhoff’s voltage law in the clockwise direction results in -VGG -VGS = 0 Ves ~ -VaG Since VGG is a fixed de supply, the voltage GS is fixed in magnitude, resulting in the designation “fixed-bias configuration.” The drain-to-source voltage of the output section can be determined by applying Kirchhoff’s voltage law as follows: Vps = Yop - 1D Rp= Vos += Vps + OV, Ko Voste=Vos Nop ‘SELF-BIAS CONFIGURATION The self-bias configuration eliminates the need for two de supplies. The controlling gate-to-source voltage is now determined by the voltage across a resistor Rg introduced in the source leg of the configuration. For the de analysis, the capacitors can again be replaced by “open circuits” and the resistor RG replaced by a short-circuit equivalent since IG = 0A The current through Rg is the source current Ig, but Is = Ip and Vrg = IDRS Vos =—TpRs that Vs is a function of the output current Ip and not fixed in magnitude as occurred for the fixed-bias configuration, The basic construction is exactly the same, but the de analysis of each is quite different. 1G = 0.A for FET amplifiers, but the magnitude of / for common-emitter BIT amplifiers can affect the de levels of current and volt- age in both the input and output ircuits. Recall that /g provides the link between input and output circuits for the v, BIT — voltage-divider configuration, whereas VGS does the same for the FET configuration. Yoo Since IG = 0A, Kirchhoff's current law requires that JR, = [R2, and the series equivalent circuit appearing to the left of the figure can be used to find the level of VG. The voltage VG, equal to the voltage across R2, can be found using the voltage- divider rule as follows RV op Rt Ry Applying Kirchhoff’s voltage law Vos=Vo~loRs ¥Feedback Amplifiers and Oscillator: Feedback implies the transfer of energy from the output of a system to its input. If a portion or the whole of the output signal of an amplifier is fed back and superimposed on the input signal, the performance of the amplifier changes significantly. Then the amplifier is said to be a feedback amplifier. ‘Negative/Inverse/Degenerative Feedback:- Feedback signal diminishes the magnitude of the input signal. Positive/Direct/Regenerative Feedback:~ Feedback signal enhances the magnitude of the input signal ‘Negative/Inverse/Degenerative Feedback In the above circuit the input signal to the amplifier with gain A is the difference of the input signal Vs and feedback signal Vr. The feedback circuit can contain passive elements like resistors, inductors, capacitors and active elements like transistors. ‘Transfer Gain of a feedback amplifier: VorAV; (A= Vo! Vi is the gain without feedback or open loop gain) Vi=BVo (B= 'fVo is known as the feedback fraction, the feedback ratio, the reverse transfer ratio or the reverse transmission factor) VieVe Ve (Positive sign for positive feedback) Vs= VitVe VolAt BVo APVolV.-A(1+AB) is the gain with feedback called as closed loop gain. The quantity AB is called as loop gain, the feedback factor, the return ratio or the loop transmission. ‘The feedback introduced into an amplifier is usually expressed in decibles(dB) by the relationshipF=<4B of Feedback =20log:0 — =201og1 — For negative feedback F is negative and for positive feedback F is positive. Feedback amplifier topologies: Depending up on the input mixer and output sampler configuration we have 4 feedback topologies. 1. Voltage Series 2. Voltage Shunt 3. Current Series 4, Current Shunt Effect of ‘Negative rein} Feedback: A number of improvements are obtained in negative feedback Better stabilised voltage gain Higher input impedance and lower output impedance Improved frequency response Reduced noise ‘More linear operation ve Positive/DirectRegenerative Feedback: In positive feedback input signal to the amplifier with gain A is the additione of the input signal Vo and feedback signal Ve. Vo=AViVer BVo VEVeVe Vs= Vi -Ver VolA- BVo ArVolV.=A/(1-AB) Oscillator Operation: yp + WeBay = The use of positive feedback that results in a feedback amplifier having closed-loop gain Ar ‘greater than 1 satisfies the phase conditions will result in operation as an oscillator. When the switch at the amplifier input is open, no oscillation occurs. Considering fictitious voltage Vi at the amplifier input Vo=AV;. And V-ABVi. If the circuits of the base amplifier and the feedback network provide AB of a correct magnitude and phase, Vy can be made equal to V,, Then, when the switch is closed and the fictitious voltage Vi is removed, the circuit will continue operating since the feedback voltage is sufficient to drive the amplifier, resulting in a proper input voltage to sustain the loop operation, The output waveform will still exist after the switch is closed if the condition AB=1 is met. This is known as Barkhausen criterion for oscillation,