Course Code Course Name Course Structure

ECECC12 Microprocessors and L-T-P 3-0-2

Computer Architecture

COURSE OUTCOME (CO):

CO1: To comprehend the instruction set architecture of 8085 microprocessor,

instruction cycle and concept of interfacing

CO2: To understand instruction set architecture of 8086 microprocessor.

CO3: To familiarize students with processor architecture, instruction set

architecture and assembly language programming in general

CO4: To develop understanding and operation of memory system and different

memory types.

UNIT-1
8086 PROCESSOR: Von-Neumann & Harvard CPU architecture and CISC &
RISC CPU architecture 8086 CPU Architecture. Addressing modes.
Physical memory Organization, General Bus operation cycle, I/O
addressing capability, Special processor activities, Minimum mode 8086
system and Timing diagrams, Maximum Mode 8086 system and Timing
diagrams.

INSTRUCTION SET OF 8086: Data transfer and arithmetic instructions.

Control/Branch Instructions, Logical Instructions, String manipulation
instructions, Flag manipulation and Processor control instructions,
Illustration of these instructions with example programs. Assembler
Directives and Operators, Assembly Language Programming and example
programs

UNIT-2
Introduction to stack, Stack structure of 8086, Programming for Stack.
Interrupts and Interrupt Service routines, Interrupt cycle of 8086, NMI,
INTR, Interrupt programming, Passing parameters to procedures, Macros,
Timing and Delays.

Basic Peripherals and their Interfacing with 8086: Static RAM Interfacing
with 8086 (5.1.1), Interfacing I/O ports, PIO 8255, Modes of operation –
Mode-0 and BSR Mode, Interfacing ADC-0808/0809, DAC-0800, 8259.

UNIT-3
CPU structure and functions, processor organization, ALU, datapaths,
internal registers, status flags; System bus structure: Data, address and
 control buses, Processor control, micro-operations, instruction fetch,
hardwired vs. microprogrammed control, microinstruction sequencing and
execution,

Unit-4
Instruction set principles, machine instructions, types of operations and
operands, encoding an instruction set, assembly language programming,
addressing modes and formats. Pipelining: basic concepts of pipelining,
throughput and speed, pipeline hazards, Comparison between CISC and
RISC architecture, Introduction to RISC-V and domain specific
architectures

UNIT-5
Memory system, internal and external memory, memory hierarchy, cache
memory and its working, virtual memory concept, I/O organization; I/O
techniques: interrupts, polling, DMA; Synchronous vs. asynchronous I/O.
Text Books:

[T2] Hall, D.V., “Microprocessors and Interfacing”, 2nd Ed., Tata McGrawHill.
2006
[T3] D.A. Patterson, J.L. Hennesey, “Computer Architecture: A Quantitative Approach”,
Sixth Edition, Morgan Kaufmann, 2017.
[T4] Brey, B.B., “The Intel Microprocessors”, 6th Ed., Pearson Education.
2003
[T5] Mano, M.M., “Computer System Architecture” 3rd Ed., Prentice-Hall of
India. 2004
[T6] Mano M. M., Cilleti M. D., “ Digital Design”5th Edition, Pearson 2013
[T7] Rajaraman, V. and Radhakrishnan, T., “Computer Organization and
Architecture”, Prentice-Hall of India. 2007
[T8] Govindrajalu, B., “Computer Architecture and Organization”, Tata
McGraw-Hill. 2004
[T9] Stallings, W., “Computer Organization and Architecture”, 5th Ed.,
Pearson Education. 2001
[T10] John E. Uffenbeck,” 8086/8088 Design programming and interfacing,’’ Prentice Hall of
India 1997.

List of Experiments

Basic Exercise 1:
To understand the operation of the kit, the various components on the kit and
their functions.
List out the major components that you see on the kit. Find out the function of
these components and classify these components into the various broad
categories of components
Write a suitable report.

Basic Exercise 2:
Read the manual supplied with the Vinytics kit. The keyboard on the kit has two
groups of keys: red keys and black keys. Understand the operation of all the red
keys. The red keys are function keys and the black keys are data keys.
Power up the kit and using the function keys store a few arbitrary numbers in
the SRAM chip of the kit. Now power off the kit for a few minutes and power it
up again. Inspect the SRAM locations again and verify that the contents of these
SRAM locations have not changed even after you powered down the Kit. Find out
why. Give your suggestions for the implementation of a circuit that would help
retain the contents of the SRAM even if the main power is turned off. Can you
replace the SRAM chips with any other type of chip and still be able to modify
the contents of those chips? What would be the advantages or disadvantages of
those alternatives? Write a report.

Basic Exercise 3:
At this point you are familiar with the basic operation of the kit..
Write a program to add a series of 10 numbers. These numbers are stored in
consecutive memory locations in the SRAM. The result should be stored in the
memory locations following the input data. What should be the size of the result
location? What if you were to add a series of 1000 numbers? How much result
storage space would be sufficient? Write a report.

Experiments:

1. Write a program to arrange the 10 numbers in SRAM memory in ascending

order. Repeat you experiment to arrange the data in descending order.
2. Develop a subroutine for Multiply and divide operations.
3. Write routines to convert Binary to ASCII, ASCII to binary, binary to BCD, BCD
to binary.
4. Write a program to test the RAM on the Kit.
5. Study the operation of 8255 Interface Card. As outlined in the 8255 Study
Card Manual.
6. Study of 8259 Interface Card. As outlined in the 8259 Study Card Manual.
7. Move a block of data from a source address location to target address location
using assembly language programming in 8086
8. Design, model and test using HDL (hardware description language), a Sign
magnitude adder, BCD incrementor, Gray Counter and LFSR based random
number generator.
9. Design model and test using HDL a PWM based LED Dimmer
10. Design model and test using HDL a single switch and keypad matrix de-
bouncing system.
11. Design and model using HDL, the following LED multiplexing schemes:
regular LED
multiplexing, Charlieplexed LED multiplexing.
12. Design, model and test using HDL, a multi-stage Dice game.
13. HDL behavioral model for a 32-bit MIPS ALU

Note: Course teachers may design 3-4 new experiments/small projects in

addition to the above suggested practical exercises.