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26 March 2018 1439 رجب9
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IC Layout
Lecture 04
Essential Layout Techniques
Dr. Hesham A. Omran
Integrated Circuits Lab (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
This lecture is mainly based on “IC Mask Design” by C. Saint and J. Saint, 2002
Padframe and IO Cells
CHIP CORE
04: Layout Techniques 2
ESD Protection
Any ESD current will flow in the ESD diodes instead of flowing into
the circuit
The diodes should be large enough to handle high current spikes
04: Layout Techniques 3
Digital Layout
Fixed height, variable width
Continuous VDD, GND, and NWELL
Bad Good
04: Layout Techniques 4
Digital Layout
Fixed height, variable width
Share power rails between flipped rows
No need for routing channels in modern technologies
04: Layout Techniques 5
Strapping Power Rails
Distant cells see more resistance through the rails due to the
length of wire
By laying straps of metal across your power rails the overall
resistance reduces
04: Layout Techniques 6
Directional Layer Technique
Metal One runs horizontally and Metal Two runs vertically
Allows wires to run in complex knots using few metal layers
without becoming trapped
Common for digital signals, but is not strictly followed for sensitive
analog/RF signals
04: Layout Techniques 7
Directional Layer Technique
This rule is not useful for short jumps
– Via resistance
– Blocking other wires
Do NOT change metal layer for short jumps
04: Layout Techniques 8
Directional Layer Technique
This rule is not useful for short jumps
– Via resistance
– Blocking other wires
Do NOT change metal layer for short jumps
04: Layout Techniques 9
Digital vs Analog Layout
Digital layout
– Primary objective is optimizing density
– Millions of gates
– Strict standard cell rules
Analog layout
– Primary objective is matching and performance
– Few amplifiers
– Many options instead of many rules
– Strong interaction required between circuit and layout
designers
04: Layout Techniques 10
Layout Designer Questions
What does this circuit do (function, frequency, precision, etc.)?
How much current does it take (current density, min wire width)?
Where are the high and low current paths (not all wires will carry
high current)?
What matching requirements are there?
Is there anything else?
04: Layout Techniques 11
Layout Designer Questions
04: Layout Techniques 12
Ex: Routing with Multi-finger Device
Route from center not from
sides
– Current spread out evenly
Ex: four-finger MOSFET
– 4 mA current
– 0.5 mA/um max density
– 8 um min wire
– 3 source regions
– 2 drain regions
– Source/drain metallization
must handle the required
current
04: Layout Techniques 13
Parasitic Capacitance
Capacitance in the order of fF
Important for high frequency and precision circuits
– Use short wire length
– Use isolated wire (far from everything else)
You have to look at metal height from subs, width, and thickness
04: Layout Techniques 14
Parasitic Capacitance
Capacitance in the order of fF
Important for high frequency and precision circuits
– Use short wire length
– Use isolated wire (far from everything else)
You have to look at metal height from subs, width, and thickness
04: Layout Techniques 15
Parasitic Capacitance
Capacitance in the order of fF
Important for high frequency and precision circuits
– Use short wire length
– Use isolated wire (far from everything else)
You have to look at metal height from subs, width, and thickness
04: Layout Techniques 16
Parasitic Capacitance
Avoid Routing over Circuitry
– Not important in digital, but may affect sensitive analog
blocks/signals
A good floorplan will help
04: Layout Techniques 17
Parasitic Resistance
May cause large I*R drops
Ex:
– 2mm long / 2 um width = 1000 squares
– R = 1000 squares * 50 mOhm/square = 50 Ohm
– Vdrop = I*R = 50 mV definitely not acceptable
Increase wire width to reduce resistance
– Max current density is not the only thing to worry about
Or use thick metal in higher layers
Or stack wires to save space
04: Layout Techniques 18
Parasitic Resistance
May cause large I*R drops
Ex:
– 2mm long / 2 um width = 1000 squares
– R = 1000 squares * 50 mOhm/square = 50 Ohm
– Vdrop = I*R = 50 mV definitely not acceptable
Increase wire width to reduce resistance
– Max current density is not the only thing to worry about
Or use thick metal in higher layers
Or stack wires to save space
04: Layout Techniques 19
MOS Capacitance/Resistance
Use multi-finger layout
– Reduces gate resistance (multiple gate stripes in parallel)
• Splitting the device into two reduces RC time constant by 4
– Drain/source sharing reduces capacitance
04: Layout Techniques 20
Matching: Orientation
orientation-specific processing errors will severely degrade
matching
Use the same orientation for matched devices
Also good practice to use the same orientation all over the chip
– Now a design rule for FinFET
04: Layout Techniques 21
Matching: Orientation
Current should be flowing in same direction
04: Layout Techniques [F. Maloberti, Layout of Analog CMOS IC] 22
Matching: Unit Elements
Applies to all components: transistors, resistors, capacitors, etc.
04: Layout Techniques 23
Matching: Unit Elements
Terrible
Good (use lowest common multiple)
04: Layout Techniques 24
Matching: Unit Elements
Terrible
Better (use middle value)
– Less contact resistance (their variation is worse)
– Larger area (less mismatch) (overall area is roughly the same)
– Note: Do NOT connect unit caps/transistors in series
04: Layout Techniques 25
Matching: Interdigitation
Place the root component (LSB) in the center
04: Layout Techniques 26
Matching: Interdigitation
Each of A and B is 4 fingers
– AABBAABB
– ABBAABBA
2 3
A B
04: Layout Techniques [F. Maloberti, Layout of Analog CMOS IC] 27
Matching: Dummies
Structures at the ends have different boundary conditions
compared to structures in the middle
Edges suffer from a big difference
04: Layout Techniques 28
Matching: Dummies
Dummy structures MUST be used
Applies for transistors, resistors, and capacitors
Dummy devices connected to GND (NMOS) or VDD (PMOS)
Dummy gate should not be connected to input to avoid increasing
capacitive loading
04: Layout Techniques [F. Maloberti, Layout of Analog CMOS IC] 29
Matching: Dummies
2D arrays need dummies all around
04: Layout Techniques 30
Matching: Common Centroid
Reduces the effect of process and thermal gradients (1st order)
Essential for differential input pair
Cross-quad matches better than linear, but takes more time to do
04: Layout Techniques 31
Matching: Common Centroid
Reduces the effect of process and thermal gradients (1st order)
Essential for differential input pair
Cross-quad matches better than linear, but takes more time to do
Ex: diff pair with AABBBBAA arrangement
04: Layout Techniques [Johns and Martin, 2012] 32
Matching: Common Centroid
Reduces the effect of process and thermal gradients (1st order)
Essential for differential input pair
Cross-quad matches better than linear, but takes more time to do
04: Layout Techniques [F. Maloberti, Layout of Analog CMOS IC] 33
Matching: Common Centroid
Reduces the effect of process and thermal gradients (1st order)
04: Layout Techniques [Johns and Martin, 2012] 34
Matching: Common Centroid
Reduces the effect of process and thermal gradients
04: Layout Techniques [F. Maloberti, Layout of Analog CMOS IC] 35
Matching: Match the Parasitics
Use extra metal overlaps to match wiring capacitance
04: Layout Techniques 36
Matching: Symmetry
A is supposed to talk to B and C in the same way
Capacitance to B and C should be matched
Bad
Good
04: Layout Techniques 37
Matching: Symmetry
A is supposed to talk to B and C in the same way
Capacitance to B and C should be matched
Bad
Good
04: Layout Techniques [F. Maloberti, Layout of Analog CMOS IC] 38
Matching: Differential Routing
Bad
Good
04: Layout Techniques 39
Matching: Differential Routing
04: Layout Techniques 40
Matching: Go Large
Remember Pelgrom’s model
Never use min feature sizes
04: Layout Techniques 41
Matching: Summary
04: Layout Techniques 42
Substrate Noise
Very critical issue in mixed-signal chips
04: Layout Techniques 43
Substrate Noise: Go Far Away
04: Layout Techniques 44
Substrate Noise: Timing
04: Layout Techniques 45
Substrate Noise: Guard Rings
04: Layout Techniques 46
Substrate Noise: Guard Ring
Avoid ANY current flow in guard rings
Best practice: connect the substrate and guards with a separate
star connection to the GND pad (or use double bonds)
04: Layout Techniques [www.eda-utilities.com] 47
Substrate Noise: Guard Ring
Avoid ANY current flow in guard rings
Best practice: connect the substrate and guards with a separate
star connection to the GND pad (or use double bonds)
04: Layout Techniques [www.eda-utilities.com] 48
Substrate Noise: N-Well Barrier
Separate analog and digital areas by an n-well
– High resistance path between analog and digital substrates
– Minimize the injection of noise from digital circuits into the
substrate under the analog circuit
The well also acts as a bypass capacitor
04: Layout Techniques [Johns and Martin, 2012] 49
Substrate Noise: Double Guard Ring
Conservative layout: VDD guard ring collect stray electrons in the
substrate
04: Layout Techniques [www.eda-utilities.com] 50
Substrate Noise: Double Guard Ring
Conservative layout: GND guard ring collect stray holes in the
substrate
04: Layout Techniques [www.eda-utilities.com] 51
Substrate Noise: Shielding
The GND line used for shielding must have quite low resistance
04: Layout Techniques 52
Shielding Sensitive/Noisy Signals
04: Layout Techniques 53
Routing Power Rails
Better to place high current blocks near power pad
Wire width can be tapered
04: Layout Techniques 54
Routing Power Rails
Better to place high current blocks near power pad
Wire width can be tapered
Better technique: high current power line should be routed
independently
– Star vs bus
04: Layout Techniques 55
Routing Power Rails
Use lowest resistance metal layer
Use FAT wires
– Do not use min width
– Do not stress the wire at its max current density
– Roughly 10% of the cell height
04: Layout Techniques 56
Supply Decoupling
Decoupling provide low resistance path for high frequency noise
Fill any white space in the layout with decoupling caps
Stacked power rails give some free decoupling caps
04: Layout Techniques 57
Vias
For analog and high current signals
– Do NOT use min metal width
– Do NOT use single via
Bad Good
04: Layout Techniques 58
Floorplanning: Wiring
Neat flylines indicate good floorplanning
Bad
Good
04: Layout Techniques 59
Floorplanning: Wiring
Minimizing the area is good
– But you must leave enough space for wiring
Remember that “in general” you cannot route over other blocks
Shielding, differential routing, power and clock routing, guard
rings, etc., all take a lot of area
04: Layout Techniques 60
Floorplanning: Wiring
Bigger area, but more realistic
04: Layout Techniques 61
Floorplanning: Wiring
Leave some free space for wiring, decoupling caps, last minute
updates, etc.
Bad Good
04: Layout Techniques 62
Floorplanning: Pinout
Inputs and outputs should be located near their appropriate cell
block
04: Layout Techniques 63
Floorplanning: ESD
Bad
Good
04: Layout Techniques 64
Floorplanning: Signal Flow
Flow of sensitive signals may dictate specific block placement
– Specifically important for RF signals at very high frequencies
04: Layout Techniques 65
Iterative Floorplanning
Bad Good
04: Layout Techniques 66
Clock Tree
The clock should tick at all elements exactly at the same time
04: Layout Techniques 67
The Package
The package type must be planned even before floorplanning
– The pinout (floorplanning)
– Chip area (the chip must fit inside the package)
04: Layout Techniques 68
Wire Bonding
The bond wire is ultra-thin (~25um) Gold or Aluminum wire
Ultrasonic wedge bonding
– Uses brute force (pressure) and ultrasound (vibration)
Ultrasonic ball bonding
– Uses high voltage and ultrasonic to melt the wire
04: Layout Techniques 69
Wire Bonding Rules
No sharp angles are allowed in wire bonding (< 45o)
Keep wires as short as possible
– The bondwire could droop causing a short circuit
04: Layout Techniques 70
Bonding Diagram
No sharp angles are allowed in wire bonding (< 45o)
Keep wires as short as possible
Bad Good
04: Layout Techniques 71
Pad-limited vs Core-limited Design
Pad-limited Core-limited
04: Layout Techniques 72
Flip-chip Packaging
Deposit bump of solder on each pad
Flip, press, and heat
Pads are not restricted to the periphery
04: Layout Techniques 73
Dicing
Diamond saw cuts wafer into chips
– Seal ring around the whole chip
– Keep some room for the saw to run (~ 50 – 100um) “Scribe
Lanes”
– Keep a “scribe margin” away from the scribe lanes
04: Layout Techniques 74
Dicing
The final size is what will go inside the package!
04: Layout Techniques 75
Thank you!
04: Layout Techniques 76
