CENG335: Digital Logic II

Sections 3.6-3.7
LUTs, PLDs, FPGA

Lecture 3
 Chapter 3.6 Programming Logic
Devices
• A PLD is a general-purpose chip for implementing logic
circuitry
– It contains a collection of logic circuit elements that can be
customized in different ways
– A PLD can be viewed as a black box that contains logic gates and
programmable switches
 Programmable Logic Arrays (PLA)
• First PLD is the PLA: programming Logic Array
– Its based on the idea of the sum-of products form
– It comprises a collection of AND gates and a set of
OR gate
 Programmable Logic Arrays (PLA)
• P! = 𝑥! 𝑥"
• P" = x! 𝑥# ,
• P# = 𝑥! 𝑥" 𝑥# ,
• P$ = 𝑥! 𝑥#
• => f!

• => f"
•
Programmable Logic Arrays (PLA)
 Programmable Array Logic (PAL)
• In PLA both AND and OR planes are
programmable
– They are Hard to fabricate
– They reduced speed performance of circuits
implemented in PLA
• These problems led to the development of PAL
devices:
– AND gates are programmable and OR gates are fixed
– simpler to manufacture
– Less expensive
– Less flexibility
• PLA allows to 4 product terms per OR gate whereas the OR
Gate in PAL have only two inputs
 Programmable Array Logic (PAL)
• Example of a PAL with three inputs four
product terms and two output
 CPLD Complex Programmable Logic
Devices
• PLA and PAL are useful to implement small
digital circuits
– Typical combined number of inputs and outputs
does not exceed 32
• A CPLD comprises multiple circuit blocks on a
single chip, with internal wiring resources to
connect the circuit blocks
– Each circuit block is similar to a PLA or a PAL;
• we will refer to the circuit blocks as PAL-like blocks
CPLD Complex Programmable Logic
Devices
 Field Programmable Gate Arrays
• CPLDs, only moderately large logic circuits can be
accommodated in a single chip.
• One way to quantify a circuit’s size is to assume that
the circuit is to be built using only simple logic gates
and then estimate how many of these gates are
needed.
– A commonly used measure is the total number of two-
input NAND gates that would be needed to build the
circuit;
– This measure is often called the number of equivalent
gates.
• Thus a typical PAL that has eight macro cells can accommodate a
circuit that needs up to about 160 gates,
• and a large CPLD that has 500 macro cells and can implement
circuits of up to about 10,000 equivalent gates.
 Field Programmable Gate Arrays
• By modern standards, a logic circuit with 10,000 gates is
not large.
• A field-programmable gate array (FPGA) is a programmable
logic device that supports implementation of relatively
large logic circuits.
– The general structure of an FPGA is illustrated on the next slide.
– It contains three main types of resources: logic blocks, I/O
blocks for connecting to the pins of the package, and
interconnection wires and switches.
• FPGAs can be used to implement logic circuits of more than
a million equivalent gates in size.
– Some examples of commercial FPGA products, from Altera and
Xilinx,
Field Programmable Gate Arrays
 Field Programmable Gate Arrays
• Each logic block has small number of input
and outputs
– The most commonly used logic block is the lookup
table LUT
• LUT contains storage cells used to implement small
logic function
• Each cell is capable of holding a single logic value 0 or 1
• This value is the output of the storage cell
• The storage cell is of various sizes defined by the
number of inputs
• This is a small LUT of two inputs and one output
– It is capable of implementing any logic function of two
variables
– Because a two variable truth table has 4 rows this LUT has
four storage cells
• One cell corresponds to the output value in each row of the truth
table
– The input variables x1 and x2 are used as the select inputs
of three multiplexers, which, depending on the valuation
of x1 and x2, select the content of one of the four storage
cells as the output of the LUT.
 Field Programmable Gate Arrays
• The arrangement of multiplexers in the LUT
correctly realizes the function f
• When x1 = x2 = 0, the output of the LUT is driven
by the top storage cell, which represents the
entry in the truth table for x1x2 = 00.
 Field Programmable Gate Arrays
• three-input LUT. It has
eight storage cells
because a three-
variable truth table
has eight rows
• In commercial FPGA
chips, LUTs usually
have either four or
five inputs, which
require 16 and 32
storage cells,
respectively
 Field Programmable Gate Arrays
• shows how a flip-flop may be included in an
FPGA logic block.
• the flip-flop is used to store the value of its D
input under control of its clock input.
 Field Programmable Gate Arrays
• For a logic circuit to be realized in an FPGA, each logic function in
the circuit must be small enough to fit within a single logic block.
– CAD tools are responsible for it

• The storage cells in the LUTs in an FPGA are volatile, which means
that they lose their stored contents whenever the power supply for
the chip is turned off.
– Hence the FPGA has to be programmed every time power is applied.
– Often a small memory chip that holds its data permanently, called a
programmable read-only memory (PROM), Is included on the circuit
board that houses the FPGA.
– The storage cells in the FPGA are loaded automatically from the
PROM when power is applied to the chips.
 Field Programmable Gate Arrays
• A small FPGA is shown to implement a circuit
• The FPGA has two-input LUTs, and there are four wires in each routing channel.
• The figure shows the programmed states of both the logic block sand wiring switches in a section of the
FPGA.
 x3 f
Implement f on an FPGA using
2 input LUT

x1
0 0
0 f1 1 f2
x2 0 0
1 0

0
1 f
1
1