6.

012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-1

Lecture 20 - Transistor Amplifiers (II)

Other Amplifier Stages

November 17, 2005

Contents:

1. Common-source amplifier (cont.)

2. Common-drain amplifier
3. Common-gate amplifier

Reading assignment:

Howe and Sodini, Ch. 8, §§8.7-8.9

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-2

Key questions

• What other amplifier stages can one build with a sin-

gle MOSFET and a current source?
• What is the uniqueness of these other stages?

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-3

1. Common-source amplifier with current-source

supply
VDD

iSUP
signal source
signal
RS iD + load

RL
vs vOUT

VGG
-

VSS

Loadline view:

load line
iSUP=ID

VGG-VSS=VDD-VSS

ISUP VGG-VSS

VGG-VSS=VT
0
VSS VDD VOUT
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-4

Current source characterized by high output resistance:

roc.

Then, unloaded voltage gain of common-source stage:

|Avo | = gm (ro //roc )

significantly higher than amplifier with resistive supply.

Can implement current source supply by means of p-

channel MOSFET:

VDD

VB iSUP
signal source

RS iD +

vs vOUT

VGG
-

VSS

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-5

• Relationship between circuit figures of merit and device

parameters

Remember:
�
�
�
W �
�
gm = 2 µnCox ID
�
L
1 L
ro
∝
λnID ID
Then:
Circuit Parameters
Device ∗ |Avo | Rin Rout
Parameters gm (ro//roc ) ∞ ro//roc
ISU P ↑ ↓ - ↓

W ↑ ↑ - -

µnCox ↑ ↑ - -

L↑ ↑ - ↑
∗
adjustments are made to VGG so
none of the other parameters change

CS amp with current supply source is good voltage am-

plifier (Rin high and |Av | high), but Rout high too ⇒
voltage gain degraded if RL  ro//roc .
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-6

Common-source amplifier is acceptable voltage amplifier

(want high Rin, high Avo , low Rout ):

RS Rout

+ +
vs + vin + Avovin
Rin RL vout
− −
− −

... but excellent transconductance amplifier

(want high Rin, high Gmo , high Rout ):

RS iout

+
vs + vin Gmovin RL
Rin Rout
−
−

For common-source amplifier:

Gmo = gm
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-7

Common-source amplifier does not work as transresis-

tance amplifier (want low Rin, high Rmo , low Rout ):

iin Rout

+
is + Rmoiin vout
RS Rin RL
−
−

nor as current amplifier

(want low Rin, high Aio , high Rout ):

iin iout

is RS Rin Aioiin Rout RL

Need new amplifier configurations.

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-8

2. Common-drain amplifier

VDD

signal source

RS

signal
vs + load
iSUP RL
vOUT
VGG
-
VSS

How does it work?

• VGG, ISU P , and W/L selected to bias MOSFET in

saturation, obtain desired output bias point, and de-
sired output swing.
• vG ↑ ⇒ iD can’t change ⇒ vOU T ↑

(source
(sour follower)
r)

ce follower
• to first order, no voltage gain: vout
vs
• but Rout small: effective voltage buffer stage
(good for making voltage amp in combination with
common-source stage).
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-9

2 Small-signal analysis

Unloaded small-signal equivalent circuit model:

D
G
+ +

vgs gmvgs ro
- S
vin
+
roc vout
- -

+ vgs -
+ +
vin gmvgs ro//roc vout
- -

vin = vgs + vout

vout = gmvgs(ro //roc)

Then:
gm
Avo = 1
1
gm + ro //roc
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-10

Input impedance: Rin = ∞

Output impedance:

+ vgs -
it
+
+
RS vin gmvgs ro//roc vt
-
-

vgs=-vt

effectively:
it
resistance of

value 1/gm
+
gmvt ro//roc vt
-

1 1
Rout = 1

gm + ro //roc
gm

small!

Loaded voltage gain:

RL RL
Av = Avo
1
1
RL + Rout RL + gm
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-11

2 Effect of back bias:

If MOSFET not fabricated on isolated p-well, then body

is tied up to wafer substrate (connected to VSS ):

VDD

signal source

RS
VSS
signal
+ load
vs
iSUP RL
vOUT
VGG
-
VSS

Two consequences:

• Bias affected: VT depends on VBS = VSS − VOU T = 0

• Small-signal figures of merit affected: signal shows up

between B and S (vbs = −vout).
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-12

Small-signal equivalent circuit model:

D
G
+ +
vgs gmvgs gmbvbs ro
- S
vin -
+
vbs roc vout
- +B -

vbs=-vout

+ vgs -
+ +
vin gmvgs gmbvout ro//roc vout
- -

gm gm
Avo = 1
<1
gm + gmb + ro //roc
gm + gmb

Also:

1 1
Rout = 1

gm + gmb + ro //roc
gm + gmb
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-13

2 Relationship between circuit figures of merit and device

parameters:
�
�
�
�
�
W
gm = 2 � µnCox ID
L

gmb = � gm
2 −2φp − VBS

Circuit Parameters
Device ∗ |Avo | Rin Rout
1
Parameters gmg+g
m
mb
∞ gm+gmb
ISU P ↑ - - ↓
W ↑ - - ↓
µnCox ↑ - - ↓
L↑ - - ↑
∗
adjustments are made to VGG so
none of the other parameters change

CD amp useful as a voltage buffer to drive small loads

(in a multistage amp, other stages will be used to provide
voltage gain).
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-14

3. Common-gate amplifier

Need to handle current-mode signal sources:

VDD

iSUP
iOUT signal
load
VSS
RL
signal source

is RS IBIAS

VSS

How does it work?

• since source is signal input terminal, body cannot be
tied up to source (Cdb is significant)
• iSU P , IBI AS , and W/L selected to bias MOSFET in
saturation, obtain desired output bias point, and de-
sired output swing
• iS ↑ ⇒ iD ↓ ⇒ iOU T ↓
• no current gain: is = −iout (curr
(current
ent buffer)
bufferr)
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-15

2 Bias: select ISU P , IBI AS , and W/L to get proper qui-

escent IOU T and keep MOSFET in saturation.
VDD

ISUP
IOUT

VSS

IBIAS

VSS

ISU P + IOU T + IBI AS = 0

Select bias so that IOU T = 0 ⇒ VOU T = 0.

Assume MOSFET in saturation (no channel modulation):

W
ID = µnCox (VGS − VT )2 = ISU P = −IBI AS
2L
but VT depends on VBS :
� �
VT = VT o + γn( −2φp − VBS − −2φp )

Must solve these two equations iteratively to get VS .

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-16

2 Small-signal circuit (unloaded)

iout
D
+ G

vgs gmvgs gmbvbs ro

- S
roc
-
vbs is
+ B

vbs=vgs

is vgs gmvgs gmbvgs ro

+

iout

is gm gmb ro

iout

iout
is = −iout ⇒ Aio = − = −1
is

Not surprising, since in a MOSFET: ig = 0.

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-17

Input resistance:
+

vgs gmvgs gmbvgs ro

-
roc RL
+
it vt
-

vgs=-vt

gmvt gmbvt ro

it vt

roc//RL
-

Do KCL on input node:

vt − (roc //RL )it
it − gmvt − gmbvt − =0
ro
Then:
1 + roc //R L
1

Rin = ro


gm + gmb + r1o gm + gmb

Very small.

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-18

Output resistance:
+

vgs gmvgs gmbvgs ro it

- +
roc vt
-
RS

vgs gmvgs gmbvgs ro it'

- +
vt'
-
RS

Do KCL on input node:

vt
+ vgs
i
t − gmvgs − gmb vgs − =0
ro
Notice also:

vgs = −i
tRS
Then:
1
Rout = roc//{ro [1+RS (gm +gmb + )]}
roc//[ro (1+gm RS )]
ro

Very large, because of the feedback effect of RS .

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-19

Summary of MOSFET amplifier stages:

stage Avo , Gmo , Aio Rin Rout key function

common source Gmo = gm ∞ ro //roc transconductance amp.

gm 1
common drain Avo
gm +gmb ∞ gm +gmb voltage buffer

1
common gate Aio
−1 gm +gmb roc //[ro(1 + gm RS )] current buffer

In order to design amplifiers with suitable performance,

need to combine these stages ⇒ multistage amplifiers

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 20-20

Key conclusions

Different MOSFET stages designed to accomplish differ-

ent goals:

• Common-source stage:

– large voltage gain and transconductance, high in-

put resistance, large output resistance
– excellent transconductance amplifier, reasonable volt-
age amplifier
• Common-drain stage:

– no voltage gain, but high input resistance and low

output resistance
– good voltage buffer
• Common-gate stage:

– no current gain, but low input resistance and high

output resistance
– good current buffer