PRELIMINARY TECHNICAL DATA

a Evaluation Board Documentation

ADE7757 Energy Metering IC
Preliminary Technical Data EVAL-ADE7757EB
FEATURES GENERAL DESCRIPTION
Single +5 V Power Supply The ADE7757 is a high accuracy energy measurement IC
Easy Connection of External Transducers via Screw with integrated oscillator. The part specifications surpass
Terminals the accuracy requirements as quoted in the IEC1036 stan-
Easy Modification of Signal Conditioning Components dard.
Using PCB Sockets
The ADE7757 supplies average real power information on the
Trim Pot for Analog Calibration of Meter Constant low frequency outputs F1 and F2. These logic outputs may be
Optically Isolated Output for Calibration/Test Purposes used to directly drive an electromechanical counter or interface
External Reference Option Available for Reference
to an MCU. The evaluation board provides screw connectors
Evaluation for easy connection to an external counter. The CF logic out-
put gives instantaneous real power information. This output is
intended to be used for calibration purposes. The evaluation
board allows this logic output to be connected to an LED or
optoisolator.
The ADE7757 evaluation board can easily be converted into
an energy meter by the addition of a local power supply and
the connection of the appropriate current sensor. A large
amount of prototype area is made available on the evaluation
board for this purpose.

FUNCTIONAL BLOCK DIAGRAM

AGND VCC VDD DGND

V2P F1
V2N CF F2
74HC08
ADE7757
V1N
V1P

VPLUS
H11L1 CFOUT

VMINUS
AD780
PROTOTYPE
AREA

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, USA
which may result from its use. No license is granted by implication or Tel: 781/329-4700 www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., June 2002
 PRELIMINARY TECHNICAL DATA
EVAL-ADE7757EB
ANALOG INPUTS (SK1 AND SK2) If Channel 2 is being used in a single-ended mode of op-
Voltage and current signals are connected at the screw termi- eration, the unused input of the pair should be connected
nals SK1 and SK2 respectively. All analog input signals are to analog ground (AGND) via an antialias filter. This is
filtered using the on-board antialias filters before being pre- shown in Figure 2 where V2N is connected to AGND
sented to the analog inputs of the ADE7757. Some analog using jumper JP8.
inputs offer additional signal conditioning, e.g., attenuation on JP7
the voltage channel. The default component values included TP5
R18
with the evaluation board are the recommended values to be SK2B V2N
used with ADE7757. The user can easily change these compo-
JP8 C19
nents, but this is not recommended unless the user is familiar
with sigma-delta converters as well as the criteria used for se-
lecting the analog input filters—see ADE7757 datasheet.
Voltage Input Figure 2. Unused Analog Inputs Connected to AGND
SK2 is a two-way connection block that can be directly All passive components (resistors and capacitors) which
connected to a high voltage source, e.g., 220 V rms. The make up the attenuation network and antialias filters may
resistor network R15 (trim pot), R19, R20, R21, and R22 be modified by the user. The components are mounted using
make up a very flexible attenuation and calibration net- PCB jack sockets for easy removal and replacement of
work—see schematic. The attenuation network is designed components.
such that the corner frequency (–3 dB frequency) of the
Current Input
network matches that of the RC (antialiasing) filters on
SK1 is a two-way connection block, which allows the
the other analog inputs. This is important, because if they
ADE7757 to be connected to a current sensor through one
do not match there will be large errors at low power fac-
differential input channel. In this example, we chose a shunt as
tors. Figure 1 shows how the attenuation network may be
the current sensor. Figure 3 shows a typical connection dia-
used with fixed resistors or the trim pot. The trim pot
gram for shunt connection.
allows the voltage signal on V2P to be scaled to calibrate
the frequency on CF to some given constant, e.g., 100
imp/kWhr. Some examples are given later.

JP5 B
SK1A
AGND ADE7757
R19 JP18 JP1
SK2A JP17
SK1B TP1
R21 R16
R20 V1N
A
R15 V2P JP2 C16
SHUNT JP3
JP6 TP2
C18 SK1C R17
R22 V1P
JP4 C17

a. Attenuation Using Trim Pot (R15)

B Figure 3. Typical Shunt Connection for Channel 1

JP5

R19 JP18 EVALUATION BOARD SETUP (ANALOG INPUTS)

SK2A JP17
R20
Figure 4 shows how the ADE7757 evaluation board can be set
R21
R15
A
V2P
up for a simple evaluation. Two signal generators are used to
provide the sinusoidal (ac) signals for Channel 1 and Channel
JP6 2. The user must have some way of phase locking the genera-
C18
R22
tors. Also if the ADE7757 performance-over-power factor is
being evaluated, two separate signal sources will be required.
The generators are shown connected in a single-ended configu-
ration. The grounded analog inputs of Channel 1 and Channel
b. Attenuation Using Fixed Resistors 2 (V1N and V2N) are connected to AGND via an antialias
Figure 1. Attenuation Network on Channel 2 filter. In Figure 4, analog input V2N is grounded via R21 and
R22. The capacitor C18 is connected in parallel.

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 PRELIMINARY TECHNICAL DATA
EVAL-ADE7757EB
JP5
OUTPUT FREQUENCY SELECTION
JP18 A
SK2A R19 ADE7757 provides up to four different output frequencies
JP17 on F1 and F2. The output frequency selection is made via
R20 P TP4
R21
R15 V2P the logic inputs S0 and S1—see ADE7757 datasheet. On
B
JP6 N
V2N the evaluation board these inputs are set by using jumpers
C18
50Hz
JP16 TP5 JP12 and JP13. The logic input SCF is set via jumper 11
R22
220V
JP7 (JP11). For a full explanation of the ADE7757 output
P frequency selection see the datasheet.
SK2B R18
N

JP8 INTERNAL CLOCK

C19 JP9
The ADE7757’s integrated oscillator serves as the clock
source to the chip. A precise 6.2 kΩ resistor with low
SK1A AGND JP1 tolerance and low drift is used to drive the internal oscilla-
R16
TP1 V1N tor.
50Hz SK1B

30mV JP2
C16
JP3

R17 TP2 V1P

SK1C
5.000V 5.000V
JP4 C17
SK3A SK3B

AGND VDD
Figure 4. Typical Connection for Analog Inputs NEUTRAL PHASE

SK5A
220V
LOGIC OUTPUTS SK1A
AGND
ADE7757 provides the active power information in the SHUNT SK5B
SK1B
form of an output frequency. The three frequency outputs V1N

are F1, F2 and CF. Consult the datasheet for more infor- 5A
2mV SK5C
mation on these outputs. The logic outputs F1 and F2 are V1P
SK1C
intended to be used to drive an impulse counter or stepper
motor. The outputs are buffered and available at the con-
nector SK6. A stepper motor may be directly connected JP5 B
here. The power supply for the buffer is +5V (SK4A) and R19 JP18
SK2A
may be connected to the ADE7757 supply using jumper R20
JP17

A
JP15, or to its own supply. SK2B R21
TP4 V2
R15
The logic output CF can be directly connected to an LED LOAD JP6 54.5mV
C18
using JP14 (Position B) or to an optically isolated output (Posi- R22
100
tion A). By closing Positions A and B, both options are se- JP1 = OPEN JP11 = 1 0.9776 Hz
imp/kWhr
JP2 = OPEN JP12 = 1
lected. The optically isolated output is available at connector JP3 = OPEN JP13 = 0
JP4 = OPEN
SK5. This isolated output is useful when the evaluation board JP5 = OPEN
JP14 = A,B
JP16 = P
FREQUENCY DISPLAY
is connected directly to a high voltage (e.g., 220 V residential). A JP6 = OPEN
JP7 = OPEN
JP17 = A
JP18 = CLOSED
typical connection diagram for this isolated output is shown in JP8 = CLOSED R21 = REMOVED
JP9 = N
Figure 5.
JP14

A B
R11

VPLUS SK5A
Figure 6. ADE7757 Evaluation Board as an Energy Meter
R12
+
R4 5V to 12V
U4
CFOUT R5 SK5B
COUNTER
EVALUATION BOARD SET UP AS AN ENERGY
H11L1
METER
VMINUS SK5C Figure 6 shows a wiring diagram that allows a simple
energy meter to be implemented using the ADE7757
evaluation board. The current transducer used in this ex-
Figure 5. Typical Connection for Opto Output ample is a 400 µΩ shunt. The meter is intended to be used
with a line voltage of 220 V and a maximum current of
25 A. The frequency outputs F1 and F2 can be used to
All logic outputs can be monitored via test points 6 to 8
drive a mechanical counter. These outputs will be cali-
(TP6 to TP8). These test points provide easy access for
brated to provide 100 imp/kWhr. The logic output CF
scope probes and meter probes.
has an output frequency that can be up to 2048 times higher

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 PRELIMINARY TECHNICAL DATA
EVAL-ADE7757EB
than the frequency on F1 and F2. This output can be used Table I.
for calibration purposes and is shown connected to a fre-
quency counter via the optoisolator in Figure 6. Jumper Option Description
At maximum current (25 A), the power seen by the meter JP1 Closed Closing this jumper will short resistor
will be 5.5 kW. This will produce a frequency of 0.153 Hz R16 and connect analog input V1N
on F1 and F2 when these outputs are calibrated to directly to SK1B. This has the effect
100imp/kWhr (100imp/hr = 0.02777 Hz, 0.02777 x 5.5 = of removing the antialias filter from
0.153 Hz). From Table V in the ADE7757 datasheet, the this input.
closest frequency to 0.153 Hz in the half-scale ac inputs Open Antialias filter in input V1N is en-
column is for F3, i.e., 0.18 Hz for a nominal internal oscilla- abled.
tor frequency of 466k Hz. Therefore F3 is selected by set-
JP2 Closed Analog input V1N is connected to
ting S1 = 1 and S0 = 0. The choice of CF frequencies in
analog ground (AGND) via the
this mode (see Table III in the ADE7757 datasheet) are
antialias filter. This jumper should be
32 times F1 and 16 times F1. For this example 32 times
closed if the Channel 1 is used in a
F1 is selected by setting SCF = 1.
single-ended mode.
Since the voltage on Channel 1 is fixed, the only possible Open When evaluating the ADE7757, Chan-
way of calibrating (adjusting) the output frequency in F1 nel 1 is best used in a differential
and F2 is by varying the voltage on Channel 2. This is mode and this jumper should be left
carried out by varying the attenuation of the line voltage open. An example is shown in Figure
using the trim pot. 3. In this example a shunt is used to
First we can calculate the voltage required in Channel 2 in sense the current. The shunt can be
order to calibrate the frequency on the logic outputs F1 and F2 referenced to the AGND of the board
to 100imp/kWhr. The ADE7757 datasheet gives the equation by using TP9 as shown.
which relates the voltage on Channel 1 and Channel 2 to the
JP3 Closed Closing this jumper will short resistor
output frequency on F1 and F2.
R17 and connect analog input V1P
515.84 × V1 × V2 × F1− 4 directly to SK1C. This has the effect
Freq = (1) of removing the antialias filter from
V 2 ref this input.
First a current is selected for calibration, 5 A for example. Open Antialias filter in input V1P is enabled.
This gives a Channel 1 voltage of 400 µΩ x 5 A = 2 mV JP4 Closed Analog input V1P is connected to ana-
rms. The on-chip or external reference of 2.5 V is selected log ground (AGND) via the antialias
using JP10. filter.
The output frequency at 5 A on F1 and F2 should be Open Normal operation.
(100imp/kWhr) x 1.1 kW = 0.03055 Hz, where (220 V x
JP5 Closed Closing this jumper will short resistors
5 A = 1.1 kW).
R19 and R20. The analog input V2P is
From Equation 1 the voltage on Channel 2 should be set connected directly to SK2A. This has
to 54.4 mV. The attenuation network as shown in Figure the effect of removing the antialias
1 is used to attenuate 220 V to 54.4 mV. R19 = 590 kΩ, filter/attenuation network from this
R20 = 200 kΩ, R22 = 100Ω and the trim pot R15 =100Ω. input. Note: if the board is being con-
However, since the meter is being calibrated at CF and nected to a high voltage, this jumper
CF is set to 32 times F1, the voltage on Channel 2 should must be left open.
be adjusted until CF = 32 x 0.03055 Hz = 0.9776 Hz is Open Antialias filter/attenuation network on
registered on the frequency counter. The counter should the input V2P is enabled.
be set up to display the average of ten frequency mea- JP6 Closed Analog input V2P is connected to ana-
surements on CF. This will remove any ripple due to the log ground (AGND) via the antialias
instantaneous power signal. See the ADE7757 datasheet filter/attenuation network. Note: SK2A
for more details. is also connected to AGND. Be care-
ful when connecting this input a high
voltage source.
JUMPER SELECTION Open Normal operation.
The ADE7757 evaluation board comes with several
jumper selections that allow the user to exercise all of JP7 Closed Closing this jumper will short resistor
the ADE7757 functionality. There are also some options R18 and connect analog input V2N
such as attenuation networks and optically isolated outputs directly to SK2B. This has the effect
that allow the ADE7757 to be evaluated under the same of removing the antialias filter/attenua-
conditions as the end application. Table I outlines all the tion network from this input.
jumper options and explains how they are used. Table I Open Antialias filter/attenuation network in
should be used in conjugation with Figure 7, which will input V2N is enabled.
make it easier to locate the jumper in question.
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 PRELIMINARY TECHNICAL DATA
EVAL-ADE7757EB
JP8 Closed Analog input V2N is connected to
analog ground (AGND) via the
antialias filter/attenuation network.
This option should be selected if
Channel 2 is used in a single-ended
mode.
Open V2N connected to SK2B for differential
operation.
JP9 N SK2B connected to V2N.
P SK2B connected to V2P.
JP10 Open ADE7757 internal (on-chip) reference
selected.
Closed External (AD780) reference selected.
JP11 1 SCF connected to VDD.
0 SCF connected to DGND.
JP12 1 S1 connected to VDD.
0 S1 connected to DGND.
JP13 1 S0 connected to VDD.
0 S0 connected to DGND.
JP14 A CF logic output connected to optically
isolated output at SK5.
B CF logic output connected to LED.
JP15 Closed VDD and +5V connected together.
Note: VDD is power supply for
ADE7757 IC (U1) and +5V is power
supply for buffer (U2)
JP16 N SK2A connected to V2N.
P SK2A connected to V2P.
JP17 A Trim pot R15 is connected to V2P or
V2N (depending on the position of
JP16)—see Figure 8. This allows the
output frequency to be scaled using the
voltage on V2P.
B When option B is selected, the jumper
JP18 should be left open. In this con-
figuration the attenuation for V2P is
provided via the fixed resistors R19,
R20, R21 and R22.
JP18 Open When open, the attenuation on V2P is
provided by fixed resistor as explained
above. Also see Figure 10.
Closed When closed, the trim pot becomes
part of the attenuation network. In this
mode of operation, the resistor R21
should be removed from its PCB jack
sockets and JP17B must be opened

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 PRELIMINARY TECHNICAL DATA
EVAL-ADE7757EB

JUMPER CLOSED
JUMPER OPEN

Figure 7. ADE7757 Evaluation Board Jumper Positions

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 PRELIMINARY TECHNICAL DATA
EVAL-ADE7757EB
Evaluation Board Bill of Material

Designator Value Description

R1, R2, R3, R4 1 kΩ, 5%, 1/4 W Resistor, No Special Requirements.
R5 100 Ω, 5%, 1/4 W Resistor, No Special Requirements.
R7, R8, R9 10 kΩ, 5%, 1/4 W Resistor, No Special Requirements.
R11, R12 820 Ω, 1%, 1/4 W Resistor, No Special Requirements.
R13, R14 20 Ω, 5%, 1/4 W Resistor, No Special Requirements.
R15 100 Ω, 10%, 1/2 W Trim Pot Resistor, 25 Turn.
BOURNS.
R16, R17, R18 200 Ω, 0.05%, 1/8 W ±15 ppm/°C Resistor, good tolerance, used as part of the analog filter
network. These resistors are not soldered, but are plugged into PCB
mount sockets for easy modification by the customer. Low drift
WELWYN RC6 Series, FARNELL Part No. 339-179.
R19 402 kΩ, 1%,1/4 W ±50 ppm/°C, FARNELL Part No. 336-660.
R20 200 kΩ, 1%, 1/4 W ±15 ppm/°C, FARNELL Part No. 341-094.
R21, R22 100 Ω, 0.1%, 1/4 W ±15 ppm/°C Resistor, Good Tolerance. Low Drift.
FARNELL Part No. 338-886.
C1 1 µF, 10% 16V Voltage reference decoupling capacitor.
C2, C3, C4 10 µF, 10% 16V Power supply decoupling capacitors, 20%, Philips CW20C 104,
FARNELL Part No. 643-579.
C5 6.2 kΩ, 0.1%, 1/4 W ±15 ppm/°C Resistor, Good Tolerance. Used to drive internal oscilla-
tor.
C7, C8, C9, C10, C11, 100 nF, 10% 100 V Power Supply Decoupling Capacitors, 10%, X7R type, AVX-
C12, C20 KYOCERNA, FARNELL Part No. 146-227.

C13, C14, C15 10 nF 10% 100V Philips CW15C 103 M, FARNELL Part No. 146-224.
C16, C17, C18, C19 0.15 µF, 10%, 50 V X7R Capacitor, Part of the Filter Network. These resistors are not
soldered, but are plugged into PCB mount sockets for easy modifica-
tion by the customer. SR15 series AVX-KYOCERNA, FARNELL
Part No. 108-948.
C21 N/A Capacitor placeholder for external reference compensation
SKT1 SOIC-nb socket Socket to hold ADE7757 chip. Loranger International Corp., 16 Gull
Wing Leaded, SOT-109A (so16), File NO. 3337161S
U1 ADE7757 Energy measurement IC by Analog Devices Inc. (see ADE7757
datasheet)
U2 74HC08 Quad CMOS AND gates.
U3 AD780 2.5 V Reference, Supplied by Analog Devices Inc.
U4 H11L1 Optical Isolator, by QT, FARNELL Part No. 326-896.
D1 LED Low Current, Red, FARNELL Part No. 637-087.
SK2, SK3, SK4, SK6 2-pin Screw Terminal 15 A, 2.5 mm Cable Screw Terminal Sockets. FARNELL Part No.
151-785. Length 10 mm, Pitch 5 mm, Pin diameter 1 mm.
SK1, SK5 3-pin Screw Terminal 15 A, 2.5 mm Cable Screw Terminal Sockets. FARNELL Part No.
151-786. Length 15 mm, Pitch 5 mm, Pin diameter 1 mm.

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 PRELIMINARY TECHNICAL DATA
EVAL-ADE7757EB
SK3B VDD SK4A SK4B
SK3A

C9 C4
+5V
1 DGND
AGND VDD C3 C10

VDD
U2 14
JP5 U1
JP18 74HC08
R19
B ADE7757 TP8 R9 1 R13
3
SK2A JP17 2 F1 16 2 SK6A
R20 P TP4 C11
R21 V2P
V2P TP7 R8 4
R14
R15 6 C12
A F2 15 5 SK6B
JP6 N V2N
C18 3
V2N
TP6 12 B
V2 JP16 R7 11 R11 TO IMPULSE
TP5 CF 13 COUNTER /
R22 14 A
STEPPER MOTOR
JP7 9 D1
8
P 10 JP14
R18
SK2B N
R12 VPLUS
JP8 7 SK5A
C19 JP9 1 6 U4 R4
REVP 12 4
JP1 R5
SK1A SK5B
CFOUT
TP1 4 C20
R16
SK1B V1N 2 5 H11L1
C5
JP2 RCLKIN SK5C
C16 11 VMINUS
V1 JP3

R17
TP2 5
SK1C V1P
JP4 C17

S0 10
TP3 S1 9 C15
VDD
7 REFIN/OUT SCF 8 C14
C1 C7
C13
2
C2 C8 JP10
U3 6
AD780 AGND DGND
R2
3 R1 R3
6 13
C21 4 VDD
1 1 1
0 0 0

JP11 JP12 JP13

PCB MOUNT SOCKETS
TEST POINT

AGND DGND VDD +5V

TP9 TP10

JP15

Figure 8. Evaluation Board Schematic

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 PRELIMINARY TECHNICAL DATA
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Figure 9. PCB Layout–Component Side

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Figure 10. PCB Layout–Solder Side

–10– REV. PrF

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Figure 11. PCB Layout–Component Placement

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