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ML610Q793

The document describes the ML610Q793, an 8-bit microcontroller for sensor control applications. It has an 8-bit CPU, 64KB flash memory, 4KB RAM, multiple sensor interfaces, and draws 0.93mA of current during normal operation. It is designed to separate sensors from the main application processor in smartphones to reduce overall power consumption.

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0% found this document useful (0 votes)
49 views24 pages

ML610Q793

The document describes the ML610Q793, an 8-bit microcontroller for sensor control applications. It has an 8-bit CPU, 64KB flash memory, 4KB RAM, multiple sensor interfaces, and draws 0.93mA of current during normal operation. It is designed to separate sensors from the main application processor in smartphones to reduce overall power consumption.

Uploaded by

hiteshmediaa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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You are on page 1/ 24

FEDL610Q793-01

Issue Date: 6/12/2013

ML610Q793
8-bit Microcontroller for Sensor Control

■ General Description

The ML610Q793 is a high-performance 8-bit low power microcontroller optimized for sensor hub, that integrates LAPIS
Semiconductor’s original high-performance 8-bit CPU core with a 16-bit multiplier/divider co-processor, 64 kByte flash
memory, 4 kByte RAM, multiple interfaces for various sensors and host interfaces with 8kByte logging RAM in small footprint
package. The ML610Q793 is an ideal sensor hub microcontroller for smart phone to separate various sensors off from its
application processor and control them effectively for reducing total system power consumption.

■ Features

● CPU
—8-bit RISC CPU (CPU name: uX-U8/100)
—16-bit length instruction system
—Minimum instruction execution time
30.5 us (32.768 kHz system clock) 0.25 us (4.096 MHz system clock)
—Built-in coprocessor for multiplication, division, and multiply-accumulate operations
Multiplication (Input: 16-bit x 16-bit, Output: 32-bit)
Division (Input: 32-bit/16-bit, Output: 32-bit)
Multiply-accumulate (Input: 16-bit x 16-bit + 32-bit, Output: 32-bit)

● Internal memory
—64-kByte Flash ROM (32-kWord x 16-bit)
—4-kByte SRAM (4-kWord x 8-bit)

● Interrupt controller
—Non-maskable interrupt: 1 source
—Maskable interrupt: 29 sources
Number of internal sources: 13 (Timer: 6, ADC: 1, SPI: 1, I2C: 1, HOSTIF: 1, Arithmetic
circuit: 1, UART: 1, SIO: 1)
Number of external sources: 16

● Timer
—8-bit auto-reload timer x 6ch
—Watchdog timer (WDT) x 1ch

● Serial interface
—SPI interface with master function x 1ch
—I2C interface with master function x 1ch
—UART interface (two-wire, full duplex communication) x 1ch
—SIO interface (two-wire, half-duplex communication) x 1ch

● Host interface
—Serial interface with slave function (SPI/I2C selectable) x 1ch
—Outputs a host processor interrupt x 1ch (secondary function of general-purpose I/O port)
—8-kByte RAM for logging

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● General-purpose I/O port


—8-bit input/output port x 2ch
—5-bit input/output port x 1ch

● A/D converter
—12-bit successive approximation type A/D converter x 3ch

● Arithmetic circuit
—Root operation (Input: 18 bit, Output: 19 bit)

● Power consumption control function


—CPU operation mode
Supports high frequency operation and low frequency operation
—HALT mode Supports the HALT mode for stopping CPU only
Returning for HALT mode : 77usec
● Input clock
—32.768 kHz (External clock input)

● Power supply voltage


—Analog section:(using ADC) 2.5V to 3.6V
(not using ADC) 1.7V to 1.9V
—Digital I/O section: 1.7V to 1.9V
—Digital core section: 1.7V to 1.9V

● Power consumption (Normal state)


—High-speed operation (4.096MHz): 0.93mA
—HALT Mode: 0.6uA

● Operating frequency
—High-speed clock: 4.096 MHz
—Low-speed clock: 32.768kHz

● Operating temperature
—Ambient temperature: -30°C to +85°C (FLASH erase/programming -30°C to +60°C)

● Package
—48-pin WL-CSP (S-UFLGA48-3.06x2.96-0.40-W)

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■ Block Diagram

DVDD
DGND
AVDD CPU
AGND (uX-U8/100) Coprocessor
VDDL
I2C_SPISEL
*1
PA0_EXI00 , PA1_EXI01 ,
*1 Program HOST IF
*1 *1 Memory
SDO_SDA_S
PA2_EXI02 , PA3_EXI03 , (RAM8kB) SDI_SA1_S
*1 *1 (Flash) 64kB
PA4_EXI04 , PA5_EXI05 , (SPI / I2C) SCS_SA0_S
*1 *1
PA6_EXI06 , PA7_EXI07 , RAM 4kB SCLK_SCL_S
*1 *1 *2
PB0_EXI08 , PB1_EXI09 , PC0_INT_S
*1 *1
PB2_EXI10 , PB3_EXI11 ,
*1 *1 Interrupt SPI (Master) SDO_M
PB4_EXI12 , PB5_EXI13 ,
*1 *1 Controller SDI_M
PB6_EXI14 , PB7_EXI15
SCS_M
*1 *1 SCLK_M
PA0_EXI00 , PA1_EXI01 , General-purpose
I2C (Master)
*1 *1
PA2_EXI02 , PA3_EXI03 , I/O Port SDA_M
*1 *1
PA4_EXI04 , PA5_EXI05 , 8-bit 2ch SCL_M
*1 *1 5-bit 1ch
PA6_EXI06 , PA7_EXI07 , Successive ADC_IN0
*1 *1
PB0_EXI08 , PB1_EXI09 , ADC ADC_IN1
*1 *1
PB2_EXI10 , PB3_EXI11 , Timer
*1 *1 8-bit 6ch 12-bit 3ch ADC_IN2
PB4_EXI12 , PB5_EXI13 , VREF
*1 *1
PB6_EXI14 , PB7_EXI15 Asynchronous *3
*2
PC0_INT_S , PC1, Arithmetic Circuit PC2_RXD0
*3 *3 SIO 1ch PC3_TXD0
*3
PC2_RXD0 , PC3_TXD0 ,
PC4 WDT
UART 1ch PB6_EXI14
*3
*3
XT PB7_EXI15
Clock
PB3_EXI11 Controller

RESET_N Reset On Chip


Controller ICE
*
VDDX 4 PLL Test VPP
*
XTN 4 TEST1
TEST0

*1 Shared by the interrupt pins and the general-purpose I/O port


*2 Shared by the interrupt output pin of the host interface and the general-purpose I/O port
*3 Shared by the UART/Asynchronous SIO transmit/receive pins and the general-purpose I/O port
*4 Leave this pin open in ML610Q793

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■ Pin Configuration (Top View)

DGND DVDD SDA_M PA2_EXI02 PA5_EXI05 PB0_EXI08 PB3_EXI11 7

AVDD VDDX VDDL PA1_EXI01 PA4_EXI04 PA7_EXI07 PB2_EXI10 6

ADC_IN1 AGND SCL_M PA0_EXI00 PA3_EXI03 PB1_EXI09 VPP 5

ADC_IN2 VREF ADC_IN0 PC1 PA6_EXI06 PB7_EXI15 PC2_RXD0 4

XTN TEST0 PC4 SCS_SA0_S SDI_M PB4_EXI12 3

XT TEST1 SDO_SDA_S SDI_SA1_S SCS_M PB6_EXI14 PC3_TXD0 2

I2C_SPISEL RESET_N SCLK_SCL_S SDO_M SCLK_M PC0_INT_S PB5_EXI13 1

G F E D C B A

48-pin WL-CSP Package(S-UFLGA48-3.06x2.96-0.40-W)


(Bottom View)

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■ List of Pins

PIN Symbol Input/output Polarity Function


No.
F5 AGND — — Analog GND
G6 AVDD — — Analog power supply
G7 DGND — — Digital IO/core GND
F7 DVDD — — Digital I/O power supply
E6 VDDL — — Digital core power supply
F6 VDDX — — Pins unused
G1 I2C_SPISEL I — Selects the interface with the host
I2C interface when I2C_SPISEL = 1
SPI interface when I2C_SPISEL = 0
E2 SDO_SDA_S IO — SDA of I2C slave interface when I2C_SPISEL = 1
O — SDO of SPI slave interface when I2C_SPISEL = 0
(This signal status is Hi-Z except for output data. )
D2 SDI_SA1_S I — I2C slave address when I2C_SPISEL = 1
I — SDI of SPI slave interface when I2C_SPISEL = 0
D3 SCS_SA0_S I — I2C slave address when I2C_SPISEL = 1
I Positive SCS of SPI slave interface when I2C_SPISEL = 0
E1 SCLK_SCL_S I — SCL of I2C slave interface when I2C_SPISEL = 1
I — SCLK of SPI slave interface when I2C_SPISEL = 0
E7 SDA_M IO — SDA of I2C master interface
E5 SCL_M O — SCL of I2C master interface
D1 SDO_M O — SDO of SPI master interface
C3 SDI_M I — SDI of SPI master interface
C2 SCS_M O Positive SCS of SPI master interface
C1 SCLK_M O — SCLK of SPI master interface
G4 ADC_IN2 — — Successive ADC input 2
G5 ADC_IN1 — — Successive ADC input 1
E4 ADC_IN0 — — Successive ADC input 0
F4 VREF — — Successive ADC reference voltage input
B1 PC0_INT_S IO — General-purpose input/output port for the primary function
O Negative Interrupt output for host interface for the secondary function
D4 PC1 IO — General-purpose input/output port
A4 PC2_RXD0 IO — General-purpose input/output port for the primary function
I — Asynchronous SIO receive data for the secondary function
A2 PC3_TXD0 IO — General-purpose input/output port for the primary function
O — Asynchronous SIO transmit data for the secondary function

E3 PC4 IO — General-purpose input/output port


D5 PA0_EXI00 IO — General-purpose input/output port/external interrupt input
D6 PA1_EXI01 IO — General-purpose input/output port/external interrupt input
D7 PA2_EXI02 IO — General-purpose input/output port/external interrupt input
C5 PA3_EXI03 IO — General-purpose input/output port/external interrupt input
C6 PA4_EXI04 IO — General-purpose input/output port/external interrupt input
C7 PA5_EXI05 IO — General-purpose input/output port/external interrupt input
C4 PA6_EXI06 IO — General-purpose input/output port/external interrupt input
B6 PA7_EXI07 IO — General-purpose input/output port/external interrupt input
B7 PB0_EXI08 IO — General-purpose input/output port/external interrupt input
B5 PB1_EXI09 IO — General-purpose input/output port/external interrupt input
A6 PB2_EXI10 IO — General-purpose input/output port/external interrupt input

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A7 PB3_EXI11 IO — General-purpose input/output port/external interrupt input


O — 32.768kHz clock for output
A3 PB4_EXI12 IO — General-purpose input/output port/external interrupt input
A1 PB5_EXI13 IO — General-purpose input/output port/external interrupt input
B2 PB6_EXI14 IO — General-purpose input/output port/external interrupt input for
the primary function
I — UART receive data for the secondary function
B4 PB7_EXI15 IO — General-purpose input/output port/external interrupt input for
the primary function
O — UART transmit data for the secondary function
F1 RESET_N I Negative System reset input
G2 XT I — External clock input
G3 XTN IO — Unused pin(Leave this pin open)
A5 VPP I — FLASH test pin
F2 TEST1 I — Test pin
F3 TEST0 I — Test pin/remap pin (for firmware update)

■ Termination of Unused Pins

Pin Recommended pin termination


VPP Leave this pin open.
VDDX Leave this pin open.
XTN Leave this pin open.
TEST0 Leave this pin open.
TEST1 Leave this pin open.
RESET_N Leave this pin as open, or connect a pull-up registor.
PA0∼PA7 Leave this pin open (refer to Note).
PB0∼PB7 Leave this pin open (refer to Note).
PC0∼PC4 Leave this pin open (refer to Note).
ADC_IN0∼2 Leave this pin open.
VREF Leave this pin open.
SDA_M, SCL_M Leave this pin open.
SDO_M, SCS_M, SCLK_M Leave this pin open.
SDI_M Connect this pin to a pull-down registor.
SCLK_SCL_S, SCS_SA0_S, Apply low level to I2C_SPISEL pin, and connect
SDI_SA1_S, SDO_SDA_S these pins to a pull-down registor.

[Note:]
The supply current flow may become excessively large if the pins of unused input ports and input/output
ports are left open with the high impedance input setting. It is recommended to set those ports to input
mode with a pull-down resistor, input mode with a pull-up resistor, or output mode by setting the port
control register.

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■ Host Interface

The ML610Q793 controls various sensors via the host interface. The host interface provides selectable I2C/SPI interface and
interrupt signals to the host processor, and includes an 8-bit and a 16-bit register address space and an 8-kByte FIFO.

● Register Map

Address Initial
Name Symbol (Byte) R/W Size
Write Read Value
00H 80H Configuration register CFG R/W 8 00H
01H 81H Sensor interrupt mask register 0 INTMSK0 R/W 8 FFH
02H 82H Sensor interrupt mask register 1 INTMSK1 R/W 8 FFH
03H~ 83H~
reserved — — — —
07H 87H
08H 88H Operation status register STATUS R/— 8 FEH
09H 89H Sensor interrupt request register 0 INTREQ0 R/— 8 00H
0AH 8AH Sensor interrupt request register 1 INTREQ1 R/— 8 00H
0BH 8BH Error code register 0 ERROR0 R/— 8 00H
0CH 8CH Error code register 1 ERROR1 R/— 8 00H
0DH~ 8DH~
reserved — — — —
0FH 8FH
10H 90H Command register 0 CMD0 R/W 8 00H
11H 91H Command register 1 CMD1 R/W 8 00H
12H 92H Parameter register 0 PRM0 R/W 8 00H
13H 93H Parameter register 1 PRM1 R/W 8 00H
14H 94H Parameter register 2 PRM2 R/W 8 00H
15H 95H Parameter register 3 PRM3 R/W 8 00H
16H 96H Parameter register 4 PRM4 R/W 8 00H
17H 97H Parameter register 5 PRM5 R/W 8 00H
18H 98H Parameter register 6 PRM6 R/W 8 00H
19H 99H Parameter register 7 PRM7 R/W 8 00H
1AH 9AH Parameter register 8 PRM8 R/W 8 00H
1BH 9BH Parameter register 9 PRM9 R/W 8 00H
1CH 9CH Parameter register A PRMA R/W 8 00H
1DH 9DH Parameter register B PRMB R/W 8 00H
1EH 9EH Parameter register C PRMC R/W 8 00H
1FH 9FH Command entry register ENT R/W 8 00H
20H A0H Result register 00 RSLT00 R/— 8/16 00H
21H A1H Result register 01 RSLT01 R/— 8 00H
22H A2H Result register 02 RSLT02 R/— 8/16 00H
23H A3H Result register 03 RSLT03 R/— 8 00H
24H A4H Result register 04 RSLT04 R/— 8/16 00H
25H A5H Result register 05 RSLT05 R/— 8 00H
26H A6H Result register 06 RSLT06 R/— 8/16 00H
27H A7H Result register 07 RSLT07 R/— 8 00H
28H A8H Result register 08 RSLT08 R/— 8/16 00H
29H A9H Result register 09 RSLT09 R/— 8 00H
2AH AAH Result register 0A RSLT0A R/— 8/16 00H
2BH ABH Result register 0B RSLT0B R/— 8 00H
2CH ACH Result register 0C RSLT0C R/— 8/16 00H
2DH ADH Result register 0D RSLT0D R/— 8 00H

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2EH AEH Result register 0E RSLT0E R/— 8/16 00H


2FH AFH Result register 0F RSLT0F R/— 8 00H
30H B0H Result register 10 RSLT10 R/— 8/16 00H
31H B1H Result register 11 RSLT11 R/— 8 00H
32H B2H Result register 12 RSLT12 R/— 8/16 00H
33H B3H Result register 13 RSLT13 R/— 8 00H
34H B4H Result register 14 RSLT14 R/— 8/16 00H
35H B5H Result register 15 RSLT15 R/— 8 00H
36H B6H Result register 16 RSLT16 R/— 8/16 00H
37H B7H Result register 17 RSLT17 R/— 8 00H
38H B8H Result register 18 RSLT18 R/— 8/16 00H
39H B9H Result register 19 RSLT19 R/— 8 00H
3AH BAH Result register 1A RSLT1A R/— 8/16 00H
3BH BBH Result register 1B RSLT1B R/— 8 00H
3CH BCH Result register 1C RSLT1C R/— 8/16 00H
3DH BDH Result register 1D RSLT1D R/— 8 00H
3EH BEH Result register 1E RSLT1E R/— 8/16 00H
3FH BFH Result register 1F RSLT1F R/— 8 00H
40H C0H Result register 20 RSLT20 R/W 8 Undefined
41H~ C1H~
reserved — — — —
7FH FFH

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● Configuration Register CFG


7 6 5 4 3 2 1 0
CFG REGMD SPI3M — — — INTLVL — —

R/W R/W R/W R/W R/W R/W R/W R/W R/W


Initial
0 0 0 0 0 0 0 0
Value

REGMD:
Sets the access mode of the serial interface (I2C/SPI). Set to "0" to increment the internal address by 1 each time a
1-byte data is transmitted/received. Set to "1" to fix the address to the same address.
The Result register 20 is not intended. In addition, there is prohibition that set to “0” to this register and read
successively for Result register “IF” to “20”.

SPI3M:
If the host interface is set "SPI" (apply low level to I2C_SPISEL pin), sets the interface type(3-wires or 4-wires) of
SPI communication. Set to "0" for 4-wires mode, or set to "1" for 3-wires mode.

INTLVL:
Sets the interrupt level. Set to "0" for pulse output, or set to "1" for level output.

● Sensor Interrupt Mask Register INTMSK0, INTMSK1


7 6 5 4 3 2 1 0
INTMSK0 MSK0[7] MSK0[6] MSK0[5] MSK0[4] MSK0[3] MSK0[2] MSK0[1] MSK0[0]

R/W R/W R/W R/W R/W R/W R/W R/W R/W


Initial
1 1 1 1 1 1 1 1
Value

7 6 5 4 3 2 1 0
INTMSK1 MSK1[7] MSK1[6] MSK1[5] MSK1[4] MSK1[3] MSK1[2] MSK1[1] MSK1[0]

R/W R/W R/W R/W R/W R/W R/W R/W R/W


Initial
1 1 1 1 1 1 1 1
Value

MSK0[7:0]:
Masks the interrupt notification to the host processor by the sensor interrupt request register (INTREQ0). Set to "0"
to mask the interrupt notification by REQ0[n] bit of INTREQ0.Set to "1" not to mask the interrupt notification.

MSK1[7:0]:
Masks the interrupt notification to the host processor by the sensor interrupt request register (INTREQ1). Set to "0"
to mask the interrupt notification by REQ1[n] bit of INTREQ1.Set to "1" not to mask the interrupt notification.

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● Operation Status Register STATUS


7 6 5 4 3 2 1 0
STATUS ST[7] ST[6] ST[5] ST[4] ST[3] ST[2] ST[1] ST[0]

R/W R/— R/— R/— R/— R/— R/— R/— R/—


Initial
0 0 0 0 0 0 0 0
Value

ST[n](N=7 to 0):
Indicates the status of sensor measurement.
Read successively for STAUS, INTREO0, INTERO1 by address increments mode.

● Sensor Interrupt Request Register INTREQn (n = 0, 1)


7 6 5 4 3 2 1 0
INTREQn REQn [7] REQn [6] REQn [5] REQn [4] REQn [3] REQn [2] REQn [1] REQn [0]

R/W R/— R/— R/— R/— R/— R/— R/— R/—


Initial
0 0 0 0 0 0 0 0
Value

REQn[7:0]:
Indicates the interrupt source to the host processor. Each bit of this register is cleared by being read by the host
processor.
Read successively for INTREO0, INTERO1 by address increments mode.

* In competition clear by the reading from a host processor and write from the CPU occurs, Writing from the CPU
may not be reflected in this register.
Therefore controls so that access of the CPU and access of the host processor do not compete.
In cases the competition is non avoidable, refer to [ML610Q793 SDK software manuals].
Provide Software avoiding competition for Software Development Kit [SDK].

● Error Code Register ERROR n (n = 0, 1)


7 6 5 4 3 2 1 0
ERRORn ERn [7] ERn [6] ERn [5] ERn [4] ERn [3] ERn [2] ERn [1] ERn [0]

R/W R/— R/— R/— R/— R/— R/— R/— R/—


Initial
0 0 0 0 0 0 0 0
Value

REQ n[7:0]:
Indicates the ERROR Code of host processor.

● Command Register CMDn (n = 0, 1)


7 6 5 4 3 2 1 0
CMDn CMDn[7] CMDn[6] CMDn[5] CMDn[4] CMDn[3] CMDn[2] CMDn[1] CMDn[0]

R/W R/W R/W R/W R/W R/W R/W R/W R/W


Initial
0 0 0 0 0 0 0 0
Value

CMDn[7:0]:
This register sets the measurement conditions of sensors and inputs commands such as measurement start/stop.

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● Parameter Register PRMn (n = 0 to 9, A to C)


7 6 5 4 3 2 1 0
PRMn PRMn[7] PRMn [6] PRMn [5] PRMn [4] PRMn [3] PRMn [2] PRMn [1] PRMn [0]

R/W R/W R/W R/W R/W R/W R/W R/W R/W


Initial
0 0 0 0 0 0 0 0
Value

PRMn[7:0]:
This register sets the parameters of commands.

● Command Entry Register ENT


7 6 5 4 3 2 1 0
ENT — — — — — — — ENT

R/W R/W R/W R/W R/W R/W R/W R/W R/W


Initial
0 0 0 0 0 0 0 0
Value

ENT:
After a command is set, set this bit "1" to notify the CPU of the command. When the CPU receives the command,
this bit is cleared.

● Result Register RSLT n (n = 00 to 1F)


7 6 5 4 3 2 1 0
RSLTn RSLTn[7] RSLTn [6] RSLTn [5] RSLTn [4] RSLTn [3] RSLTn [2] RSLTn [1] RSLTn [0]

R/W R/— R/— R/— R/— R/— R/— R/— R/—


Initial
0 0 0 0 0 0 0 0
Value

RSLTn[7:0]:
This register indicates the command processing result.

● Result Register RSLT20


7 6 5 4 3 2 1 0
RSLT20 RSLT20[7] RSLT20 [6] RSLT20 [5] RSLT20 [4] RSLT20 [3] RSLT20 [2] RSLT20 [1] RSLT20 [0]

R/W R/— R/— R/— R/— R/— R/— R/— R/—


Initial
X X X X X X X X
Value

RSLT20[7:0]:
This register indicates the command processing result. As this register has a FIFO structure, read data with the given
size.
This register can be written from a host processor only when using firmware update software which SDK offers.
For details. please refer to a [ML610Q793 SDK firm updates software manuals].

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■ Absolute Maximum Ratings

(DGND=AGND=0V)
Parameter Symbol Condition Rating Unit
Power supply voltage VDD
Ta = 25°C −0.3 to +4.6
(Digital I/O)
Power supply voltage VDDL
Ta = 25°C −0.3 to +3.6
(Digital CORE)
Power supply voltage VDDA V
Ta = 25°C −0.3 to +4.6
(Analog)
Input voltage VIN Ta = 25°C −0.3 to VDD+0.3
Output current IOUT Ta = 25°C −12 to +11 mA
Power dissipation PD Ta = 25°C 0.9 W
Storage temperature TSTG ⎯ −55 to +150 °C

■ Recommended Operation Conditions

(DGND=AGND=0V)
Parameter Symbol Condition Min. Typ. Max. Unit
Power supply voltage
VDD ⎯ 1.7 1.8 1.9
(Digital I/O)
Power supply voltage
VDDL ⎯ 1.7 1.8 1.9
(Digital CORE)
V
Power supply voltage UsesADC 2.5 3.3 3.6
VDDA
(Analog) Unuses ADC 1.7 1.8 1.9
Analog reference voltage VREF ⎯ 2.2 ⎯ VDDA
Auto transient response
ΔVout ⎯ ⎯ ⎯ ± 19 mV
(VDDL)
Clock input frequency fCLK ⎯ 32.441 32.768 33.095 kHz

normal operation -30 25 +85


Ambient temperature Ta FLASH erase/write °C
-30 25 +60
operation

■ Operating Conditions of Flash Memory

(DGND=AGND=0V)
Parameter Symbol Condition Range Unit
read operation -30 to +85
Operating temperature TOP °C
erase/write operation -30 to +60
Power supply voltage VDDL ⎯ 1.7 to 1.9 V
Rewrite count CEP ⎯ 100 cycles
VDDL pin external
CL0 ⎯ 10 years
capacitance

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■ Electrical Characteristics

● DC Characteristics (1/2)
(DVDD = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C)
Parameter Symbol Condition Min. Typ. Max. Unit
Power consumption CPU stop
IDD2 - 0.6 16.5 µA
(HALT) *1,*2
Power consumption CPU 32 kHz operation
IDD3 - 7.5 25 µA
(Low-speed operation) *1,*2
Power consumption CPU 4 MHz operation
IDD4-1 - 0.93 1.3 mA
(High-speed operation 1) *2
Power consumption
IDD4-2 CPU 4 MHz operation - 1.5 2.3 mA
(High-speed operation 2)
*1 The low-speed clock operates, and only the high-speed clock (PLL) stops
*2 The successive approximation type ADC stops

● DC Characteristics (2/2)

(DVDD = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C)


Parameter Symbol Condition Min. Typ. Max. Unit
Output voltage 1 VOH1 - - - -
V
(SDA_M,SCL_M) VOL1 IOL1 = +0.5mA - - 0.5
Output leakage 1 IOOH1 - - - -
VOL=0V µA
(SDA_M,SCL_M) IOOL1 -1 - -
(in high-impedance state)
DVDD
Output voltage 2 VOH2 IOH=-0.5mA - -
- 0.5
V
(Excluding SDA_M and
VOL2 IOH= 0.5mA - - 0.5
SCL_M)
VOH= VDD
Output leakage 2 IOOH2 - - 1
(in high-impedance state)
µA
(Excluding SDA_M and VOL= 0V
IOOL2 -1 - -
SCL_M) (in high-impedance state)
Input current 1 IIH1 VIH1=DVDD 0 - 1
µA
(RESET_N, TEST1) IIL1 VIL1 = VSS -600 -300 -2
Input current 2 IIH2 VIH1=DVDD 2 300 600
µA
(TEST0) IIL2 VIL1 = VSS -1 - 0
IIH3 VIH1 = DVDD(pull-down) 2 30 200
Input current 3
IIL3 VIL1 = VSS(pull-up) -200 -30 -2
VIH1=0V
IIH3Z - - 1 µA
(Excluding RESET_N, (in high-impedance state)
TEST1, and TEST0) VIL1=DVDD
IIL3Z -1 - -
(in high-impedance state)
DVDD
VIH1 - - -
× 0.7
Input voltage V
DVDD
VIL1 - - -
× 0.3

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zAC Characteristics (Clock)


(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
Input clock frequency fCLK ¯- 32.441 32.768 33.095 kHz
Input clock
TCLKH ¯- 9.2 15.259 21.3 µs
High pulse width
Input clock
TCLKL ¯- 9.2 15.259 21.3 µs
Low pulse width
No variable power supply 3.99 4.096 4.20 MHz
System clock frequency fSYSCLK
VRPL ≤ 19mV 3.89 4.096 4.30 MHz

TCLK*
*TCLK = 1/fCLK
TCLKH TCLKL

XT

(Clock input pin)

TSYSCLK* *TSYSCLK = 1/fSYSCLK

SYSCLK
(Inside system clock)

zAC Characteristics (Reset)

(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
Reset pulse width PRST ¯ 200 ¯ ¯
Reset noise elimination µs
PNRST ¯ ¯ ¯ 0.3
pulse width
Power on reset generated
TPOR ¯ ¯ ¯ 10 ms
power rise time

RESET_N VIL1 VIL1 VIL1 VIL1

PRST
PNRST

RESET_N pin reset Reset noise elimination

0.9×VDDA

AVDD
0.1×VDDA
TPOR
Power-on reset

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zAC Characteristics (External Interrupt)

(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
Interrupt: Enabled (MIE = 1),
External interrupt disable
TNUL CPU: NOP operation 76.8 ¯ 106.8 μs
period
System clock: 32.768kHz

PA0 to PA7
PB0 to PB7
(Rising-edge interrupt mode) tNUL

PA0 to PA7
PB0 to PB7

(Falling-edge interrupt mode) tonal

PA0 to PA7
PB0 to PB7
(Both-edge interrupt mode) tNUL

zAC Characteristics (UART/SIO)


(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
1
Transmit baud rate tTBRT ¯ ¯ BRT* ¯ s
1 1
BRT* 1 BRT*
Receive baud rate tRBRT ¯ BRT* s
-3% +3%
*1: UART:Baud rate period set with the UART baud rate dividing register (LSB/MSB).
SIO:Baud rate period set with the UART0 baud rate register (UA0BRTL,H) and the UART0 mode register 0 (UA0MOD0).

tTBRT

UART:PB7_EXI15
SIO:PC3_TXD0

tRBRT

UART:PB6_EXI14
SIO:PC2_RXD0

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● AC Characteristics (Host Interface: I2C Slave Interface)

(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
SCL clock frequency fSCL ⎯ 0 ⎯ 400 kHz
SCL hold time
(start/restart tHD:STA ⎯ 0.6 ⎯ ⎯ μs
condition)
SCL ”L” level time tLOW ⎯ 1.3 ⎯ ⎯ μs
SCL ”H” level time tHIGH ⎯ 0.6 ⎯ ⎯ μs
SCL setup time
tSU:STA ⎯ 0.6 ⎯ ⎯ μs
(restart condition)
SDA hold time tHD:DAT ⎯ 0 ⎯ ⎯ ns
SDA setup time tSU:DAT ⎯ 0.1 ⎯ ⎯ μs
SDA setup time
tSU:STO ⎯ 0.6 ⎯ ⎯ μs
(stop condition)
Bus-free time tBUF ⎯ 1.3 ⎯ ⎯ μs

Start Restart Stop


condition condition condition

SDA
(SDO_SDA_S)

SCL
(SCLK_SCL_S)
tBUF
tSU:STO
tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT

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● AC Characteristics (Host Interface: SPI Slave Interface)

(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.

SCLK input cycle tSCYC ¯ 0.5 ¯ ¯ μs

SCLK input pulse width tSW ¯ 0.2 ¯ ¯ μs

tCS1 ¯ 80 ¯ ¯ ns
SCS setup time
tCS2 ¯ 80 ¯ ¯ ns

SCS hold time tCH ¯ 80 ¯ ¯ ns

SCS input pulse width tCW ¯ 90 ¯ ¯ ns

SDO output delay time tSD ¯ ¯ ¯ 240 ns

CLKI input setup time tSS ¯ 80 ¯ ¯ ns

SDI input hold time tSH ¯ 80 ¯ ¯ ns

tSCYC tSW tSW


SCLK
(SCLK_SCLK_S)
tCS1
SCLK
(SCLK_SCLK_S)

tCS2 tSS tSH

SDI
(SDI_SA1_S)
tSD
SDO
(SDO_SDA_S)
tCH2
SCS
(SCS_SA0_S)
tCH1
tCW

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● AC Characteristics (SPI Master Interface)


(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
1
SCLK_M output cycle tSCYC ¯ ¯ SCLK* ¯ s
1 1 1
SCLK* SCLK* SCLK*
SCLK_M output pulse width tSW ¯ s
×0.4 ×0.5 ×0.6

SDO_M output delay time tSD ¯ ¯ ¯ 240 ns

SDI_M input setup time tSS ¯ 240 ¯ ¯ ns

SDI_M input hold time tSH ¯ 80 ¯ ¯ ns


1
* : Internal clock cycle selected by the interface register

tSCYC

tSW tSW

SCLK_M

tSD tSD

SDO_M

tSS tSH

SDI_M

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● AC Characteristics (I2C Master Interface: Standard Mode 100 kHz)


(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
SCL clock frequency fSCL ⎯ 0 ⎯ 100 kHz
SCL hold time
(start/restart tHD:STA ⎯ 4.0 ⎯ ⎯ μs
condition)
SCL ”L” level time tLOW ⎯ 4.7 ⎯ ⎯ μs
SCL ”H” level time tHIGH ⎯ 4.0 ⎯ ⎯ μs
SCL setup time
tSU:STA ⎯ 4.7 ⎯ ⎯ μs
(restart condition)
SDA hold time tHD:DAT ⎯ 0 ⎯ ⎯ μs
SDA setup time tSU:DAT ⎯ 0.25 ⎯ ⎯ μs
SDA setup time
tSU:STO ⎯ 4.0 ⎯ ⎯ μs
(stop condition)
Bus-free time tBUF ⎯ 4.7 ⎯ ⎯ μs

● AC Characteristics (I2C Master Interface: Fast Mode 400 kHz)


(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
SCL_M clock frequency fSCL ⎯ 0 ⎯ 400 kHz
SCL_M hold time
(start/restart tHD:STA ⎯ 0.6 ⎯ ⎯ μs
condition)
SCL_M ”L” level time tLOW ⎯ 1.3 ⎯ ⎯ μs
SCL_M ”H” level time tHIGH ⎯ 0.6 ⎯ ⎯ μs
SCL_M setup time
tSU:STA ⎯ 0.6 ⎯ ⎯ μs
(restart condition)
SDA_M hold time tHD:DAT ⎯ 0 ⎯ ⎯ μs
SDA_M setup time tSU:DAT ⎯ 0.1 ⎯ ⎯ μs
SDA_M setup time
tSU:STO ⎯ 0.6 ⎯ ⎯ μs
(stop condition)
Bus-free time tBUF ⎯ 1.3 ⎯ ⎯ μs

Start Restart Stop


condition condition condition

SDA_M

SCL_M

tBUF
tSU:STO
tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT

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● Electrical Characteristics of Successive Approximation Type A/D Converter


(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
Resolution n ¯ ¯ ¯ 12 bit
Integral non-linearity error 2.7V≤VREF≤3.6V -4 ¯ +4
INL
margin 2.2V≤VREF≤2.7V -6 ¯ +6
Differential non-linearity 2.7V≤VREF≤3.6V -3 ¯ +3
DNL LSB
error margin 2.2V≤VREF≤2.7V -5 ¯ +5
Zero-scale error VOFF ¯ -6 ¯ +6
Full-scale error FSE ¯ -6 ¯ +6
Reference voltage VREF ¯ 2.2 ¯ VDDA V

Conversion time tCONV At high-speed operation ¯ 112 ¯ φ/CH

φ: Cycle of high-speed clock

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■ Power-On / Power-Off Procedures

Keep the power-on and power-off procedures of DVDD, VDDL and AVDD supply at the same time.
And DVDD, VDDL supply indetical voltage.
The timing restrictions are shown as following.

2sec 5 msec or less


or more 0.9×VDD
DVDD
30mV or less 0.1×VDD
VDDL

5 msec or less
2sec 0.9×VDDA
AVDD or more
30mV or less 0.1×VDDA

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■ Package Dimensions

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number,
package code and desired mounting conditions (reflow method, temperature and times).

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■ Revision History

Issue Date Page


Document No. Previous New Description
Edition Edition

PEDL610Q793-00 Oct. 20,2012 ― ― Preliminary first edition issued

FEDL610Q793-01 Jun. 12, 2013 ― ― First edition issued

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NOTES

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Ltd.
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