ML610Q793
ML610Q793
ML610Q793
8-bit Microcontroller for Sensor Control
■ General Description
The ML610Q793 is a high-performance 8-bit low power microcontroller optimized for sensor hub, that integrates LAPIS
Semiconductor’s original high-performance 8-bit CPU core with a 16-bit multiplier/divider co-processor, 64 kByte flash
memory, 4 kByte RAM, multiple interfaces for various sensors and host interfaces with 8kByte logging RAM in small footprint
package. The ML610Q793 is an ideal sensor hub microcontroller for smart phone to separate various sensors off from its
application processor and control them effectively for reducing total system power consumption.
■ Features
● CPU
—8-bit RISC CPU (CPU name: uX-U8/100)
—16-bit length instruction system
—Minimum instruction execution time
30.5 us (32.768 kHz system clock) 0.25 us (4.096 MHz system clock)
—Built-in coprocessor for multiplication, division, and multiply-accumulate operations
Multiplication (Input: 16-bit x 16-bit, Output: 32-bit)
Division (Input: 32-bit/16-bit, Output: 32-bit)
Multiply-accumulate (Input: 16-bit x 16-bit + 32-bit, Output: 32-bit)
● Internal memory
—64-kByte Flash ROM (32-kWord x 16-bit)
—4-kByte SRAM (4-kWord x 8-bit)
● Interrupt controller
—Non-maskable interrupt: 1 source
—Maskable interrupt: 29 sources
Number of internal sources: 13 (Timer: 6, ADC: 1, SPI: 1, I2C: 1, HOSTIF: 1, Arithmetic
circuit: 1, UART: 1, SIO: 1)
Number of external sources: 16
● Timer
—8-bit auto-reload timer x 6ch
—Watchdog timer (WDT) x 1ch
● Serial interface
—SPI interface with master function x 1ch
—I2C interface with master function x 1ch
—UART interface (two-wire, full duplex communication) x 1ch
—SIO interface (two-wire, half-duplex communication) x 1ch
● Host interface
—Serial interface with slave function (SPI/I2C selectable) x 1ch
—Outputs a host processor interrupt x 1ch (secondary function of general-purpose I/O port)
—8-kByte RAM for logging
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● A/D converter
—12-bit successive approximation type A/D converter x 3ch
● Arithmetic circuit
—Root operation (Input: 18 bit, Output: 19 bit)
● Operating frequency
—High-speed clock: 4.096 MHz
—Low-speed clock: 32.768kHz
● Operating temperature
—Ambient temperature: -30°C to +85°C (FLASH erase/programming -30°C to +60°C)
● Package
—48-pin WL-CSP (S-UFLGA48-3.06x2.96-0.40-W)
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■ Block Diagram
DVDD
DGND
AVDD CPU
AGND (uX-U8/100) Coprocessor
VDDL
I2C_SPISEL
*1
PA0_EXI00 , PA1_EXI01 ,
*1 Program HOST IF
*1 *1 Memory
SDO_SDA_S
PA2_EXI02 , PA3_EXI03 , (RAM8kB) SDI_SA1_S
*1 *1 (Flash) 64kB
PA4_EXI04 , PA5_EXI05 , (SPI / I2C) SCS_SA0_S
*1 *1
PA6_EXI06 , PA7_EXI07 , RAM 4kB SCLK_SCL_S
*1 *1 *2
PB0_EXI08 , PB1_EXI09 , PC0_INT_S
*1 *1
PB2_EXI10 , PB3_EXI11 ,
*1 *1 Interrupt SPI (Master) SDO_M
PB4_EXI12 , PB5_EXI13 ,
*1 *1 Controller SDI_M
PB6_EXI14 , PB7_EXI15
SCS_M
*1 *1 SCLK_M
PA0_EXI00 , PA1_EXI01 , General-purpose
I2C (Master)
*1 *1
PA2_EXI02 , PA3_EXI03 , I/O Port SDA_M
*1 *1
PA4_EXI04 , PA5_EXI05 , 8-bit 2ch SCL_M
*1 *1 5-bit 1ch
PA6_EXI06 , PA7_EXI07 , Successive ADC_IN0
*1 *1
PB0_EXI08 , PB1_EXI09 , ADC ADC_IN1
*1 *1
PB2_EXI10 , PB3_EXI11 , Timer
*1 *1 8-bit 6ch 12-bit 3ch ADC_IN2
PB4_EXI12 , PB5_EXI13 , VREF
*1 *1
PB6_EXI14 , PB7_EXI15 Asynchronous *3
*2
PC0_INT_S , PC1, Arithmetic Circuit PC2_RXD0
*3 *3 SIO 1ch PC3_TXD0
*3
PC2_RXD0 , PC3_TXD0 ,
PC4 WDT
UART 1ch PB6_EXI14
*3
*3
XT PB7_EXI15
Clock
PB3_EXI11 Controller
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G F E D C B A
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■ List of Pins
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[Note:]
The supply current flow may become excessively large if the pins of unused input ports and input/output
ports are left open with the high impedance input setting. It is recommended to set those ports to input
mode with a pull-down resistor, input mode with a pull-up resistor, or output mode by setting the port
control register.
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■ Host Interface
The ML610Q793 controls various sensors via the host interface. The host interface provides selectable I2C/SPI interface and
interrupt signals to the host processor, and includes an 8-bit and a 16-bit register address space and an 8-kByte FIFO.
● Register Map
Address Initial
Name Symbol (Byte) R/W Size
Write Read Value
00H 80H Configuration register CFG R/W 8 00H
01H 81H Sensor interrupt mask register 0 INTMSK0 R/W 8 FFH
02H 82H Sensor interrupt mask register 1 INTMSK1 R/W 8 FFH
03H~ 83H~
reserved — — — —
07H 87H
08H 88H Operation status register STATUS R/— 8 FEH
09H 89H Sensor interrupt request register 0 INTREQ0 R/— 8 00H
0AH 8AH Sensor interrupt request register 1 INTREQ1 R/— 8 00H
0BH 8BH Error code register 0 ERROR0 R/— 8 00H
0CH 8CH Error code register 1 ERROR1 R/— 8 00H
0DH~ 8DH~
reserved — — — —
0FH 8FH
10H 90H Command register 0 CMD0 R/W 8 00H
11H 91H Command register 1 CMD1 R/W 8 00H
12H 92H Parameter register 0 PRM0 R/W 8 00H
13H 93H Parameter register 1 PRM1 R/W 8 00H
14H 94H Parameter register 2 PRM2 R/W 8 00H
15H 95H Parameter register 3 PRM3 R/W 8 00H
16H 96H Parameter register 4 PRM4 R/W 8 00H
17H 97H Parameter register 5 PRM5 R/W 8 00H
18H 98H Parameter register 6 PRM6 R/W 8 00H
19H 99H Parameter register 7 PRM7 R/W 8 00H
1AH 9AH Parameter register 8 PRM8 R/W 8 00H
1BH 9BH Parameter register 9 PRM9 R/W 8 00H
1CH 9CH Parameter register A PRMA R/W 8 00H
1DH 9DH Parameter register B PRMB R/W 8 00H
1EH 9EH Parameter register C PRMC R/W 8 00H
1FH 9FH Command entry register ENT R/W 8 00H
20H A0H Result register 00 RSLT00 R/— 8/16 00H
21H A1H Result register 01 RSLT01 R/— 8 00H
22H A2H Result register 02 RSLT02 R/— 8/16 00H
23H A3H Result register 03 RSLT03 R/— 8 00H
24H A4H Result register 04 RSLT04 R/— 8/16 00H
25H A5H Result register 05 RSLT05 R/— 8 00H
26H A6H Result register 06 RSLT06 R/— 8/16 00H
27H A7H Result register 07 RSLT07 R/— 8 00H
28H A8H Result register 08 RSLT08 R/— 8/16 00H
29H A9H Result register 09 RSLT09 R/— 8 00H
2AH AAH Result register 0A RSLT0A R/— 8/16 00H
2BH ABH Result register 0B RSLT0B R/— 8 00H
2CH ACH Result register 0C RSLT0C R/— 8/16 00H
2DH ADH Result register 0D RSLT0D R/— 8 00H
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REGMD:
Sets the access mode of the serial interface (I2C/SPI). Set to "0" to increment the internal address by 1 each time a
1-byte data is transmitted/received. Set to "1" to fix the address to the same address.
The Result register 20 is not intended. In addition, there is prohibition that set to “0” to this register and read
successively for Result register “IF” to “20”.
SPI3M:
If the host interface is set "SPI" (apply low level to I2C_SPISEL pin), sets the interface type(3-wires or 4-wires) of
SPI communication. Set to "0" for 4-wires mode, or set to "1" for 3-wires mode.
INTLVL:
Sets the interrupt level. Set to "0" for pulse output, or set to "1" for level output.
7 6 5 4 3 2 1 0
INTMSK1 MSK1[7] MSK1[6] MSK1[5] MSK1[4] MSK1[3] MSK1[2] MSK1[1] MSK1[0]
MSK0[7:0]:
Masks the interrupt notification to the host processor by the sensor interrupt request register (INTREQ0). Set to "0"
to mask the interrupt notification by REQ0[n] bit of INTREQ0.Set to "1" not to mask the interrupt notification.
MSK1[7:0]:
Masks the interrupt notification to the host processor by the sensor interrupt request register (INTREQ1). Set to "0"
to mask the interrupt notification by REQ1[n] bit of INTREQ1.Set to "1" not to mask the interrupt notification.
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ST[n](N=7 to 0):
Indicates the status of sensor measurement.
Read successively for STAUS, INTREO0, INTERO1 by address increments mode.
REQn[7:0]:
Indicates the interrupt source to the host processor. Each bit of this register is cleared by being read by the host
processor.
Read successively for INTREO0, INTERO1 by address increments mode.
* In competition clear by the reading from a host processor and write from the CPU occurs, Writing from the CPU
may not be reflected in this register.
Therefore controls so that access of the CPU and access of the host processor do not compete.
In cases the competition is non avoidable, refer to [ML610Q793 SDK software manuals].
Provide Software avoiding competition for Software Development Kit [SDK].
REQ n[7:0]:
Indicates the ERROR Code of host processor.
CMDn[7:0]:
This register sets the measurement conditions of sensors and inputs commands such as measurement start/stop.
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PRMn[7:0]:
This register sets the parameters of commands.
ENT:
After a command is set, set this bit "1" to notify the CPU of the command. When the CPU receives the command,
this bit is cleared.
RSLTn[7:0]:
This register indicates the command processing result.
RSLT20[7:0]:
This register indicates the command processing result. As this register has a FIFO structure, read data with the given
size.
This register can be written from a host processor only when using firmware update software which SDK offers.
For details. please refer to a [ML610Q793 SDK firm updates software manuals].
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(DGND=AGND=0V)
Parameter Symbol Condition Rating Unit
Power supply voltage VDD
Ta = 25°C −0.3 to +4.6
(Digital I/O)
Power supply voltage VDDL
Ta = 25°C −0.3 to +3.6
(Digital CORE)
Power supply voltage VDDA V
Ta = 25°C −0.3 to +4.6
(Analog)
Input voltage VIN Ta = 25°C −0.3 to VDD+0.3
Output current IOUT Ta = 25°C −12 to +11 mA
Power dissipation PD Ta = 25°C 0.9 W
Storage temperature TSTG ⎯ −55 to +150 °C
(DGND=AGND=0V)
Parameter Symbol Condition Min. Typ. Max. Unit
Power supply voltage
VDD ⎯ 1.7 1.8 1.9
(Digital I/O)
Power supply voltage
VDDL ⎯ 1.7 1.8 1.9
(Digital CORE)
V
Power supply voltage UsesADC 2.5 3.3 3.6
VDDA
(Analog) Unuses ADC 1.7 1.8 1.9
Analog reference voltage VREF ⎯ 2.2 ⎯ VDDA
Auto transient response
ΔVout ⎯ ⎯ ⎯ ± 19 mV
(VDDL)
Clock input frequency fCLK ⎯ 32.441 32.768 33.095 kHz
(DGND=AGND=0V)
Parameter Symbol Condition Range Unit
read operation -30 to +85
Operating temperature TOP °C
erase/write operation -30 to +60
Power supply voltage VDDL ⎯ 1.7 to 1.9 V
Rewrite count CEP ⎯ 100 cycles
VDDL pin external
CL0 ⎯ 10 years
capacitance
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■ Electrical Characteristics
● DC Characteristics (1/2)
(DVDD = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C)
Parameter Symbol Condition Min. Typ. Max. Unit
Power consumption CPU stop
IDD2 - 0.6 16.5 µA
(HALT) *1,*2
Power consumption CPU 32 kHz operation
IDD3 - 7.5 25 µA
(Low-speed operation) *1,*2
Power consumption CPU 4 MHz operation
IDD4-1 - 0.93 1.3 mA
(High-speed operation 1) *2
Power consumption
IDD4-2 CPU 4 MHz operation - 1.5 2.3 mA
(High-speed operation 2)
*1 The low-speed clock operates, and only the high-speed clock (PLL) stops
*2 The successive approximation type ADC stops
● DC Characteristics (2/2)
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TCLK*
*TCLK = 1/fCLK
TCLKH TCLKL
XT
SYSCLK
(Inside system clock)
(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
Reset pulse width PRST ¯ 200 ¯ ¯
Reset noise elimination µs
PNRST ¯ ¯ ¯ 0.3
pulse width
Power on reset generated
TPOR ¯ ¯ ¯ 10 ms
power rise time
PRST
PNRST
0.9×VDDA
AVDD
0.1×VDDA
TPOR
Power-on reset
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(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
Interrupt: Enabled (MIE = 1),
External interrupt disable
TNUL CPU: NOP operation 76.8 ¯ 106.8 μs
period
System clock: 32.768kHz
PA0 to PA7
PB0 to PB7
(Rising-edge interrupt mode) tNUL
PA0 to PA7
PB0 to PB7
PA0 to PA7
PB0 to PB7
(Both-edge interrupt mode) tNUL
tTBRT
UART:PB7_EXI15
SIO:PC3_TXD0
tRBRT
UART:PB6_EXI14
SIO:PC2_RXD0
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(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
SCL clock frequency fSCL ⎯ 0 ⎯ 400 kHz
SCL hold time
(start/restart tHD:STA ⎯ 0.6 ⎯ ⎯ μs
condition)
SCL ”L” level time tLOW ⎯ 1.3 ⎯ ⎯ μs
SCL ”H” level time tHIGH ⎯ 0.6 ⎯ ⎯ μs
SCL setup time
tSU:STA ⎯ 0.6 ⎯ ⎯ μs
(restart condition)
SDA hold time tHD:DAT ⎯ 0 ⎯ ⎯ ns
SDA setup time tSU:DAT ⎯ 0.1 ⎯ ⎯ μs
SDA setup time
tSU:STO ⎯ 0.6 ⎯ ⎯ μs
(stop condition)
Bus-free time tBUF ⎯ 1.3 ⎯ ⎯ μs
SDA
(SDO_SDA_S)
SCL
(SCLK_SCL_S)
tBUF
tSU:STO
tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT
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(Unless otherwise specified, DVDD = AVDD = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C)
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
tCS1 ¯ 80 ¯ ¯ ns
SCS setup time
tCS2 ¯ 80 ¯ ¯ ns
SDI
(SDI_SA1_S)
tSD
SDO
(SDO_SDA_S)
tCH2
SCS
(SCS_SA0_S)
tCH1
tCW
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tSCYC
tSW tSW
SCLK_M
tSD tSD
SDO_M
tSS tSH
SDI_M
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SDA_M
SCL_M
tBUF
tSU:STO
tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT
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Keep the power-on and power-off procedures of DVDD, VDDL and AVDD supply at the same time.
And DVDD, VDDL supply indetical voltage.
The timing restrictions are shown as following.
5 msec or less
2sec 0.9×VDDA
AVDD or more
30mV or less 0.1×VDDA
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■ Package Dimensions
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number,
package code and desired mounting conditions (reflow method, temperature and times).
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■ Revision History
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NOTES
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