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UNIT-2 Prsoyyanrenoble abe. Logic De Devices(PL0's)
@rn @ pa OEP OFPGA
Cplen gales
Defimitor : Proparnnmable Lag ic devia Ig aq om TC
Gugigs mB ( “Aad! gobs “PYlouedl an
OH OR Ales, Thad ow. cll a
— OPA ea @crin @ePGA @P-Rorg He |
| x USe: TE IS Ad to oaple onto emultipl, logical
Tunes § 9 Gasle Chip.
@® Prog ;0mmable Lo Logic Array CPLA CPLA)
OF ene Trpat buffer, Pepiavomable
AND ow 50 Praarmable ‘or’ ay.
od outph é be ie
| ® Cousider Hoo block dliagian § PLA -
| “ThE ps inside The ye —baftes
OS wall af Cem pleonnded ae
@TD impPemmend deny, Logica Somdios ,
|
WR i Novel Sorry
We have.
to Get the SALT Ai date
vate K-wnape ue it tons | AN Tmplemroat tke Jollewing fumdiovi Wiles Pea Pen
GUD) $3,569): a E249 |
BE SEN Kemap fee, Keamap fy Po
ON Caveat
x i
Ete
E- Re rama | a eC
| gtipr : Timpeomactatcos | Thowtifis ot le y
AX Hach Mom—e peatoct) Paroduct .
| We have C34 d= 6 Parduck Ferma ,
te eee
Wwe need bo Deparment 2 fumdbonis (F,48)
BH we mead two ‘or’ eres iy OR-Aarrang
fips Logic dia Son0 P50 Yowrmobk Atiay Logic fayar is liga Ai (ferren
“Grovn PAL, Te hed Pero yornmalte ANO yhuk Pined
‘ \
OR Arn
Peaiilit, 4) P60 Gorrownins iS LU,
uwlbtre
Ea Nov ae
‘og
Com porrd
_ Tris cmost widly Used PLO, but tke
Te Foose, Move
to PLA:
get JS defirmined by The vo Lumtlagn
Kovdus, emagi mnt) Prvoduck Lerent , .
En@! Tompermact He fellas fumdbiains Wong IL
== g xy+ x2
stip) y- Detiymine Ha M0 "AND aay for Coch
Sumubins - Since F, 33 Navins ‘2 Pospeluact
Terms , BS we Neel
& B- xy! +
= 6 ANC gyalay Chad),
ye + x2.
2 (max ~Predack X 2 (fuidiors)
* PAL
hig Yoo } —{|— —
YS PSP
Zoos *
vu wy
et TUT iy
AD Hewsces pity PLA & PAL PLA & PAL
4 os
© pha sto —[Peey | —| Pera | 4 p(
PAL” ; Mes Pegg 1 | Fined. Fined. e/p%
@ PLA H PAL!
Te tans fy Pang, Lepie Aran: ® Porg- Pow Wey logic
@: Tt Yous? Poy AND & Pevpy Loadey. l It
Berio Com be “Wed fo Doad tke Configurat-
vies def dE FPGA.
Qthey we “alto used” iy Sonalll detigen appli
Cotto, Like acttress Pecodinny. A
TISEAU TAT Brekd| (PawersannenebLae |]
Oo, TO . i)
To tephra Vayu Gr owks Comore Wak 2p, anciuba)
Wwe we eC IAememable clap va Sorgen ‘Magic
Copacila, is wed. De iS Kmowo ob. POA. ,
® PAS One quite , effort frseon CPLDX, thi
do mi Guta “ARPA OR’ Pond, ~
@rPaas Pmvids “loaic Pooks” oe ili
vom ple med chien a ae Dogical Plan cbions 3.6 PROGRAMMABLE LoGic Devices
oO Logic block [Interconnection switches
W/O block
x
3
3
3
g
W/O block
(a) General structure of an FPGA @ Consida te Avchitidin oF FPGAS:
L % Blom TU
SS
!
' ' cembincommedicoy Wired,
reer? oh
Al F7o Block i lel
xy (Ree “Moin Se bounces :
ia eae. Rrocks Bx “Blocks
iW) Tati Gomedinn uirees & Suto.
BD) Logic Blocks: Back logic bleck insbiele. 4 PGA
GoSears Small M0 -c-. Vols & eo ne mes Commrnoulay
UM Logic Block iS Look 4p Tote CLUT).
Ce et Table Cowdteucs Storage Cells iain Wee
40 iempleemint Somott Logic Sumeios .
@ The imbiCormubion Wives aig Onganised Os rete
ond Wor pat Feb” homme belwery Logie,
Nolecks & Te blockts hare eubn Bah,
Contacs Pioyrasmnenolle Switclwy thee! alle ogi ¢
Pocky TO be Comenectad iy Tren LIYE * QT blocks Critans ep Gaga pins rou
Whe FPA Cons Communicates ui Ihe entlorero
/ Pevphtrol avis,
» Apthicabions FFAS 2 @ FRGAS Are weal on
both, covred and wirloss’ dante Cowannumni ctiav $.
@ Br is wy do Nekwer! ns Colubior's aml adnan
Glandonds Wi-MAX, SG/GH_ Cormrnumic
Uy for
EPan Chips
(anes doko Porees)
| @T™ Ne wmedicod Pidld,
| Aiag notice ond cron itibiiny Pungosed
o use tho RRRPACER evppli clon.
: Konc@ -_
Look UP Fable ?- Logic block Lrdiche > FPGA
15 calle os ook up fable CLOT) , vali. Cowtait
— Stremge Cells to tPlemot Aogic francis +
2 in LUT 32 Doran) the tral olin yhomn aac Trubs
fab fow a-mpub Lut, b Lo ple mont 2-4 r
XNOR ge PHafior - ‘
Sol ‘
BE COHAN FF (ax) HTK tH Hoot
Bere %2)
(c) Storage cell contents in the LUT
Figure 3.36 A two-input lookup table (LUT). S|
5
se
SSS S( Sis s
x: 3
input LUT,
A three-
Figure 3.37 ’ FPGA
CPLO
OL Yawk fos Complex
Paoyxamenable Logie Pevice.
@tt is ow Te that lulps to
temple mad chigitel Sys
OTk Prrvidis kus Logic
DEGDULCES,
route BK made up a foaser
| logic blocks
OTS Cut ef tive
© CPLOS Cenguane Dass Phosen
@PLDs one Suitable. ors
| SmMoll to onediuw Scale
| OPPlicalrewy,
@ceips Cowsist,
ONS ahi
VHSIe — Hardware -
ODL i uted to Rycwtl
“AND KOR”,
Y lepic
FPQA
@rt Kouncs Ay Field
Pacgtamemabl. Gale aa
(@Tris ow Te clesig maf +o
be Comfiqued 'ay a user (ov)
(Bi Prrvides Mose ve
Oven dt + logic SeyCbrceg
@ FPan’s ox Made apd
Kony Aogic blocks,
(FDIS expensive them CAD
© Fras Gn
Ru
D FRaas One Suitable fox
Mose Cem
Plex epplicatas
© LWhre “8, FG ay as
as Look-up fates .
Peseviptay Lamguase CUNO)
heim “tran a.
Some amove
X mayan tv be exceed © a Com pte,
;@vyrpr is Hficialt,
ond 7 Seppo teal
by oll
SGitsd hordtons ,
eudlos coef 4 Teer
Veudays Which Q@YHPL Cale fy Holt Ad
tne alums, stat the Code by includ.
Neodled libeadits Awol mecesohyy Prekages, buy
hin © yee! class,
Ithvoy Eee s
Wwe |eee. sH_ logic Wey, alls
Outi Hoadde 44
Pont- ¢ dfn’
i a,b 2 IN Std_llegie = \ Vp & oy
| P
| Sum, Gong ¢ OUT Sel logic) « Poot
| awd Hoaddey 5
| i
| oseliteclure data flocs Hoadder jf
begin
Sum <= a tor b;
Carty <= A awd b»
ena dofaftors 5 ENNOL Cob for Fut ndder
—~
Viboony, TEE 5
USE TecE .Std-logic - Ay ally
Fu adder hes 2 impula
enti Funke 1S omd 2 owtpids
Pak F321. 2N SAAiCs =
| Sur ,Casng + OOF SHL_Logie me ee |__
| umd €_Adders a LY covery
© orschitedding Adtaflew E_nddes is
, Sam =O y G2
| bey
| Sum <= F FET 'Y a 2, cooing « og eae
© Cuesy & Komd gon Yordz ey Zooks;
amd dat Glows 5
Ma & (A ond (ret 6)
Yy & (Awd Bs i
BW Code OF dutou aaa atu Recoder hos 2 Vy
| Gooroy, Tee nee
| Woe TEE. MACs CUGHals ; ¥,
| emi by Deceder 2404 iS ] zhey [Te
G—] be TN
Post C A, BI LN Skh_losic > Yy
| Yo, Yo Vy 2 OUT Sd logic s Yo= Ae! 2 NG,
| tad Dewoder oto 5 Yb =A, YY, = AB,
ovsclii keabuse dates Flow % Devod _atou t&
| agin
Yo <= (Emote a) and (mt @)) 5
| YS Comer a) ant 87 iy
|
|
tnd aledaflou s , Verilog HPL Vesibg Coun ple and Seplarticatiof langue
Govdleped fy Simulation amd Verifications fp digit diet
CAD too cre used to Laplerment The vesilog cole Imto
hor duanre iaplemutation of ee Cis tut, ,
Edverilog Coote fr HeiPedlin | @ Vesilog code. fy Pulled
module Pelfadd Ca she, 69s module. Lutlodd 55%, 9
inp a, bs ee 192;
Output Silys ams S, .
aAWiem S2 athe M§m se ayy -
"gS ; O$41§ m C= NIGH) fa
akign Cy aks and , D
end module vaale
~~ -
QVerileg code fy 2x1 Muy
a e
smndule mua} (Ty F, SDE
IMnpot Tia, gs
Out Pale fi 7
Bin fa cep
ne ” ft JKT) } G42),
,
~~_
Overilog code faux Mos
modude Fe A,
mi ge ea
inet Tyr ;
and es” UT 2,Tz, %,3,¢
a £2 (54 94T,) |
te (Guage a) (éskes ay )|
© Vewilog Conde. fore EXOR pole; (&& ae ,
amodule Eaorget (x4, f)
et a (GNewilog Code fox 2 yp AND
Fj re
oe medal Amds(2,9,2, £)
oO t= A ys impak 4,549 «
end medile_ ok Pah 49
es 7
in f 2 ak 462; @ Vesitog Coke fr 2 te decor
Weieg OR fe 2B te
moolwle «dec _2_y (EX-,21, Py,D,0, 0.) ey
Uapat EN, 25,0, 5
Outpat Do, DOLD)
Asigay D, = (ENE Me, LHe) 5
Osign De ( ENX we, ee) 5
Sim D,- (EN& €,8 wo,)¢
SY 4 Dye CEN & Co &e,) 5
end omedule ;
Cot hy tod treed.
ea Yo
| We M19 (Co, £25.25 % )y safe
ne
Input €5,@, 22 C35 =
oubpak %o, Ss
v1
: 3
avn = (e | E05
; oO
amg Y= Ce, )e)s ae
emcl nodule ; Yor ertea 7 Y= eee
Q@vesilog Code Fors Binput NoR @verislog Code fer = ve
SS ene XNoOR
oe mi £y anodule 2-xW0R( HY, 25 &)5
oudpuk fs inpak 43,8 5
: , output 4.
assign fe v(xlalz); assign f= ~(a*9*2)
eck onoclule +
/
:
i
Y
