Verilog code for Seven segment display:
//Verilog module
module BCD to segment7(BCD,SEG)
//Declare inputs outputs variables.
input [3:0]BCD;
output reg[6:0]SEG;
//Converting BCD digit into 7 segment format
always@(BCD)
begin
case(BCD)
4'b0000: SEG =7'b0000001;
4'b0001: SEG =7'b1001111;
4'b0010: SEG =7'b0010010;
4'b0011: SEG =7'b0000110;
4'b0100: SEG =7'b1001100;
4'b0101: SEG =7'b0100100;
4'b0110: SEG =7'b0100000;
4'b0111: SEG =7'b0001111;
4'b1000: SEG =7'b0000000;
4'b1001: SEG =7'b0000100;
endcase
end
endmodule
Unknown
module usensor (trig, echo, distance, reset, clk);
output trig, distance;
input clk, echo, reset;
reg dist_counter=0;
reg counter=0;
always @ (posedge clk)
begin
if (reset)
begin
counter<=0;
distance<=0;
end
else
begin
counter <= counter + 1;
if (counter <= 500) //10usec to initialize
sensor
begin
echo<=0;
trig<=1; // trig is set high
end
if (echo) // sensing 5v at echo pin so
echo pin is high
begin
dist_counter <= dist_counter + 1;
trig <=0;
end
if (counter<= 1900000) // maximum time of sensing
any object is 38ms
begin
echo<=0;
trig<=0;
end
if (counter<= 5000000) // wait 1 sec to begin again
begin
counter<=0;
distance <=0;
end
end
end
assign distance = (dist_counter ** (-1)) * 340; // speed of sound in
air
endmodule
Verilog for generating pulse
module 8 pulse generation
// 40kHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from Key-0, high when Key-0 is pressed
input cclk,
genvar i;
generate
for (i = 0; i < 8; i=i+1) begin: pwm_gen_loop
pwm #(.CTR_LEN(3)) pwm (
.rst(rst),
.clk(clk),
.compare(i),
.pwm(led[i])
);
end
endgenerate
endmodule
module 8 pulse 40kHz(clk, pulse, clkout);
input clk; // 40kHz clock input
input pulse;
output clkout;
reg cnt, temp;
initial begin cnt = 0;
temp = 0;
end
always @(posedge clk)
if(pulse && !cnt) begin
cnt <= ~cnt; // button (active low)
temp <= 1;
end
else if(!pulse) begin
cnt <= 0;
end
else
temp <= 0;
assign clkout = temp|clk;
endmodule
Ex:
initial clk = 0;
always #10 clk = ~clk;
If you want stream of pulses, use always block.
Ex:
always begin
clk = 0;
#10;
clk = 1;
#10;
end
OR
always
begin
clk = 0;
forever #10 clk = ~clk;
end
module distance counter(distance,pulse);
output reg signed[6:0] distance;
input [1:0] pulse;
reg [6:0] reference_distance;
always @(*)
begin
reference_distance = (pulse[ 0]^1'b1) + (pulse[ 1]^1'b1)
if (pulse[0] == 1'b1) distance = reference_distance ;
else distance = 6'd62 - reference_distance ;
end
endmodule
Lab 5
// Code your design here
/*
Module name:- pwn_4bit
Descirption:- 4 bit pwm
Dependencies:- adder_4bitv, ripple_count-up_4bit, ripple_count_up_6bit
Author:- Alfred Li
Company: HKUspace
Date/Rev:- 21/08/2022, Rev0.1
Project:- Electronic System Lab 2
*/
module pwm_4bit(ratio, clk, nclr,pwm_out);
output pem_out;
input [3:0]ratio;
input clk, nclr;
//Define inernal wires
wire [3:0] count;
wire [5:0] clk_div;
ripple_count_up-6bit u3 (.clk(clk), .nclr(nclr),.q(clk_div)); //
divdes clock by max of 64 (2^6)
ripple_count_up-4bit u1 (.clk(clk_div[2]), .nclr(nclr), . q(count));
adder_4bit u2
(.a(ratio),.b(count),.cin(1'b0),.sum(),.cout(pwm_out));
endmodule // terminate module.
