William Stallings Computer Organization and Architecture 8th Edition

Chapter 3 Top Level View of Computer Function and Interconnection

Program Concept
Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals

What is a program?
A sequence of steps For each step, an arithmetic or logical operation is done For each operation, a different set of control signals is needed

Function of Control Unit

For each operation a unique code is provided
e.g. ADD, MOVE

A hardware segment accepts the code and issues the control signals We have a computer!

Components
The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit Data and instructions need to get into the system and results out
Input/output

Temporary storage of code and results is needed

Main memory

Computer Components: Top Level View

Thumb drive Printer Hard disk CD-ROM Network adapter Graphic card Etc..

Instruction Cycle
Two steps:
Fetch Execute

Fetch Cycle
Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC
Unless told otherwise

Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions

Execute Cycle
Processor-memory
data transfer between CPU and main memory

Processor I/O
Data transfer between CPU and I/O module

Data processing
Some arithmetic or logical operation on data

Control
Alteration of sequence of operations e.g. jump

Combination of above

Let look at the example of how CPU run the program

The CPU structures

0001 10100100000

The CPU structures

0001 0011 0111 ?

110100100000 101010001010 101111010100 .. .. .. ..

? The easier way for us to write instruction is to use hexadecimal 1940 3370

Example of Program Execution

1940 5941 2941

Instruction Cycle State Diagram

William Stallings Computer Organization and Architecture 8th Edition

Chapter 3 Top Level View of Computer Interrupt

Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program
e.g. overflow, division by zero

Timer
Generated by internal processor timer Used in pre-emptive multi-tasking

I/O
from I/O controller

Hardware failure
e.g. memory parity error

Program Flow Control

Interrupt Cycle
Added to instruction cycle Processor checks for interrupt
Indicated by an interrupt signal

If no interrupt, fetch next instruction If interrupt pending:

Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program

Transfer of Control via Interrupts

Instruction Cycle with Interrupts

Program Timing Short I/O Wait

Program Timing Long I/O Wait

Instruction Cycle (with Interrupts) State Diagram

Multiple Interrupts
Disable interrupts
Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur

Define priorities
Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt

Multiple Interrupts - Sequential

Multiple Interrupts Nested

Time Sequence of Multiple Interrupts

William Stallings Computer Organization and Architecture 8th Edition Chapter 10 Instruction Sets: Characteristics and Functions

What is an Instruction Set? (2) The complete collection of instructions that are understood by a CPU Machine Code Binary
Operation
8 bits

Operand
24 bits

Operation field

Addressing information

Elements of an Instruction Operation code (Op code)

Do this

Source Operand reference

To this

Result Operand reference

Put the answer here

Next Instruction Reference

When you have done that, do this...

Instruction Cycle State Diagram (1)

Instruction Cycle State Diagram (2)

Instruction Representation (1) In machine code each instruction has a unique bit pattern For human consumption (well, programmers anyway) a symbolic representation is used
e.g. ADD, SUB, LOAD

Operands can also be represented in this way

ADD A,B

Instruction Representation (2)

0001 0011 0111 ?

110100100000 101010001010 101111010100 .. .. .. ..

?
The easier way for us to write instruction is to use hexadecimal 1940 3370

LOAD

Simple Instruction Format

Instruction Types Data processing Data storage (main memory) Data movement (I/O) Program flow control

Number of Addresses (a) 3 addresses

Operand 1, Operand 2, Result a = b + c; ADD a, b, c Operation Operand ADD a b c
Operation Source 1 Source 2 Destination

Needs very long words to hold everything

Number of Addresses (b) 2 addresses

One address doubles as operand and result a = a + b ADD a, b
Operation Source Destination

Reduces length of instruction Requires some extra work

Temporary storage to hold some results

Number of Addresses (c) 1 address

LOAD B = AC B Implicit second address Usually a register (accumulator) Common on early machines

Operation

Source/Destination

Number of Addresses (d) 0 (zero) addresses

All addresses implicit Uses a stack e.g. push pop

How Many Addresses More addresses

More complex (powerful?) instructions More registers
Inter-register operations are quicker

Fewer instructions per program

Fewer addresses
Less complex (powerful?) instructions More instructions per program Faster fetch/execution of instructions

Types of Operand Addresses Numbers

Integer/floating point

Characters
ASCII etc.

Logical Data
Bits or flags

Case study: x86

It is a Intel 8086 CPU It being implemented on Intel, Cyric, AMD It has instruction sets The architecture used until today such as in Intel pentium, Intel Core 2 & etc

Case study: x86 Data Types 8 bit Byte 16 bit word 32 bit double word 64 bit quad word 128 bit double quadword Addressing is by 8 bit unit Words do not need to align at evennumbered address Data accessed across 32 bit bus in units of double word read at addresses divisible by 4 Little endian

x86 Numeric Data Formats

Types of Operation Data Transfer Arithmetic Logical Conversion I/O System Control Transfer of Control

Data Transfer Specify

Source Destination Amount of data

May be different instructions for different movements

e.g. IBM 370

Or one instruction and different addresses

e.g. VAX

Arithmetic Add, Subtract, Multiply, Divide Signed Integer Floating point May include
Increment (a++) Decrement (a--) Negate (-a)

Logical Bitwise operations AND, OR, NOT

Conversion E.g. Binary to Decimal

Input/Output May be specific instructions May be done using data movement instructions (memory mapped) May be done by a separate controller (DMA)

Transfer of Control Branch

e.g. branch to x if result is zero

Skip
e.g. increment and skip if zero ISZ Register1 Branch xxxx ADD A

Subroutine call
c.f. interrupt call

Branch Instruction

Nested Procedure Calls

Byte Order Names The problem is called Endian The system on the left has the least significant byte in the lowest address This is called big-endian The system on the right has the least significant byte in the highest address This is called little-endian

Example of C Data Structure

Alternative View of Memory Map

William Stallings Computer Organization and Architecture 8th Edition Chapter 11 Instruction Sets: Addressing Modes and Formats

Definition of this chapter 11

How is the address of an operand specified How are the bits of an instruction organized to define the operand address and operation of that instruction? Chapter 10 is on:
What instruction does. Examine types of operands and operations

Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement

Immediate Addressing
Operand is part of instruction Operand = address field e.g. ADD 5
Add 5 to contents of accumulator 5 is operand

No memory reference to fetch data Fast Limited range

Immediate Addressing Diagram

Instruction
Opcode Operand

Direct Addressing
Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A
Add contents of cell A to accumulator Look in memory at address A for operand

Single memory reference to access data No additional calculations to work out effective address Limited address space

Direct Addressing Diagram

Instruction
Opcode Address A Memory

Operand

Indirect Addressing (1) Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A)
Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator

Indirect Addressing Diagram (2)

Instruction

Opcode

Address A

Memory Pointer to operand

EA = (A) Look in A, find address (A) and look there for operand

Operand

Indirect Addressing (3) Large address space 2n where n = word length May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself

Multiple memory accesses to find operand Hence slower

Register Addressing (1) Operand is held in register named in address filed EA = R Limited number of registers Very small address field needed
Shorter instructions Faster instruction fetch

Register Addressing Diagram (2)

Instruction
Opcode Register Address R Registers

Operand

Register Addressing (3)

No memory access Very fast execution Very limited address space Multiple registers helps performance
Requires good assembly programming or compiler writing N.B. C programming
register int a;

c.f. Direct addressing

Register Indirect Addressing

C.f. indirect addressing EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2n) One fewer memory access than indirect addressing

Register Indirect Addressing Diagram

Instruction
Opcode Register Address R Memory

Registers

Pointer to Operand

Operand

Displacement Addressing EA = A + (R) Address field hold two values

A = base value R = register that holds displacement or vice versa

Displacement Addressing Diagram

Instruction
Opcode Register R Address A Registers Memory

Pointer to Operand

Operand