STM32U585xx

Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU,

240 DMIPS, up to 2 MB Flash memory, 786 KB SRAM, crypto
Datasheet - production data

Features
Includes ST state-of-the-art patented
technology
LQFP48 (7 x 7 mm) UFQFPN48 WLCSP90 UFBGA132
(7 x 7 mm)
Ultra-low-power with FlexPowerControl LQFP64 (10 x 10 mm) (7 x 7 mm)
LQFP100 (14 x 14 mm)
(4.2 x 3.95 mm)
UFBGA169
LQFP144 (20 x 20 mm) (7 x 7 mm)
• 1.71 V to 3.6 V power supply
• –40 °C to +85/125 °C temperature range • 651 CoreMark® (4.07 CoreMark®/MHz)
• Low-power background autonomous mode • 535 ULPMark™-CP
(LPBAM): autonomous peripherals with DMA, • 149 ULPMark™-PP
functional down to Stop 2 mode
• 58.2 ULPMark™-CM
• VBAT mode: supply for RTC, 32 x 32-bit backup
registers and 2-Kbyte backup SRAM • 133000 SecureMark™-TLS

• 160 nA Shutdown mode (24 wakeup pins) Memories

• 210 nA Standby mode (24 wakeup pins) • 2-Mbyte Flash memory with ECC, 2 banks
• 440 nA Standby mode with RTC read-while-write, including 512 Kbytes with
100 kcycles
• 1.9 μA Stop 3 mode with 16-Kbyte SRAM
• 786-Kbyte SRAM with ECC OFF or 722-Kbyte
• 4.3 µA Stop 3 mode with full SRAM
SRAM including up to 322-Kbyte SRAM with
• 4.0 µA Stop 2 mode with 16-Kbyte SRAM ECC ON
• 8.95 µA Stop 2 mode with full SRAM • External memory interface supporting SRAM,
• 19.5 μA/MHz Run mode @ 3.3 V PSRAM, NOR, NAND and FRAM memories
• 2 Octo-SPI memory interfaces
Core
• Arm® 32-bit Cortex®-M33 CPU with Security and cryptography
TrustZone®, MPU, DSP, and FPU • PSA level 3 and SESIP level 3 certified
ART Accelerator • Arm® TrustZone® and securable I/Os,
memories and peripherals
• 8-Kbyte instruction cache allowing 0-wait-state
execution from Flash and external memories: • Flexible life cycle scheme with RDP and
up to 160 MHz, 240 DMIPS password protected debug

• 4-Kbyte data cache for external memories • Root of trust thanks to unique boot entry and
secure hide protection area (HDP)
Power management • Secure firmware installation (SFI) thanks to
• Embedded regulator (LDO) and SMPS embedded root secure services (RSS)
step-down converter supporting switch • Secure data storage with hardware unique key
on-the-fly and voltage scaling (HUK)
Benchmarks • Secure firmware upgrade support with TF-M

• 1.5 DMIPS/MHz (Drystone 2.1)

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This is information on a product in full production. www.st.com
 STM32U585xx

• 2 AES coprocessors including one with • 3 SPIs (5x SPIs with the dual OCTOSPI)
DPA resistance • 1 CAN FD controller
• Public key accelerator, DPA resistant • 2 SDMMC interfaces
• On-the-fly decryption of Octo-SPI external • 1 multi-function digital filter (6 filters)+ 1 audio
memories digital filter with sound-activity detection
• HASH hardware accelerator • Parallel synchronous slave interface
• True random number generator, NIST
SP800-90B compliant 16- and 4-channel DMA controllers,
functional in Stop mode
• 96-bit unique ID
• 512-byte OTP (one-time programmable) Graphic features
• Active tampers • Chrom-ART Accelerator (DMA2D) for
enhanced graphic content creation
Clock management
• 1 digital camera interface
• 4 to 50 MHz crystal oscillator
• 32 kHz crystal oscillator for RTC (LSE)
Mathematical co-processor
• Internal 16 MHz factory-trimmed RC (±1%) • CORDIC for trigonometric functions
acceleration
• Internal low-power 32 kHz RC (±5%)
• Filter mathematical accelerator (FMAC)
• 2 internal multispeed 100 kHz to 48 MHz
oscillators, including one auto-trimmed by LSE Up to 22 capacitive sensing channels
(better than ±0.25% accuracy)
• Support touch key, linear and rotary touch
• Internal 48 MHz with clock recovery sensors
• 3 PLLs for system clock, USB, audio, ADC
Rich analog peripherals (independent
General-purpose input/outputs supply)
• Up to 136 fast I/Os with interrupt capability • 14-bit ADC 2.5-Msps with hardware
most 5V-tolerant and up to 14 I/Os with oversampling
independent supply down to 1.08 V • 12-bit ADC 2.5-Msps, with hardware
oversampling, autonomous in Stop 2 mode
Up to 17 timers and 2 watchdogs
• 2 12-bit DAC, low-power sample and hold
• 2 16-bit advanced motor-control, 4 32-bit,
5 16-bit, 4 low-power 16-bit (available in Stop • 2 operational amplifiers with built-in PGA
mode), 2 SysTick timers and 2 watchdogs • 2 ultra-low-power comparators
• RTC with hardware calendar and calibration
CRC calculation unit
Up to 22 communication peripherals Debug
• 1 USB Type-C®/USB power delivery controller • Development support: serial-wire debug
• 1 USB OTG 2.0 full-speed controller (SWD), JTAG, Embedded Trace Macrocell™
(ETM)
• 2 SAIs (serial-audio interface)
• 4 I2C FM+(1 Mbit/s), SMBus/PMBus® ECOPACK2 compliant packages
• 6 USARTs (ISO 7816, LIN, IrDA, modem)
Table 1. Device summary
Reference Part numbers

STM32U585AI, STM32U585CI, STM32U585OI, STM32U585QI, STM32U585RI,

STM32U585xx
STM32U585VI, STM32U585ZI

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Arm Cortex-M33 core with TrustZone and FPU . . . . . . . . . . . . . . . . . . . . 22
3.2 ART Accelerator (ICACHE and DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.1 Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.2 Data cache (DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4.1 Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.2 Additional Flash memory protections when TrustZone activated . . . . . 27
3.4.3 FLASH privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5 Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5.1 SRAMs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5.2 SRAMs privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.6.2 Default TrustZone security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9.3 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.9.4 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.9.5 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.10 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.11 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.11.1 RCC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.12 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 50

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3.13.1 GPIOs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.14 Low-power general-purpose inputs/outputs (LPGPIO) . . . . . . . . . . . . . . 50
3.14.1 LPGPIO TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.15 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.16 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . . . . 51
3.17 General purpose direct memory access controller (GPDMA) . . . . . . . . . 51
3.18 Low-power direct memory access controller (LPDMA) . . . . . . . . . . . . . . 53
3.19 Chrom-ART Accelerator controller (DMA2D) . . . . . . . . . . . . . . . . . . . . . . 55
3.20 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.20.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 56
3.20.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 56
3.21 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 57
3.22 CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.23 Filter math accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.24 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.24.1 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.24.2 FSMC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.25 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.25.1 OCTOSPI TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.26 OCTOSPI I/O manager (OCTOSPIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.27 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.28 Analog-to-digital converter (ADC1 and ADC4) . . . . . . . . . . . . . . . . . . . . . 60
3.28.1 Analog-to-digital converter 1 (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.28.2 Analog-to-digital converter 4 (ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.28.3 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.28.4 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.28.5 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.29 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.30 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.31 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.32 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.33 Multi-function digital filter (MDF) and audio digital filter (ADF) . . . . . . . . . 67
3.33.1 Multi-function digital filter (MDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.33.2 Audio digital filter (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.34 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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3.35 Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 71

3.36 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.37 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.38 Secure advanced encryption standard hardware accelerator (SAES)
and encryption standard hardware accelerator (AES) . . . . . . . . . . . . . . . 73
3.39 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.40 On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.41 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.42 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.42.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.42.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15,
TIM16,TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.42.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.42.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4) . . . . . . . . . . . . 79
3.42.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.42.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.42.7 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.42.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.43 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 80
3.43.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.43.2 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.44 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.45 Universal synchronous/asynchronous receiver transmitter (USART/UART)
and low-power universal asynchronous receiver transmitter (LPUART) . 84
3.45.1 Universal synchronous/asynchronous receiver transmitter
(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.45.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . 86
3.46 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.47 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.48 Secure digital input/output and MultiMediaCards interface (SDMMC) . . . 89
3.49 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.50 USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.51 USB Type-C /USB Power Delivery controller (UCPD) . . . . . . . . . . . . . . . 93
3.52 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.52.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.52.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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4 Pinout, pin description and alternate functions . . . . . . . . . . . . . . . . . . 94

4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.2 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . 155
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 155
5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.3.7 External clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.3.8 Internal clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 234
5.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5.3.18 14-bit analog-to-digital converter (ADC1) characteristics . . . . . . . . . . 235
5.3.19 12-bit analog-to-digital converter (ADC4) characteristics . . . . . . . . . . 241
5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

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5.3.21 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
5.3.23 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 247
5.3.24 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 251
5.3.25 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
5.3.26 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 255
5.3.27 Temperature and Backup domain supply thresholds monitoring . . . . . 258
5.3.28 ADF/MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
5.3.29 DCMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
5.3.30 PSSI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
5.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
5.3.32 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
5.3.33 OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
5.3.34 SD/SDIO/e•MMC card host interfaces (SDMMC) characteristics . . . . 286
5.3.35 Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
5.3.36 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
5.3.37 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
5.3.38 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
5.3.39 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
5.3.40 OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
5.3.41 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
5.3.42 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 297

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

6.1 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
6.2 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
6.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
6.4 WLSCP90 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
6.5 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
6.6 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
6.7 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
6.8 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
6.9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

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8
Contents STM32U585xx

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32U585xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3. Access status versus protection level and execution modes when TZEN = 0 . . . . . . . . . . 25
Table 4. Access status versus protection level and execution modes when TZEN = 1 . . . . . . . . . . 26
Table 5. Example of memory map security attribution versus SAU configuration regions . . . . . . . . 29
Table 6. Boot modes when TrustZone is disabled (TZEN = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. Boot modes when TrustZone is enabled (TZEN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. Boot space versus RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9. STM32U585xx mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 10. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 11. GPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 12. GPDMA1 autonomous mode and wakeup in low-power modes. . . . . . . . . . . . . . . . . . . . . 53
Table 13. LPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 14. LPDMA1 autonomous mode and wakeup in low-power modes . . . . . . . . . . . . . . . . . . . . . 55
Table 15. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 16. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 17. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 18. MDF features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 19. AES/SAES features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 20. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 21. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 22. USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 23. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 24. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 25. SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 26. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 27. STM32U585xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 28. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 29. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 30. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 31. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 32. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 33. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 34. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 35. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 36. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 37. Current consumption in Run mode on LDO, code with data processing
running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 160
Table 38. Current consumption in Run mode on SMPS, code with data processing
running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 161
Table 39. Current consumption in Run mode on SMPS, code with data processing
running from Flash memory, ICACHE ON (1-way), prefetch ON, VDD = 3.0 V . . . . . . . . 162
Table 40. Typical current consumption in Run mode on LDO, with different codes
running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON . . . 163
Table 41. Typical current consumption in Run mode on LDO, with different codes
running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 163
Table 42. Typical current consumption in Run mode on SMPS, with different codes
running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON . . . 165

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List of tables STM32U585xx

Table 43. Typical current consumption in Run mode on SMPS, with different codes
running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 165
Table 44. Current consumption in Sleep mode on LDO, Flash memory in power down . . . . . . . . . 167
Table 45. Current consumption in Sleep mode on SMPS, Flash memory in power down . . . . . . . . 168
Table 46. Current consumption in Sleep mode on SMPS,
Flash memory in power down, VDD = 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 47. SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and SMPS . . . . . . . 170
Table 48. Static power consumption of Flash banks, when supplied by LDO/SMPS . . . . . . . . . . . . 171
Table 49. Current consumption in Stop 0 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 50. Current consumption in Stop 0 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 51. Current consumption in Stop 1 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 52. Current consumption during wakeup from Stop 1 mode on LDO . . . . . . . . . . . . . . . . . . . 175
Table 53. Current consumption in Stop 1 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 54. Current consumption during wakeup from Stop 1 mode on SMPS . . . . . . . . . . . . . . . . . 177
Table 55. Current consumption in Stop 2 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 56. SRAM static power consumption in Stop 2 when supplied by LDO . . . . . . . . . . . . . . . . . 179
Table 57. Current consumption during wakeup from Stop 2 mode on LDO . . . . . . . . . . . . . . . . . . . 180
Table 58. Current consumption in Stop 2 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 59. SRAM static power consumption in Stop 2 when supplied by SMPS. . . . . . . . . . . . . . . . 182
Table 60. Current consumption during wakeup from Stop 2 mode on SMPS . . . . . . . . . . . . . . . . . 183
Table 61. Current consumption in Stop 3 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 62. SRAM static power consumption in Stop 3 when supplied by LDO . . . . . . . . . . . . . . . . . 185
Table 63. Current consumption during wakeup from Stop 3 mode on LDO . . . . . . . . . . . . . . . . . . . 186
Table 64. Current consumption in Stop 3 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 65. SRAM static power consumption in Stop 3 when supplied by SMPS. . . . . . . . . . . . . . . . 188
Table 66. Current consumption during wakeup from Stop 3 mode on SMPS . . . . . . . . . . . . . . . . . 189
Table 67. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 68. Current consumption during wakeup from Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 69. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 70. Current consumption during wakeup from Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . 194
Table 71. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 72. Typical dynamic current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 73. Low-power mode wakeup timings on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 74. Low-power mode wakeup timings on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 75. Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 76. Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 77. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 78. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 79. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 80. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 81. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 82. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 83. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 84. SHSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 85. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 86. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 87. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 88. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 89. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 90. EMI characteristics for fHSE = 8 MHz and fHCLK = 160 MHz. . . . . . . . . . . . . . . . . . . . . . . 222
Table 91. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 92. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

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Table 93. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 94. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 95. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 96. Output voltage characteristics for FT_t I/Os in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 228
Table 97. Output AC characteristics, HSLV OFF (all I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . 228
Table 98. Output AC characteristics, HSLV ON (all I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . . 231
Table 99. Output AC characteristics for FT_c I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 100. Output AC characteristics for FT_t I/Os in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 101. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 102. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 103. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 104. 14-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 105. Maximum RAIN for 14-bit ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 106. 14-bit ADC1 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 107. 12-bit ADC4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 108. Maximum RAIN for 12-bit ADC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 109. 12-bit ADC4 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 110. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 111. VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 112. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 113. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 114. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 115. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 116. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 117. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 118. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 119. ADF characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 120. MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 121. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 122. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 123. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 124. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 125. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 126. WWDG min/max timeout value at 160 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 127. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 268
Table 128. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 268
Table 129. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 269
Table 130. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 270
Table 131. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 132. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 271
Table 133. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 134. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 273
Table 135. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 136. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 137. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 138. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 139. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 140. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 141. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 142. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 143. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus . . . . . . . . . . . . . . . . . . . . 283
Table 144. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

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Table 145. e•MMC characteristics (VDD = 1.71 V to 1.9 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table 146. Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 147. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 148. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 149. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 150. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 151. OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 152. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 153. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 154. SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Table 155. UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 156. LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 157. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 158. WLCSP90 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Table 159. WLCSP90 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Table 160. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Table 161. UFBGA132 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Table 162. UFBGA132 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 319
Table 163. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Table 164. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Table 165. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 326
Table 166. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Table 167. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

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List of figures

Figure 1. STM32U585xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 2. STM32U585xQ power supply overview (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 3. STM32U585xx power supply overview (without SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 4. Power-up /down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 5. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 6. VREFBUF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 7. LQFP48_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 8. LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 9. UFQFPN48_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 10. UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 11. LQFP64_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 12. LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 13. WLCSP90-SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 14. LQFP100_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 15. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 16. UFBGA132 _SMPS ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 17. UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 18. LQFP144 _SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 19. LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 20. UFBGA169_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 21. UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 22. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 23. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 24. STM32U585xx power supply scheme (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 25. STM32U585xQ power supply scheme (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 26. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 27. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 28. AC timing diagram for high-speed external clock source . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 29. AC timing diagram for low-speed external square clock source . . . . . . . . . . . . . . . . . . . . 208
Figure 30. AC timing diagram for low-speed external sinusoidal clock source . . . . . . . . . . . . . . . . . 209
Figure 31. Typical application with a 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 32. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 33. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 34. I/O input characteristics (all I/Os except BOOT0 and FT_c). . . . . . . . . . . . . . . . . . . . . . . 226
Figure 35. Output AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 36. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 37. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 38. Typical connection diagram when using the ADC
with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 39. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 40. VREFBUF_OUT versus temperature (VRS = 000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 41. VREFBUF_OUT versus temperature (VRS = 001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 42. VREFBUF_OUT versus temperature (VRS = 010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 43. VREFBUF_OUT versus temperature (VRS = 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 44. OPAMP voltage noise density, normal mode, RLOAD = 3.9 kΩ . . . . . . . . . . . . . . . . . . . . 258
Figure 45. OPAMP voltage noise density, low-power mode, RLOAD = 20 kΩ . . . . . . . . . . . . . . . . . . 258
Figure 46. ADF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 47. MDF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

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List of figures STM32U585xx

Figure 48. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 49. PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 50. PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 267
Figure 52. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 269
Figure 53. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 54. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 55. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 56. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 57. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 58. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 59. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 60. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 61. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 279
Figure 62. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 280
Figure 63. OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 64. OCTOSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 65. OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 66. OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 67. OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 68. OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 69. SD high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 70. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 71. SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 72. USART timing diagram in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 73. USART timing diagram in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 74. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 75. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 76. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 77. SAI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 78. SAI slave timing digram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 79. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 80. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 81. UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Figure 82. UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 83. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 84. LQFP48 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 85. LQFP48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 86. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 87. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 88. LQFP64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 89. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 90. WLCSP90 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 91. WLCSP90 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Figure 92. WLCSP90 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 93. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 94. LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 95. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 96. UFBGA132 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 97. UFBGA132 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Figure 98. UFBGA132 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 99. LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

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STM32U585xx List of figures

Figure 100. LQFP144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Figure 101. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 102. UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 103. UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 104. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

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15
Introduction STM32U585xx

1 Introduction

This document provides the ordering information and mechanical device characteristics of
the STM32U585xx microcontrollers.
For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33
Technical Reference Manual, available from the www.arm.com website.

For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32U575xx and STM32U585xx errata sheet (ES0499)

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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STM32U585xx Description

2 Description

The STM32U585xx devices belong to an ultra-low-power microcontrollers family

(STM32U5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core.
They operate at a frequency of up to 160 MHz.
The Cortex®-M33 core features a single-precision FPU (floating-point unit), that supports all
the Arm® single-precision data-processing instructions and all the data types.
The Cortex®-M33 core also implements a full set of DSP (digital signal processing)
instructions and a MPU (memory protection unit) that enhances the application security.
The devices embed high-speed memories (2 Mbytes of Flash memory and 786 Kbytes of
SRAM), a FSMC (flexible external memory controller) for static memories (for devices with
packages of 90 pins and more), two Octo-SPI Flash memory interfaces (at least one
Quad-SPI available on all packages) and an extensive range of enhanced I/Os and
peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB bus
matrix.
The devices offer security foundation compliant with the TBSA (trusted-based security
architecture) requirements from Arm®. It embeds the necessary security features to
implement a secure boot, secure data storage and secure firmware update. Besides these
capabilities, the devices incorporate a secure firmware installation feature, that allows the
customer to secure the provisioning of the code during its production. A flexible lifecycle is
managed thanks to multiple levels of readout protection and debug unlock with password.
Firmware hardware isolation is supported thanks to securable peripherals, memories and
I/Os, and privilege configuration of peripherals and memories.
The devices feature several protection mechanisms for embedded Flash memory and
SRAM: readout protection, write protection, secure and hide protection areas.
The devices embed several peripherals reinforcing security: a fast AES coprocessor,
a secure AES coprocessor with DPA resistance and hardware unique key that can be
shared by hardware with fast AES, a PKA (public key accelerator) with DPA resistance,
an on-the-fly decryption engine for Octo-SPI external memories, a HASH hardware
accelerator, and a true random number generator.
The devices offer active tamper detection and protection against transient and
environmental perturbation attacks, thanks to several internal monitoring generating secret
data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications.
The devices offer one fast 14-bit ADC (2.5 Msps), one 12-bit ADC (2.5 Msps), two
comparators, two operational amplifiers, two DAC channels, an internal voltage reference
buffer, a low-power RTC, four 32-bit general-purpose timers, two 16-bit PWM timers
dedicated to motor control, three 16-bit general-purpose timers, two 16-bit basic timers and
four 16-bit low-power timers.
The devices support a MDF (multi-function digital filter) with six filters dedicated to the
connection of external sigma-delta modulators. Another low-power digital filter dedicated to
audio signals is embedded (ADF), with one filter supporting sound-activity detection. The
devices embed also a Chrom-ART Accelerator dedicated to graphic applications, and
mathematical accelerators (a trigonometric functions accelerator plus a filter mathematical
accelerator). In addition, up to 22 capacitive sensing channels are available.

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21
Description STM32U585xx

The devices also feature standard and advanced communication interfaces such as:
four I2Cs, three SPIs, three USARTs, two UARTs, one low-power UART, two SAIs, one
digital camera interface (DCMI), two SDMMCs, one FDCAN, one USB OTG full-speed,
one USB Type-C /USB Power Delivery controller, and one generic synchronous 8-/16-bit
PSSI (parallel data input/output slave interface).
The devices operate in the –40 to +85 °C (+105 °C junction) and –40 to +125 °C
(+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.
A comprehensive set of power-saving modes allow the design of low-power applications.
Many peripherals (including communication, analog, timers and audio peripherals) can be
functional and autonomous down to Stop mode with direct memory access, thanks to
LPBAM support (low-power background autonomous mode).
Some independent power supplies are supported like an analog independent supply input
for ADC, DACs, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and
up to 14 I/Os, that can be supplied independently down to 1.08 V. A VBAT input is available
for connecting a backup battery in order to preserve the RTC functionality and to backup 32
32-bit registers and 2-Kbyte SRAM.
The devices offer eight packages from 48 to 169 pins.

Table 2. STM32U585xx features and peripheral counts

STM32U585OI

STM32U585QI
STM32U585CI

STM32U585RI

STM32U585AI
STM32U585VI

STM32U585ZI
Peripherals

Flash memory (Mbytes) 2

System (Kbytes) 784 (192+64+512+16)
SRAM
Backup (bytes) 2048 backup SRAM + 128 backup registers
External memory controller for
No Yes(1) Yes(2)
static memories (FSMC)
OCTOSPI 2(3) 2
Advanced control 2 (16 bits)
General purpose 4 (32 bits) and 3 (16 bits)
Basic 2 (16 bits)

Timers Low power 4 (16 bits)

SysTick timer 2
Watchdog timers
(independent, 2
window)

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STM32U585xx Description

Table 2. STM32U585xx features and peripheral counts (continued)

STM32U585OI

STM32U585QI
STM32U585CI

STM32U585RI

STM32U585AI
STM32U585VI

STM32U585ZI
Peripherals

SPI 3
I2C 4
USART 3
UART 1 2
LPUART 1

Communication SAI 1 2
interfaces FDCAN 1
OTG FS Yes
UCPD Yes
SDMMC 0 2(4)
Camera interface No Yes/No(5) Yes
PSSI No Yes/No(5) Yes
Yes Yes
MDF (multi-function digital filter)
(2 filters) (6 filters)
ADF (audio digital filter) Yes
CORDIC co-processor Yes
FMAC (filter mathematical
Yes
accelerator)
RTC (real-time clock) Yes
Tamper pins (without SMPS / 3/3 4/3 -/8 8/7 8/8 8/7 8/8
with SMPS)
Active tampers (without SMPS /
2/2 3/2 -/7 7/6 7/7 7/6 7/7
with SMPS)(6)
True random number generator Yes
SAES, AES Yes
PKA (public key accelerator) Yes
HASH (SHA-256) Yes
On-the-fly decryption for OCTOSPI Yes
GPIOs (without SMPS / 37 / 33 51 / 47 69 82 / 79 110 / 106 114 / 111 136 / 133
with SMPS)
Wakeup pins (without SMPS /
17 / 15 18 / 17 23 23 / 22 24 / 24 24 / 23 24 / 24
with SMPS)
Number of I/Os down to 1.08 V
(without SMPS / with SMPS) 0/0 0/0 6 0/0 13 / 10 14 / 13 14 / 11

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21
Description STM32U585xx

Table 2. STM32U585xx features and peripheral counts (continued)

STM32U585OI

STM32U585QI
STM32U585CI

STM32U585RI

STM32U585AI
STM32U585VI

STM32U585ZI
Peripherals

Capacitive sensing
Number of channels (without SMPS 5/4 10 / 9 11 19 / 18 22 / 22 22 / 21 22 / 22
/ with SMPS)
12-bit ADC 1
14-bit ADC 1
ADC
Nbr of channels
(without SMPS / 11 / 10 17 / 15 16 20 / 18 24 / 24 24 / 22 24 / 24
with SMPS)
Number of 12-bit
DAC 2
D-to-A converters
Internal voltage reference buffer No Yes
Analog comparator 2
Operational amplifiers 2
Maximum CPU frequency 160 MHz
Operating voltage 1.71 to 3.6 V
Ambient operating temperature: –40 to +85 °C / –40 to +125 °C
Operating temperature
Junction temperature: –40 to +105 °C / –40 to +130 °C
LQFP48,
WLCSP LQFP UFBGA UFBGA
Package UFQFPN LQFP64 LQFP144
90 100 132 169
48
1. For the WLCSP90 package, FSMC can only support 8-bit LCD interface.
2. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 chip select.
3. Two OCTOSPIs are available only in Muxed mode.
4. When both are used simultaneously, one supports only SDIO interface.
5. Available on packages without SMPS, not available on packages with SMPS.
6. Active tampers in output sharing mode (one output shared by all inputs).

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STM32U585xx Description

Figure 1. STM32U585xx block diagram

CLK, NE[4:1], NL, NBL[1:0],
A[25:0], D[15:0], NOE, NWE,
Flexible static memory controller (FSMC):
NJTRST, JTDI, JTCK/SWCLK, JTAG/ SW MPU NWAIT, NCE, INT as AF
SRAM, PSRAM, NOR Flash,FRAM, NAND Flash
JTMS/SWDIO, JTDO
IO[7:0], CLK, NCLK, NCS.
ETM NVIC OTFDEC1 and Octo-SPI1 memory interface DQS as AF

(8 Kbytes)
TRACECLK,

ICACHE
OTFDEC2 and Octo-SPI2 memory interface IO[7:0], CLK, NCLK, NCS.
TRACED[3:0] Arm Cortex-M33 DQS as AF
160 MHz C-BUS Flash memory RNG
TrustZone FPU AES

AHB bus-matrix
(up to 2 Mbytes)
HASH

DCACHE1
S-BUS

(4 Kbytes)
SAES
SRAM1 (192 Kbytes)
@VDDUSB
SRAM2 (64 Kbytes) PKA
D[7:0], D[3:1]dir

FIFO

PHY
DP
FIFO
CMD, CMDdir,CK, CKin SDMMC1 USB FS
SRAM3 (512 Kbytes) DM
D0dir, D2dir
FIFO

SDMMC2
DCMI/PSSI D[15:0], CK, CMD as AF

AHB2 160 MHz

DMA2D
@VDD
@VDD
VDD Power management
SHSI
GPDMA1
Voltage regulator LDO VDD = 1.71 to 3.6 V
HSI48 and SMPS 3.3 to 1.2 V VSS
8 groups of 4 channels max TSC
as AF MSI @VDD
SDIN[5:0], CKIN[5:0], CCK0, Reset Supply supervision
CCK1 as AF MDF1 HSI16 BOR
@VSW Int
VDDIO, VDDUSB, VDDA,
PA[15:0] GPIO port A PVD, PVM VSSA, VDD, VSS, NRST
PLL 1, 2, 3
BKPSRAM
PB[15:0] GPIO port B (2 Kbytes) @VDD
PC[15:13]
AHB1 160 MHz

GPIO port C XTAL OSC

PC[12:0] OSC_IN
@VSW 4- 50 MHz OSC_OUT
PD[15:0] GPIO port D
LSI IWDG
PE[15:0] GPIO port E

PF[15:0] GPIO port F

Standby
PG[15:2] GTZC1 Reset and clock control WKUPx (x=1 to 8)
GPIO port G interface
PG[1:0]
PH[15:0] GPIO port H CRC TIM2 32b 4 channels, ETR as AF
FCLK

HCLKx

PCLKx
PI[7:0] GPIO port I
CORDIC TIM3 32b 4 channels, ETR as AF
136 AF EXT IT. WKP

@VDDA FMAC CRS TIM4 32b 4 channels, ETR as AF

17xIN
ADC1 ITF
TIM5 32b 4 channels, ETR as AF

3 compl. channels smcard

RX, TX, CK, CTS, RTS as AF
(TIM1_CH[1:3]N), TIM1/PWM 16b AHB/APB2 AHB/APB1 USART2 irDA
4 channels (TIM1_CH[1:4]),

APB1 160 MHz (max)

smcard
ETR, BKIN, BKIN2 as AF RX, TX, CK, CTS, RTS as AF
USART3 irDA
3 compl. channels
(TIM1_CH[1:3]N), UART4 RX, TX, CTS, RTS as AF
TIM8/PWM 16b
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF UART5 RX, TX, CTS, RTS as AF
SYSCFG
2 channels, TIM15 16b MOSI, MISO, SCK, NSS as
APB2 160 MHz

1 compl. channel, BKIN as AF SPI2

AF
1 channel, TIM16 16b
1 compl. channel, BKIN as AF
I2C1/SMBUS SCL, SDA, SMBA as AF
1 channel, TIM17 16b
1 compl. channel, BKIN as AF I2C2/SMBUS SCL, SDA, SMBA as AF
smcard
RX, TX, CK,CTS, RTS as AF USART1
irDA
I2C4/SMBUS SCL, SDA, SMBA as AF
WWDG
MOSI, MISO, SCK, NSS as SPI1
FIFO

AF
FDCAN1 TX, RX as AF
MCLK_A, SD_A, FS_A, SRAM4
LPDMA1
SCK_A, MCLK_B, SD_B, (16 Kbytes)
SAI1
PHY

FS_B, SCK_B as AF
AHB bus-matrix

UCPD1 CC1, DBCC1, CC2, DBCC2,

TIM6 16b
FRSCC1, FRSCC2 as AF
AUDIOCLK as AF

MCLK_A, SD_A, FS_A, SAI2 TIM7 16b

SCK_A, MCLK_B, SD_B, IN1, IN2, CH1, CH2,
LPTIM2
FS_B, SCK_B as AF Temperature ETR as AF
monitoring
@VSW
RTC_OUT1, RTC_OUT2, XTAL 32k @VDDA
RTC_REFIN, RTC_TS DAC1_OUT1
RTC D/A converter 1
ITF
RTC_OUT[8:1], RTC_IN[8:1] TAMP
D/A converter 2 DAC1_OUT2
@VDDA AHB/APB3
VREF+
VREF buffer @VDDA
APB3 160 MHz

AHB3 160 MHz

@VDDA ITF ADC4 19xIN

INP, INN, OUT
COMP1
COMP2
INP, INN, OUT

@VDDA LPGPIO IO[15:0] as AF

INP, INN, OUT
OpAmp1
OpAmp2
INP, INN, OUT SDIN0, CKIN0, CCK0,
ADF1
CCK1 as AF
IN1, IN2, CH1, CH2,
LPTIM1
ETR as AF
IN1, IN2, CH1, CH2, LPTIM3 GTZC2
ETR as AF

IN1, OUT, ETR as AF LPTIM4

SCL, SDA, SMBA as AF I2C3/SMBUS VDD power VDDUSB power VSW power VDDIO2 power VDDA power
MOSI, MISO, SCK, NSS as
domain domain domain domain domain
SPI3
AF
RX, TX, CTS, RTS_DE as
LPUART1 Note: VSW = VDD when VDD is above VBOR0, and VSW = VBAT when VDD is below VBOR0.
AF
MSv60471V6

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Functional overview STM32U585xx

3 Functional overview

3.1 Arm Cortex-M33 core with TrustZone and FPU

The Cortex-M33 with TrustZone and FPU is a highly energy-efficient processor designed for
microcontrollers and deeply embedded applications, especially those requiring efficient
security.
The Cortex-M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. It features:
• Arm TrustZone technology, using the Armv8-M main extension supporting secure and
non-secure states
• MPUs (memory protection units), supporting up to 16 regions for secure and
non-secure applications
• Configurable SAU (secure attribute unit) supporting up to eight memory regions as
secure or non-secure
• Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
The Cortex-M33 processor supports the following bus interfaces:
• System AHB bus:
The S-AHB (system AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, external RAM and external device,
or Vendor_SYS regions of the Armv8-M memory map.
• Code AHB bus:
The C-AHB (code AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32U585xx devices.

3.2 ART Accelerator (ICACHE and DCACHE)

3.2.1 Instruction cache (ICACHE)

The ICACHE is introduced on C-AHB code bus of Cortex-M33 processor to improve
performance when fetching instruction (or data) from both internal and external memories.
ICACHE offers the following features:
• Multi-bus interface:
– Slave port receiving the memory requests from the Cortex-M33 C-AHB code
execution port
– Master1 port performing refill requests to internal memories (Flash memory and
SRAMs)
– Master2 port performing refill requests to external memories (external Flash
memory and RAMs through Octo-SPI and FMC interfaces)
– Second slave port dedicated to ICACHE registers access

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STM32U585xx Functional overview

• Close to zero wait-states instructions/data access performance:

– 0 wait-state on cache hit
– Hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
– Critical-word-first refill policy, minimizing processor stalls on cache miss
– Hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– Dual master ports allowing to decouple internal and external memory traffics, on
fast and slow buses, respectively; also minimizing impact on interrupt latency
– Optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– Performance monitoring by means of a hit counter and a miss counter
• Extension of cacheable region beyond the code memory space, by means of address
remapping logic that allows four cacheable external regions to be defined
• Power consumption reduced intrinsically (more accesses to cache memory rather to
bigger main memories); even improved by configuring ICACHE as direct mapped
(rather than the default two-ways set-associative mode)
• TrustZone security support
• Maintenance operation for software management of cache coherency
• Error management: detection of unexpected cacheable write access, with optional
interrupt raising

3.2.2 Data cache (DCACHE)

The DCACHE is introduced on S-AHB system bus of Cortex-M33 processor to improve the
performance of data traffic to/from external memories.
DCACHE offers the following features:
• Multi-bus interface:
– Slave port receiving the memory requests from the Cortex-M33 S-AHB system
port
– Master port performing refill requests to external memories (external Flash
memory and RAMs through Octo-SPI and FMC interfaces)
– Second slave port dedicated to DCACHE registers access
• Close to zero wait-states external data access performance:
– Zero wait-states on cache hit
– Hit-under-miss capability, allowing to serve new processor requests to cached
data, while a line refill (due to a previous cache miss) is still ongoing
– Critical-word-first refill policy for read transactions, minimizing processor stalls on
cache miss
– Hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– Optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– Performance monitoring by means of two hit counters (for read and write) and two
miss counters (for read and write)

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93
Functional overview STM32U585xx

• Supported cache accesses:

– Both write-back and write-through policies supported (selectable with AHB
bufferable attribute)
– Read and write-back always allocated
– Write-through always non-allocated (write-around)
– Byte, half-word and word writes supported
• TrustZone security support
• Maintenance operations for software management of cache coherency:
– Full cache invalidation (non interruptible)
– Address range clean and/or invalidate operations (background task, interruptible)
• Error management: detection of error for master port request initiated by DCACHE (line
eviction or clean operation), with optional interrupt raising

3.3 Memory protection unit

The MPU (memory protection unit) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 16 protected areas.
The MPU regions and registers are banked across secure and non-secure states.
The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by a RTOS
(real-time operating system).
If a program accesses a memory location that is prohibited by the MPU, the RTOS can
detect it and take action. In a RTOS environment, the kernel can dynamically update the
MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

3.4 Embedded Flash memory

The devices feature 2 Mbytes of embedded Flash memory that is available for storing
programs and data. The Flash memory supports 10 000 cycles and up to 100 000 cycles
on 512 Kbytes.
A 128-bit instruction prefetch is implemented and can optionally be enabled.
The Flash memory interface features:
• Dual-bank operating modes
• Read-while-write (RWW)
This allows a read operation to be performed from one bank while an erase or program
operation is performed to the other bank. The dual-bank boot is also supported. Each bank
contains 128 pages of 8 Kbytes. The Flash memory also embeds 512-byte OTP (one-time
programmable) for user data.
The whole non-volatile memory embeds the ECC (error correction code) feature supporting:
• single-error detection and correction
• double-error detection
• ECC fail address report

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3.4.1 Flash memory protection

The option bytes allow the configuration of flexible protections:
• write protection (WRP) to protect areas against erasing and programming. Two areas
per bank can be selected with 8-Kbyte granularity.
• RDP (readout protection) to protect the whole memory, has four levels of protection
available (see Table 3 and Table 4):
– Level 0: no readout protection
– Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the non-secure Flash
memory are possible. The debug access to secure area is prohibited.
Debug access to non-secure area remains possible.
– Level 1: memory readout protection
The Flash memory cannot be read from or written to if either the debug features
are connected or the boot in RAM or bootloader are selected. If TrustZone is
enabled, the non-secure debug is possible and the boot in SRAM is not possible.
Regressions from Level 1 to lower levels can be protected by password
authentication.
– Level 2: chip readout protection
The debug features, the boot in RAM and the bootloader selection are disabled.
A secure secret key can be configured in the secure options to allow the
regression capability from Level 2 to Level 1. By default (key not configured), this
Level 2 selection is irreversible and JTAG/SWD interfaces are disabled. If the
secret key was previously configured in lower RDP levels, the device enables the
RDP regression from Level 2 to Level 1 after password authentication through
JTAG/SWD interface.
Note: In order to reach the best protection level, it is recommended to activate TrustZone and to
set the RDP Level 2 with password authentication regression enabled.

Table 3. Access status versus protection level and execution modes when TZEN = 0
User execution
RDP Debug/boot from RAM/ bootloader(1)
Area (boot from Flash memory)
level
Read Write Erase Read Write Erase

1 Yes Yes Yes No No No(4)

Flash main memory
2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No
System memory (2)
2 Yes No No N/A N/A N/A

1 Yes Yes(4) N/A Yes Yes(4) N/A

Option bytes(3)
2 Yes No(5) N/A N/A N/A N/A

1 Yes Yes(6) N/A Yes Yes(6) N/A

OTP
2 Yes Yes(6) N/A N/A N/A N/A

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Functional overview STM32U585xx

Table 3. Access status versus protection level and execution modes when TZEN = 0 (continued)
User execution
RDP Debug/boot from RAM/ bootloader(1)
Area (boot from Flash memory)
level
Read Write Erase Read Write Erase

1 Yes Yes N/A No No N/A(7)

Backup registers
2 Yes Yes N/A N/A N/A N/A

1 Yes Yes N/A No No N/A(8)

SRAM2/backup
RAM
2 Yes Yes N/A N/A N/A N/A

1 Yes Yes Yes No(9) Yes Yes

OTFDEC regions
(Octo-SPI)
2 Yes Yes Yes N/A N/A N/A

1. When the protection level 2 is active, the debug port, the boot from RAM and the boot from system memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. Option bytes are only accessible through the Flash memory registers and OPSTRT bit.
4. The Flash main memory is erased when the RDP option byte changes from level 1 to level 0.
5. SWAP_BANK option bit can be modified.
6. OTP can only be written once.
7. The backup registers are erased when RDP changes from level 1 to level 0.
8. All SRAMs are erased when RDP changes from level 1 to level 0.
9. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.

Table 4. Access status versus protection level and execution modes when TZEN = 1
User execution
RDP Debug/ bootloader(1)
Area (boot from Flash memory)
level
Read Write Erase Read Write Erase

0.5 Yes Yes Yes Yes(2) Yes(2) Yes(2)

Flash main memory 1 Yes Yes Yes No No No(5)

2 Yes Yes Yes N/A N/A N/A

0.5 Yes No No Yes No No

System memory (3) 1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

0.5 Yes Yes(5) N/A Yes Yes (5) N/A

Option bytes(4) 1 Yes Yes(5) N/A Yes Yes(5) N/A

2 Yes No(6) N/A N/A N/A N/A

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Table 4. Access status versus protection level and execution modes when TZEN = 1 (continued)
User execution
RDP Debug/ bootloader(1)
Area (boot from Flash memory)
level
Read Write Erase Read Write Erase

0.5 Yes Yes(7) N/A Yes Yes(7) N/A

OTP 1 Yes Yes(7) N/A Yes Yes(7) N/A

2 Yes Yes(7) N/A N/A N/A N/A

0.5 Yes Yes N/A Yes(2) Yes(2) N/A(8)

Backup registers 1 Yes Yes N/A No No N/A(8)

2 Yes Yes N/A N/A N/A N/A

0.5 Yes Yes N/A Yes(2) Yes(2) N/A(9)

SRAM2/backup
1 Yes Yes N/A No No N/A(9)
RAM
2 Yes Yes N/A N/A N/A N/A

0.5 Yes Yes Yes No(10) Yes Yes

OTFDEC regions
1 Yes Yes Yes No(10) Yes Yes
(Octo-SPI)
2 Yes Yes Yes N/A N/A N/A

1. When the protection level 2 is active, the debug port and the bootloader mode are disabled.
2. Depends on TrustZone security access rights.
3. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
4. Option bytes are only accessible through the Flash memory registers and OPSTRT bit.
5. The Flash main memory is erased when the RDP option byte regresses from level 1 to level 0.
6. SWAP_BANK option bit can be modified.
7. OTP can only be written once.
8. The backup registers are erased when RDP changes from level 1 to level 0.
9. All SRAMs are erased when RDP changes from level 1 to level 0.
10. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.

3.4.2 Additional Flash memory protections when TrustZone activated

When the TrustZone security is enabled through option bytes, the whole Flash memory is
secure after reset and the following protections are available:
• non-volatile watermark-based secure Flash memory area
The secure area can be accessed only in Secure mode. One area per bank can be
selected with a page granularity.
• secure HDP (hide protection area)
It is part of the Flash memory secure area and can be protected to deny an access to
this area by any data read, write and instruction fetch. For example, a software code in
the secure Flash memory hide protection area can be executed only once and deny

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Functional overview STM32U585xx

any further access to this area until next system reset. One area per bank can be
selected at the beginning of the secure area.
• volatile block-based secure Flash memory area
Each page can be programmed on-the-fly as secure or non-secure.

3.4.3 FLASH privilege protection

Each Flash memory page can be programmed on-the-fly as privileged or unprivileged.

3.5 Embedded SRAMs

Five SRAMs are embedded in the STM32U585xx devices, each with specific features.
SRAM1, SRAM2, and SRAM3 are the main SRAMs. SRAM4 is in the SRAM used for
peripherals LPBAM (low-power background autonomous mode) in Stop 2 mode.
These SRAMs are made of several blocks that can be powered down in Stop mode to
reduce consumption:
• SRAM1: three 64-Kbyte blocks (total 192 Kbytes)
• SRAM2: 8-Kbyte + 56-Kbyte blocks (total 64 Kbytes) with optional ECC. In addition
SRAM2 blocks can be retained in Standby mode.
• SRAM3: eight 64-Kbyte blocks (total 512 Kbytes) with optional ECC. When ECC is
enabled, 256 Kbytes support ECC and 192 Kbytes of SRAM3 can be accessed
without ECC.
• SRAM4: 16 Kbytes
• BKPSRAM (backup SRAM): 2 Kbytes with optional ECC. The BKPSRAM can be
retained in all low-power modes and when VDD is off in VBAT mode, but not in
Shutdown mode.

3.5.1 SRAMs TrustZone security

When the TrustZone security is enabled, all SRAMs are secure after reset.
The SRAM1, SRAM2, SRAM3, SRAM4 can be programmed as secure or non-secure by
blocks, using the MPCBB (block-based memory protection controller).
The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions
can be programmed as secure or non-secure with watermark, using the TZSC (TrustZone
security controller) in the GTZC (global TrustZone controller).

3.5.2 SRAMs privilege protection

The SRAM1, SRAM2, SRAM3, SRAM4 can be programmed as privileged or unprivileged
by blocks, using the MPCBB. The granularity of SRAM privilege block based is a page
of 512 bytes. Backup SRAM regions can be programmed as privileged or unprivileged
with watermark, using the TZSC (TrustZone security controller) in the GTZC (global
TrustZone controller).

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3.6 TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) define the access permissions based on secure
and non-secure state.
• SAU: up to eight SAU configurable regions are available for security attribution.
• IDAU: It provides a first memory partition as non-secure or non-secure callable
attributes. It is then combined with the results from the SAU security attribution and
the higher security state is selected.
Based on IDAU security attribution, the Flash memory, system SRAM and peripheral
memory space is aliased twice for secure and non-secure states. However, the external
memory space is not aliased.
The table below shows an example of typical SAU region configuration based on IDAU
regions. The user can split and choose the secure, non-secure or NSC regions for external
memories as needed.
Table 5. Example of memory map security attribution versus SAU configuration regions
SAU security
Region IDAU security Final security
Address range attribution typical
description attribution attribution
configuration

0x0000 0000 Secure or Secure or

Code - external memories Non-secure
0x07FF FFFF non-secure or NSC(1) non-secure or NSC

0x0800 0000
Non-secure Non-secure Non-secure
0x0BFF FFFF
Code - Flash and SRAM
0x0C00 0000
NSC Secure or NSC Secure or NSC
0x0FFF FFFF
0x1000 0000
0x17FF FFFF
Code - external memories Non-secure
0x1800 0000
Non-secure
0x1FFF FFFF
0x2000 0000
Non-secure
0x2FFF FFFF
SRAM
0x3000 0000
NSC Secure or NSC Secure or NSC
0x3FFF FFFF
0x4000 0000
Non-secure Non-secure Non-secure
0x4FFF FFFF
Peripherals
0x5000 0000
NSC Secure or NSC Secure or NSC
0x5FFF FFFF
0x6000 0000 Secure or Secure or
External memories Non-secure
0xDFFF FFFF non-secure or NSC non-secure or NSC
1. NSC = non-secure callable.

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3.6.1 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or
TrustZone-aware type as follows:
• securable: peripheral protected by an AHB/APB firewall gate that is controlled from
TZSC to define security properties
• TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing
a specific TrustZone behavior such as a subset of registers being secure

3.6.2 Default TrustZone security state

The default system security state is detailed below:
• CPU:
– Cortex-M33 is in secure state after reset. The boot address must be in secure
address.
• Memory map:
– SAU is fully secure after reset. Consequently, all memory map is fully secure.
Up to eight SAU configurable regions are available for security attribution.
• Flash memory:
– Flash memory security area is defined by watermark user options.
– Flash memory block based area is non-secure after reset.
• SRAMs:
– All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
• External memories:
– FSMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection
watermark based controller) is secure.
• Peripherals
– Securable peripherals are non-secure after reset.
– TrustZone-aware peripherals are non-secure after reset. Their secure
configuration registers are secure.
• All GPIOs are secure after reset.
• Interrupts:
– NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-
secure state.
• TZIC: All illegal access interrupts are disabled after reset.

3.7 Boot modes

At startup, a BOOT0 pin, nBOOT0, NSBOOTADDx[24:0] (x = 0, 1) and
SECBOOTADD0[24:0] option bytes are used to select the boot memory address that
includes:
• Boot from any address in user Flash memory.
• Boot from system memory bootloader.
• Boot from any address in embedded SRAM.
• Boot from RSS (root security services).

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The BOOT0 value comes from the PH3-BOOT0 pin or from an option bit depending on the
value of a user option bit to free the GPIO pad if needed.
The bootloader is located in the system memory, programmed by ST during production.
The bootloader is used to reprogram the Flash memory by using USART, I2C, SPI, FDCAN
or USB FS in device mode through the DFU (device firmware upgrade).
The bootloader is available on all devices. Refer to the application note
STM32 microcontroller system memory boot mode (AN2606) for more details.
The RSS are embedded in a Flash memory area named secure information block,
programmed during ST production.
For example, the RSS enable the SFI (secure firmware installation), thanks to the RSSe SFI
(RSS extension firmware).
This feature allows customer to produce the confidentiality of the firmware to be provisioned
into the STM32, when production is sub-contracted to untrusted third party.
The RSS are available on all devices, after enabling the TrustZone through the TZEN option
bit. Refer to the application note Overview secure firmware install (SFI) (AN4992)
for more details.
Refer to Table 6 and Table 7 for boot modes when TrustZone is disabled and
enabled respectively.

Table 6. Boot modes when TrustZone is disabled (TZEN = 0)

nBOOT0 nSWBOOT0 Boot address
BOOT0 ST programmed
FLASH_ FLASH_ option-byte Boot area
pin PH3 default value
OPTR[27] OPTR[26] selection

Boot address defined by

- 0 1 NSBOOTADD0[24:0] user option bytes Flash: 0x0800 0000
NSBOOTADD0[24:0]
Boot address defined by
Bootloader:
- 1 1 NSBOOTADD1[24:0] user option bytes
0x0BF9 0000
NSBOOTADD1[24:0]
Boot address defined by
1 - 0 NSBOOTADD0[24:0] user option bytes Flash: 0x0800 0000
NSBOOTADD0[24:0]
Boot address defined by
Bootloader:
0 - 0 NSBOOTADD1[24:0] user option bytes
0x0BF9 0000
NSBOOTADD1[24:0]

When TrustZone is enabled by setting the TZEN option bit, the boot space must be in the
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure
memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing
to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot
options are ignored.

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Table 7. Boot modes when TrustZone is enabled (TZEN = 1)

nBOOT0 BOOT0 nSWBOOT0 RSS Boot address ST pro-
BOOT_
FLASH_ pin FLASH_ com- option-bytes Boot area grammed
LOCK
OPTR[27] PH3 OPTR[26] mand selection default value

Secure boot address

SECBOOTADD0 defined by user Flash:
- 0 1 0
[24:0] option bytes 0x0C00 0000
SECBOOTADD0[24:0]
RSS:
- 1 1 0 N/A RSS
0x0FF8 0000
Secure boot address
0
SECBOOTADD0 defined by user Flash:
1 - 0 0
[24:0] option bytes 0x0C00 0000
SECBOOTADD0[24:0]
RSS:
0 - 0 0 N/A RSS
0x0FF8 0000
RSS:
- - - ≠0 N/A RSS
0x0FF8 0000
Secure boot address
SECBOOTADD0 defined by user Flash:
1 - - - -
[24:0] option bytes 0x0C00 0000
SECBOOTADD0[24:0]

The boot address option bytes allow any boot memory address to be programmed.
However, the allowed address space depends on the Flash memory RDP level.
If the programmed boot memory address is out of the allowed memory mapped area when
RDP level is 0.5 or more, the default boot address is forced either in secure Flash memory
or non-secure Flash memory, depending on TrustZone security option as described in the
table below.

Table 8. Boot space versus RDP protection

RDP TZEN = 1 TZEN = 0

0 Any boot address Any boot address

0.5 N/A
1 Boot address only in RSS or secure Flash memory: Any boot address
0x0C00 0000 - 0x0C1F FFFF Boot address only in Flash memory
2 Otherwise, forced boot address is 0x0FF8 0000. 0x0800 0000 - 0x081F FFFF
Otherwise, forced boot address is 0x0800 0000.

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3.8 Global TrustZone controller (GTZC)

GTZC is used to configure TrustZone and privileged attributes within the full system.
The GTZC includes three different sub-blocks:
• TZSC: TrustZone security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the non-secure area size for the watermark memory peripheral controller
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
• TZIC: TrustZone illegal access controller
This sub-block gathers all security illegal access events in the system and generates
a secure interrupt towards NVIC.
• MPCBB: MPCBB: block-based memory protection controller
This sub-block controls secure states of all memory blocks (512-byte pages) of the
associated SRAM. This peripheral aims at configuring the internal RAM in a TrustZone
system product having segmented SRAM with programmable-security and privileged
attributes.
The GTZC main features are:
• Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB
• Secure and non-secure access supported for privileged/unprivileged part of TZSC
• Set of registers to define product security settings:
– Secure/privilege regions for external memories
– Secure/privilege access mode for securable peripherals
– Secure/privilege access mode for securable legacy masters

3.9 Power supply management

The PWR (power controller) main features are:
• Power supplies and supply domains
– Core domain (VCORE)
– VDD domain
– Backup domain (VBAT)
– Analog domain (VDDA)
– SMPS power stage (VDDSMPS, available only on SMPS packages)
– VDDIO2 domain
– VDDUSB for USB transceiver
• System supply voltage regulation
– SMPS step down converter
– Voltage regulator (LDO)
• Power supply supervision
– BOR monitor
– PVD monitor
– PVM monitor (VDDA, VDDUSB, VDDIO2)

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• Power management
– Operating modes
– Voltage scaling control
– Low-power modes
• VBAT battery charging
• TrustZone security and privileged protection

3.9.1 Power supply schemes

The devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V (functionality guaranteed down to VBORx min value)
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
• VDDA = 1.58 V (COMPs) / 1.6 V (DACs, OPAMPs) / 1.62 V (ADCs) /
1.8 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for ADCs, DACs, voltage reference buffer,
operational amplifiers and comparators. The VDDA voltage level is independent from
the VDD voltage and must be connected to VDD or VSS pin (preferably to VDD) when
these peripherals are not used.
• VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step down converter. It is provided
externally through VDDSMPS supply pin and must be connected to the same supply
than VDD.
• VLXSMPS is the switched SMPS step down converter output.
Note: The SMPS power supply pins are available only on a specific package with SMPS step
down converter option.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. VDDUSB
voltage level is independent from the VDD voltage and must be connected to VDD or
VSS pin (preferably to VDD) when the USB is not used.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage level
is independent from the VDD voltage and must be connected to VDD or VSS pin
(preferably to VDD) when PG[15:2] are not used.
• VBAT = 1.65 V to 3.6 V (functionality guaranteed down to VBOR_VBAT min value)
VBAT is the power supply for RTC, TAMP, external and internal clocks 32 kHz
oscillators, and backup registers (through power switch) when VDD is not present.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports four outputs:
– VREF+ around 1.5 V. This requires VDDA ≥ 1.8 V.
– VREF+ around 1.8 V. This requires VDDA ≥ 2.1 V.

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– VREF+ around 2.048 V. This requires VDDA ≥ 2.4 V.

– VREF+ around 2.5 V. This requires VDDA ≥ 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled.
VREF- must always be equal to VSSA.
The STM32U585xx devices embed two regulators: one LDO and one SMPS in parallel to
provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3 and SRAM4 and
embedded Flash memory. The SMPS generates this voltage on VDD11 (two pins), with
a total external capacitor of 4.7 μF typical. SMPS requires an external coil of 2.2 μH typical.
The LDO generates this voltage on VCAP pin connected to an external capacitor of 4.7 μF
typical.
Both regulators can provide four different voltages (voltage scaling) and can operate in
Stop modes.
It is possible to switch from SMPS to LDO and from LDO to SMPS on-the-fly.

Figure 2. STM32U585xQ power supply overview (with SMPS)

VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer

VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1 I/O ring

Reset block
Temperature sensor
3 x PLL VCORE domain
Internal RC oscillators
Core
VSS Standby circuitry
(Wakeup logic, IWDG) SRAM1
VDD SRAM2
Voltage regulator SRAM3
SRAM4
LDO regulator VCORE
2x VDD11 Digital
VLXSMPS peripherals
SMPS regulator
VDDSMPS
VSSSMPS
Flash memory
Low-voltage detector

Backup domain
VBAT LSE crystal 32 kHz oscillator
LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
TAMP
BKPSRAM

MSv63604V3

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Figure 3. STM32U585xx power supply overview (without SMPS)

VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer

VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1
I/O ring
VCORE domain
Reset block
Temperature sensor Core
3 x PLL
VSS Internal RC oscillators SRAM1
SRAM2
Standby circuitry SRAM3
(Wakeup logic, IWDG) SRAM4
VDD
VCORE
VCAP Digital
peripherals
LDO regulator

Flash memory
Low-voltage detector

Backup domain
LSE crystal 32kHz oscillator
VBAT LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
TAMP
BKPSRAM

MSv64350V4

During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must remain
below VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
• During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the
power-down transient phase.

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Figure 4. Power-up /down sequence

V

3.6
VDDX(1)

VDD

VBOR0

0.3

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1

1. VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.

3.9.2 Power supply supervisor

The devices have an integrated ultra-low-power BOR (Brownout reset) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the device after power
on and during power down. The device remains in reset mode when the monitored supply
voltage VDD is below a specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded PVD (programmable voltage
detector) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below and/or rises above the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor that compares the independent
supply voltages VDDA, VDDUSB and VDDIO2 to ensure that the peripheral is in its functional
supply range.
The devices support dynamic voltage scaling to optimize its power consumption in Run
mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
• Range 1 (VCORE = 1.2 V) with CPU and peripherals running at up to 160 MHz
• Range 2 (VCORE = 1.1 V) with CPU and peripherals running at up to 110 MHz
• Range 3 (VCORE = 1.0 V) with CPU and peripherals running at up to 55 MHz
• Range 4 (VCORE = 0.9 V) with CPU and peripherals running at up to 25 MHz

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Low-power modes
The ultra-low-power STM32U585xx devices support seven low-power modes to achieve the
best compromise between low-power consumption, short startup time, available peripherals
and available wakeup sources.
The table below details the related low-power modes.

Table 9. STM32U585xx mode overview

(1)
Mode Regulator CPU Flash SRAM Clocks DMA and peripherals(2) Wakeup source

Range 1
Range 2 All
Run Yes ON(3) ON Any N/A
Range 3
Range 4 All except OTG_FS and UCPD
Range 1
Range 2 All Any interrupt or
Sleep No ON ON(4) Any
Range 3 event

Range 4 All except OTG_FS, and UCPD

Range 1 BOR, PVD, PVM,
Reset pin, all I/Os,
Range 2 RTC, TAMP, IWDG,
BOR, PVD, PVM,
Stop 0 TEMP (temp. sensor),
Range 3 RTC, TAMP, IWDG,
VREFBUF,
TEMP,
Range 4 ADC4(7),
DAC1 (2 channels)(8), ADC4,
COMPx (x = 1, 2), DAC1 (2 channels),
OPAMPx (x = 1, 2), COMPx (x = 1, 2),
LSE USARTx (x = 1...5),
USARTx (x = 1...5)(9),
No OFF ON(5) LSI LPUART1,
(6)
LPUART1,
SPIx (x = 1...3)(10), SPIx (x = 1...3),
I2Cx (x = 1...4)(11), I2Cx (x = 1...4),
Stop 1 LPR
LPTIMx (x = 1...4)(12), LPTIMx (x = 1...4),
MDF1(13), ADF1, MDF1, ADF1,
GPIO, LPGPIO, GPDMA1,
LPDMA1,
GPDMA1(14), LPDMA1
OTG_FS, UCPD

All other peripherals are frozen.

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Table 9. STM32U585xx mode overview (continued)

Mode Regulator(1) CPU Flash SRAM Clocks DMA and peripherals(2) Wakeup source

BOR, PVD, PVM, Reset pin, all I/Os,

RTC, TAMP, IWDG, BOR, PVD, PVM,
TEMP, VREFBUF, RTC, TAMP, IWDG,
ADC4, TEMP,
DAC1 (2 channels), ADC4,
COMPx (x = 1, 2), COMPx (x = 1, 2),
OPAMPx (x = 1, 2), LPUART1,
LSE LPUART1, SPI3,
Stop 2 LPR No OFF ON(5)
LSI SPI3, I2C3,
I2C3, LPTIMx (x = 1,3,4),
LPTIMx (x = 1, 3, 4), ADF1,
ADF1, LPDMA1
LPGPIO,
LPDMA1

All other peripherals are frozen.

BOR, Reset pin,
RTC, TAMP, IWDG, 24 I/Os (WKUPx),
DAC1 (2 static channels), BOR, RTC, TAMP,
OPAMPx (x = 1, 2) IWDG
LSE
Stop 3 LPR No OFF ON(5)
LSI
All other peripherals are frozen.

I/O configuration can be floating,

pull-up or pull-down.
all other SRAMs powered off

Reset pin,
64-, 56- or 8-Kbyte SRAM2

BOR, RTC, TAMP, IWDG

2-Kbyte BKPSRAM(5)

24 I/Os (WKUPx),
All other peripherals are BOR, RTC, TAMP,
powered off. IWDG
LPR
Powered off

LSE I/O configuration can be floating,

Standby OFF pull-up or pull-down.
LSI
Powered

OFF
off

RTC, TAMP Reset pin,

24 I/Os (WKUPx),
Powered off

Powered

All other peripherals are RTC, TAMP

Shutdown OFF OFF LSE powered off.
off

I/O configuration can be floating,

pull-up or pull-down(15).

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1. LPR means that the main regulator is OFF and the low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. One bank can
also be put in power-down mode.
4. The SRAM1, SRAM2, SRAM3, SRAM4 and BKPSRAM clocks can be gated on or off independently.
5. The SRAM can be individually powered off to save power consumption.
6. MSI and HSI16 can be temporary enabled upon peripheral request, for autonomous functions with DMA or wakeup from
Stop event detections.
7. The ADC4 conversion is functional and autonomous with DMA in Stop mode, and can generate a wakeup interrupt on
conversion events.
8. DAC1 is the digital-to-analog (D/A) converter controller instance name. This instance controls two D/A converters also
called "two channels". The DAC conversions are functional and autonomous with DMA in Stop mode.
9. U(S)ART and LPUART transmission and reception is functional and autonomous with DMA in Stop mode, and can
generate a wakeup interrupt on transfer events.
10. SPI transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wakeup interrupt
on transfer events.
11. I2C transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wakeup interrupt
on transfer events.
12. LPTIM is functional and autonomous with DMA in Stop mode, and can generate a wakeup interrupt on all events.
13. MDF and ADF are functional and autonomous with DMA in Stop mode, and can generate a wakeup interrupt on events.
14. GPDMA and LPDMA are functional and autonomous in Stop mode, and can generate a wakeup interrupt on events.
15. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.

By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop 0, Stop 1, Stop 2 and Stop 3 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI,
the HSI16, the HSI48 and the HSE crystal oscillators are disabled. The LSE or LSI is
still running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals are autonomous and can operate in Stop mode by requesting their
kernel clock and their bus (APB or AHB) when needed, in order to transfer data with
DMA (GPDMA1 in Stop 0 and Stop 1 modes, LPDMA1 in Stop 0, Stop 1 and Stop 2
modes). Refer to Low-power background autonomous mode (LPBAM) for more details.
LPBAM is not supported in Stop 3 mode.
In Stop 2 and Stop 3 modes, most of the VCORE domain is put in a lower leakage mode.
Stop 0 and Stop 1 modes offer the largest number of active peripherals and wakeup
sources, a smaller wakeup time but a higher consumption than Stop 2 mode.
In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but
with much higher consumption.
Stop 3 is the lowest power mode with full retention, but the functional peripherals and
sources of wakeup are reduced to the same ones than in Standby mode.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 mode can be either MSI
up to 24 MHz or HSI16, depending on software configuration.

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• Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL, the
MSI, the HSI16, the HSI48 and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The BOR always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAMs and register contents are lost except for registers
and backup SRAM in the Backup domain and Standby circuitry. Optionally, the full
SRAM2 or 8 Kbytes or 56 Kbytes can be retained in Standby mode, supplied by the
low-power regulator (Standby with SRAM2 retention mode).
The BOR can be configured in ultra-low-power mode to further reduce power
consumption during Standby mode.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), an RTC event occurs (alarm,
periodic wakeup, timestamp), or a tamper detection. The tamper detection can be
raised either due to external pins or due to an internal failure detection.
The system clock after wakeup is MSI up to 4 MHz.
• Shutdown mode
The lowest power consumption is achieved in Shutdown mode. The internal regulator
is switched off so that the VCORE domain is powered off. The PLL, the HSI16,
the HSI48, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported (VBAT).
SRAMs and register contents are lost except for registers in the Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp), or a tamper detection.
The system clock after wakeup is MSI at 4 MHz.

Low-power background autonomous mode (LPBAM)

The ultra-low-power STM32U585xx devices support LPBAM (low-power background
autonomous mode) that allows peripherals to be functional and autonomous in Stop mode
(Stop 0, Stop 1 and Stop 2 modes), so without any software running.
In Stop 0 and Stop 1 modes, the autonomous peripherals are the following: ADC4, DAC1,
LPTIMx (x = 1 to 4), USARTx (x = 1 to 5), LPUART1, SPIx (x = 1 to 3), I2Cx (x = 1 to 4),
MDF1, ADF1, GPDMA1 and LPDMA1. In these modes, SRAM1, SRAM2, SRAM3 and
SRAM4 can be accessed by the GPDMA1, and SRAM4 can be accessed by the LPDMA1.
In Stop 2 mode, the autonomous peripherals are the following: ADC4, DAC1, LPTIM1,
LPTIM3, LPTIM4, LPUART1, SPI3, I2C3, ADF1 and LPDMA1. In this mode, the SRAM4
can be accessed by the LPDMA1.

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Those peripherals support the features detailed below:

• Functionality in Stop mode thanks to its own independent clock (named kernel clock)
request capability: the peripheral kernel clock is automatically switched on when
requested by a peripheral, and automatically switched off when no peripheral
requests it.
• DMA transfers supported in Stop mode thanks to system clock request capability: the
system clock (MSI or HSI16) automatically switched on when requested by
a peripheral, and automatically switched off when no peripheral requests it. When the
system clock is requested by an autonomous peripheral, the system clock is woken up
and distributed to all peripherals enabled in the RCC. This allows the DMA to access
the enabled SRAM, and any enabled peripheral register (for instance GPIO or LPGPIO
registers).
• Automatic start of the peripheral thanks to hardware synchronous or asynchronous
triggers (such as I/Os edge detection and low-power timer event).
• Wakeup from Stop mode with peripheral interrupt.
The GPDMA and LPDMA are fully functional and the linked-list is updated in Stop mode,
allowing the different DMA transfers to be linked without any CPU wakeup. This can be
used to chain different peripherals transfers, or to write peripherals registers in order to
change their configuration while remaining in Stop mode.
The DMA transfers from memory to memory can be started by hardware synchronous or
asynchronous triggers, and the DMA transfers between peripherals and memories can also
be gated by those triggers.
Here below some use-cases that can be done while remaining in Stop mode:
• A/D or D/A conversion triggered by a low-power timer (or any other trigger)
– wakeup from Stop mode on analog watchdog if the A/D conversion result is out of
programmed thresholds
– wakeup from Stop mode on DMA buffer event
• Audio digital filter data transfer into SRAM
– wakeup from Stop on sound-activity detection
• I2C slave reception or transmission, SPI reception, UART/LPUART reception
– wakeup at the end of peripheral transfer or on DMA buffer event
2
• I C master transfer, SPI transmission, UART/LPUART transmission, triggered by
a low-power timer (or any other trigger):
– example: sensor periodic read
– wakeup at the end of peripheral transfer or on DMA buffer event
• Bridges between peripherals
– example: ADC converted data transferred by communication peripherals
• Data transfer from/to GPIO/LPGPIO to/from SRAM for:
– controlling external components
– implementing data transmission and reception protocols

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Table 10. Functionalities depending on the working mode(1)

Stop 0/1 Stop 2 Stop 3 Standby Shutdown

capability

capability

capability

capability

capability
Wakeup

Wakeup

Wakeup

Wakeup

Wakeup
Peripheral Run Sleep VBAT
- - - - -

CPU Y - - - - - - - - - - - -
Flash memory
O(2) O(2) - - - - - - - - - - -
(2 Mbytes)
SRAM1 (192 Kbytes) Y(3)(4) Y(3)(4) O(7) - O(7) - O(7) - - - - - -
SRAM2 (64 Kbytes) Y(3)(4) Y(3)(4) O(7) O(5) O(7) - O(7) - O(6) - - - -
(3)(4)
SRAM3 (512 Kbytes) Y Y(3)(4) O(7) O(5) O(7) - O(7) - - - - - -
SRAM4 (16 Kbytes) Y(3)(4) Y(3)(4) O(7) - O(7) - O(7) - - - - - -
(4) O(4) O(5)
BKPSRAM O O O O O - O
FSMC O O - - - - - - - - - - -
OCTOSPIx (x = 1,2) O O - - - - - - - - - - -
Backup registers Y Y Y - Y - Y - Y - Y - Y
BOR (Brownout reset) Y Y Y Y Y Y Y Y Y Y - - -
PVD (programmable
O O O O O O - - - - - - -
voltage detector)
Peripheral voltage
O O O O O O - - - - - - -
monitor
GPDMA1 O O O O(8) - - - - - - - - -
LPDMA1 O O O O(9) O O(9) - - - - - - -
DMA2D O O
HSI16 (high-speed (10) (10)
O O - - - - - - - - -
internal)
HSI48 oscillator O O - - - - - - - - - - -
HSE (high-speed
O O - - - - - - - - - - -
external)
LSI (low-speed
O O O - O - O - O - - - O
internal)
LSE (low-speed
O O O - O - O - O - O - O
external)
MSIS and MSIK (10) (10)
O O - - - - - - - - -
(multi-speed internal)
CSS (clock security
O O - - - - - - - - - - -
system)
Clock security system
O O O O O O O O O O O O O
on LSE

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Table 10. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Stop 3 Standby Shutdown

capability

capability

capability

capability

capability
Wakeup

Wakeup

Wakeup

Wakeup

Wakeup
Peripheral Run Sleep VBAT
- - - - -

Backup domain
voltage and
O O O O O O O O O O O O O
temperature
monitoring
RTC/TAMP O O O O O O O O O O O O O
Number of RTC
8 8 8 O 8 O 8 O 8 O 8 O 8
tamper pins
OTG_FS, UCPD O(11) O(11) - O - - - - - - - - -
USARTx
O O O(12) O(12) - - - - - - - - -
(x = 1,2,3,4,5)
Low-power UART
O O O(12) O(12) O(12) O(12) - - - - - - -
(LPUART1)
I2Cx (x = 1,2,4) O O O(13) O(13) - - - - - - - - -
I2C3 O O O(13) O(13) O(13) O(13) - - - - - - -
(14) O(14)
SPIx (x = 1,2) O O O - - - - - - - - -
(14) O(14) O(14) O(14)
SPI3 O O O
FDCAN1 O O - - - - - - - - - - -
SDMMCx (x = 1,2) O O - - - - - - - - - - -
SAIx (x = 1,2) O O - - - - - - - - - - -
ADC1 O O - - - - - - - - - - -
ADC4 O O O(15) O(15) O(15) O(15) - - - - - - -
DAC1 (2 converters) O O O - O - - - - - - - -
VREFBUF O O O - O - - - - - - - -
OPAMPx (x = 1,2) O O O - O - - - - - - - -
COMPx (x = 1,2) O O O O O O - - - - - - -
Temperature sensor O O O - O - - - - - - - -
Timers (TIMx) O O - - - - - - - - - - -

LPTIMx (x = 1,3,4) O O O(16) O(16) O(16) O(16) - - - - - - -

LPTIM2 O O O(16) O(16) - - - - - - - - -

IWDG (independent O O
O O O O O O O (17) O (17) - - -
watchdog)
WWDG (window
O O - - - - - - - - - - -
watchdog)

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Table 10. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Stop 3 Standby Shutdown

capability

capability

capability

capability

capability
Wakeup

Wakeup

Wakeup

Wakeup

Wakeup
Peripheral Run Sleep VBAT
- - - - -

SysTick timer O O - - - - - - - - - - -
MDF1 (multi-function
O O O(18) O(18) - - - - - - - - -
digital filter)
ADF1 (audio digital
O O O(18) O(18) O(18) O(18) - - - - - - -
filter)
DCMI (digital camera
O O - - - - - - - - - - -
interface)
PSSI (paral. synch.
O O - - - - - - - - - - -
slave interface)
CORDIC coprocessor O O - - - - - - - - - - -
FMAC (filter
mathematical O O - - - - - - - - - - -
accelerator)
TSC (touch sensing
O O - - - - - - - - - - -
controller)
RNG (true random
O O - - - - - - - - - - -
number generator)
AES and secure AES O O - - - - - - - - - - -
PKA (public key
O O - - - - - - - - - - -
accelerator)
OTFDEC (on-the-fly
O O - - - - - - - - - - -
decryption)
HASH accelerator O O - - - - - - - - - - -
CRC calculation unit O O - - - - - - - - - - -
- -
24 24 - 24
GPIOs O O O O O O (19) (19) (20) -
pins pins pins
1. Y = yes (enabled). O = optional (disabled by default, can be enabled by software). - = not available.
Gray cells highlight the wakeup capability in each mode.
2. The Flash memory can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAMs can be powered on or off independently.
4. The SRAM clock can be gated on or off independently.
5. ECC error interrupt or NMI wakeup from Stop mode.
6. 8-Kbyte, 56-Kbyte or full SRAM2 content can be preserved.
7. Sub-blocks or full SRAM1 and SRAM3, full SRAM2 and SRAM4 can be powered-off to save power consumption. SRAM1,
SRAM2, SRAM3 and SRAM4 can be accessed by GPDMA1 in Stop 0 and Stop 1 modes. SRAM4 can be accessed by
LPDMA1 in Stop 0, Stop 1 and Stop 2 modes.
8. GPDMA transfers are functional and autonomous in Stop mode, and generates a wakeup interrupt on transfer events.
9. LPDMA transfers are functional and autonomous in Stop mode, and generates a wakeup interrupt on transfer events.

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10. Some peripherals with autonomous mode and wakeup from Stop capability can request HSI16, MSIS or MSIK to be
enabled. In this case, the oscillator is woken up by the peripheral, and is automatically put off when no peripheral needs it.
11. OTG_FS is functional in voltage scaling range 1, 2 and 3.
12. USART and LPUART reception and transmission are functional and autonomous in Stop mode in asynchronous and
in SPI master modes, and generate a wakeup interrupt on transfer events.
13. I2C reception and transmission are functional and autonomous in Stop mode, and generate a wakeup interrupt
on transfer events.
14. SPI reception and transmission are functional and autonomous in Stop mode, and generate a wakeup interrupt
on transfer events.
15. A/D conversion is functional and autonomous in Stop mode, and generates a wakeup interrupt on conversion events.
16. LPTIM is functional and autonomous in Stop mode, and generates a wakeup interrupt on events.
17. Only IWDG reset can exit the device from Stop 3 and Standby modes. Wakeup with IWDG interrupt is not supported.
18. MDF and ADF are functional and autonomous in Stop mode, and generate a wakeup interrupt on events.
19. I/Os can be configured with internal pull-up, pull-down or floating in Stop 3 and Standby modes.
20. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.

3.9.3 Reset mode

In order to improve the consumption under reset, the I/O state under and after reset is
“analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.

3.9.4 VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery or
an external super-capacitor.
The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup registers
and 2-Kbyte backup SRAM. Eight anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal
VBAT battery charging circuit is embedded and can be activated when VDD is present.
Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.

3.9.5 PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security secures the following configuration:
• low-power mode
• WKUP (wakeup) pins
• voltage detection and monitoring
• VBAT mode
Some of the PWR configuration bits security is defined by the security of other peripherals:
• The VOS (voltage scaling) configuration is secure when the system clock selection is
secure in RCC.
• The I/O pull-up/pull-down in Standby mode configuration is secure when the
corresponding GPIO is secure.

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3.10 Peripheral interconnect matrix

Several peripherals have direct connections between them, that allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep,
Low-power Run and Sleep, Stop 0, Stop 1 and Stop 2 modes.

3.11 Reset and clock controller (RCC)

The RCC (reset and clock control) manages the different reset types, and generates all
clocks for the bus and peripherals.
The RCC distributes the clocks coming from the different oscillators to the core and to
the peripherals. It also manages the clock gating for low-power modes and ensures the
clock robustness. It features:
• Clock prescaler: in order to get the best trade-off between speed and current
consumption, the clock frequency to the CPU and peripherals can be adjusted by
a programmable prescaler.
• Clock security system: clock sources can be changed safely on-the-fly in Run mode
through a configuration register.
• Clock management: in order to reduce the power consumption, the clock controller
can stop the clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– HSE (4 to 50 MHz high-speed external crystal or ceramic resonator) that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
– HSI16 (16 MHz high-speed internal RC oscillator) trimmable by software, that can
supply a PLL.
– MSI (multispeed internal RC oscillator) trimmable by software, that can generate
16 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device, saving the need of an external high-speed crystal (HSE). The MSI
can supply a PLL.
– System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 160 MHz.
• HSI48 (RC48 with clock recovery system) internal 48 MHz clock source that can be
used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output
on the MCO.
• UCPD kernel clock, derived from HSI16 clock. The HSI16 RC oscillator must be
enabled prior to the UCPD kernel clock use.

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• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
– LSE (32.768 kHz low-speed external crystal), supporting three drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– LSI (32 kHz low-speed internal RC), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided by 128 to
output a 250 Hz as source clock.
• Peripheral clock sources: several peripherals have their own independent clock
whatever the system clock. Three PLLs, each having three independent outputs
allowing the highest flexibility, can generate independent clocks for the ADC, USB,
SDMMC, RNG, MDF, ADF, FDCAN1, OCTOSPIs and SAIs.
• Startup clock: after reset, the microcontroller restarts by default with MSI. The prescaler
ratio and clock source can be changed by the application program as soon as the code
execution starts.
• CSS (clock security system): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock automatically switches to HSI16 and a software
interrupt is generated if enabled. LSE failure can also be detected and generates
an interrupt.
• Clock-out capability:
– MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application.
– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT mode).
Several prescalers allow AHB and APB frequencies configuration. The maximum frequency
of the AHB and the APB clock domains is 160 MHz.

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Figure 5. Clock tree

LSI RC
32 kHz or 250 Hz
LSCO LSI To IWDG

LSE OSC HSI16

To UCPD1
OSC32_OUT 32.768 kHz
To RTC
Clock LSI
detector LSE
OSC32_IN /32 MSIK x2
HSI16 To LPTIM1, LPTIM3, LPTIM4
LSE
LSI
MSIS To AHB bus, core, memory and DMA
MCO HSI16
/ 1→16 HSE
SYSCLK AHB HCLK FCLK Cortex free running clock
PRESC
pll1_r_ck / 1,2,..512 LSE
HSI48 LSI To Cortex system timer
MSIK /8
Clock
source
OSC_OUT HSE OSC control APB1 PCLK1
4-50 MHz PRESC
HSE To APB1 peripherals
/ 1,2,4,8,16
OSC_IN Clock
detector x1 or x2
SYSCLK To TIMx
(x = 2 to 7)
HSI RC 16 MHz HSI16 LSE
HSI16 x4
To USARTx
SYSCLK
(x = 2 to 5)
MSI RC MSIS
MSIS 100 kHz – 48 MHz MSIK
MSIK HSI16 To SPI2
MSIK 100 kHz – 48 MHz
SYSCLK

HSI48
HSI48 RC 48 MHz HSI16 x3
SYSCLK To I2Cx
MSIK (X = 1,2,4)
MSIS
PLL1 /M HSI16
pll1_p_ck HSE LSI
VCO /P LSE To LPTIM2
pll1_q_ck HSI16
/Q
pll1_r_ck HSE
/N /R pll1_q_ck
pll2_p_ck To FDCAN1

MSIS CRS clock

PLL2 /M HSI16 SYSCLK
HSE MSIK
pll2_p_ck pll1_q_ck
VCO /P To OCTOSPIx
pll2_q_ck pll2_q_ck
(X = 1,2)
/Q
pll2_r_ck PCLK2 To SAES
/N /R
APB2
PRESC
To APB2 peripherals
/ 1,2,4,8,16
MSIS x1 or x2
PLL3 /M HSI16 To TIMx
pll3_p_ck HSE (x = 1,8,15,16,17)
VCO /P
pll3_q_ck
/Q
pll3_r_ck LSE
/N /R HSI16 To USART1
SYSCLK

SHSI RC MSIK
/2 HSI16
SYSCLK To SPI1
pll1_p_ck
pll3_q_ck x2
MSIK To ADF1 and MDF1
AUDIOCLK
pll1_p_ck
pll2_p_ck x2
pll3_p_ck To SAIx
pll1_p_ck HSI16 (X = 1,2)

To SDMMCx
(X = 1,2)
MSIK ICLK
HSI48
pll1_q_ck 48 MHz clock to OTG_FS
pll2_q_ck HSI16
/2
To RNG

PCLK3
APB3
PRESC To APB3 peripherals
/ 1,2,4,8,16

MSIK To I2C3
HSI16

MSIK To SPI3
HSI16

MSIK
HSI16 To LPUART1
LSE
pll2_r_ck
HSE To ADC1, ADC4 and DAC1
HSI16 LSI
MSIK
LSE
DAC1 sample and hold clock
MSv63634V6

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3.11.1 RCC TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
TrustZone security mode.
The RCC TrustZone security secures some RCC system configuration and peripheral
configuration clock from being read or modified by non-secure accesses: when a peripheral
is secure, the related peripheral clock, reset, clock source selection and clock enable during
low-power modes control bits are secure.
A peripheral is in secure state:
• when its corresponding SEC security bit is set in the TZSC (TrustZone security
controller), for securable peripherals.
• when a security feature of this peripheral is enabled through its dedicated bits, for
TrustZone-aware peripherals.

3.12 Clock recovery system (CRS)

The devices embed a special block that allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, that is either derived
from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin
or generated by user software. For faster lock-in during startup, automatic trimming and
manual trimming action can be combined.

3.13 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain),
as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

3.13.1 GPIOs TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a non-secure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.

3.14 Low-power general-purpose inputs/outputs (LPGPIO)

The LPGPIO allows dynamic I/O control in Stop 2 mode thanks to LPDMA1. Up to 16 I/Os
can be configured and controlled as input or output (open-drain or push-pull depending on
GPIO configuration).

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3.14.1 LPGPIO TrustZone security

Each I/O pin registers bit of the LPGPIO is configured as secure if the corresponding I/O is
configured as secure in the GPIO.

3.15 Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all master (CPU, DMA2D, GPDMA1, SDMMC1,
SDMMC2) and slave (Flash memory, RAM, FMC, OCTOSPIs, SRAMs, AHB and APB)
peripherals. It also ensures a seamless and efficient operation even when several high-
speed peripherals work simultaneously.
Another multi-AHB bus matrix interconnects two masters (previous AHB bus matrix slave
port and LPDMA1) and all slaves that are functional in Stop 2 modes (SRAM4 and
AHB/APB peripherals functional in Stop 2 mode).

3.16 System configuration controller (SYSCFG)

The STM32U585xx devices feature a set of configuration registers. The main purposes of
the system configuration controller are the following:
• Managing robustness feature
• Configuring FPU interrupts
• Enabling/disabling the FMP high-drive mode of some I/Os and voltage booster for I/Os
analog switches
• Managing the I/O compensation cell
• Configuring register security access

3.17 General purpose direct memory access controller (GPDMA)

The general purpose direct memory access (GPDMA) controller is a bus master and system
peripheral.
The GPDMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.
The GPDMA main features are:
• Dual bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep and Stop modes
• Transfers arbitration based on a four-grade programmed priority at a channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)

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• Per channel event generation, on any of the following events: transfer complete or half
transfer complete or data transfer error or user setting error, and/or update linked-list
item error or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable
per event
• 16 concurrent DMA channels:
– Per channel FIFO for queuing source and destination transfers
– Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– 12 channels with linear source and destination addressing: either fixed or
contiguously incremented addressing, programmed at a block level, between
successive single transfers
– Four channels with 2D source and destination addressing: programmable signed
address offsets between successive burst transfers (non-contiguous addressing
within a block, combined with programmable signed address offsets between
successive blocks, at a second 2D/repeated block level)
– Support for scatter-gather (multi-buffer transfers), data interleaving and
deinterleaving via 2D addressing
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting including FIFO level and event flags
• TrustZone support:
– Support for secure and non-secure DMA transfers, independently at a first
channel level, and independently at a source/destination and link sub-levels
– Secure and non-secure interrupts reporting, resulting from any of the respectively
secure and non-secure channels
– TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a non-secure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at
channel level
– Privileged-aware AHB slave port

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Table 11. GPDMA1 channels implementation and usage

Hardware parameters
Channel
Features
x dma_fifo_ dma_
size[x] addressing[x]

Channel x (x = 0 to 11) is implemented with:

– a FIFO of 8 bytes, 2 words
x = 0 to 11 2 0 – fixed/contiguously incremented addressing
These channels may be also used for GPDMA transfers, between an APB
or AHB peripheral and SRAM.
Channel x (x = 12 to 15) is implemented with:
– a FIFO of 32 bytes, 8 words
x = 12 to – 2D addressing
4 1
15 These channels may be also used for GPDMA transfers, between
a demanding AHB peripheral and SRAM, or for transfers from/to external
memories.

Table 12. GPDMA1 autonomous mode and wakeup in low-power modes

Feature Low-power modes

Autonomous mode and wakeup GPDMA1 in Sleep, Stop 0 and Stop 1 modes

3.18 Low-power direct memory access controller (LPDMA)

The LPDMA controller is a bus master and system peripheral. The LPDMA is used to
perform programmable data transfers between memory-mapped peripherals and/or
memories via linked-lists, upon the control of an off-loaded CPU.
The LPDMA main features are:
• Single bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep and Stop modes
• Transfers arbitration based on a 4-grade programmed priority at channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete, or
half-transfer complete, or data transfer error, or user setting error, and/or update
linked-list item error, or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable
per event

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• Four concurrent DMA channels:

– Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
padding or truncation, sign extension and left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– Linear source and destination addressing: either fixed or contiguously
incremented addressing, programmed at a block level, between successive
single transfers
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting and event flags
• TrustZone support
– Support for secure and non-secure DMA transfers, independently at a first
channel level, and independently at a source/destination and link sub-levels
– Secure and non-secure interrupts reporting, resulting from any of the respectively
secure and non-secure channels
– TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a non-secure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at
channel level
– Privileged-aware AHB slave port

Table 13. LPDMA1 channels implementation and usage

Hardware parameters
Channel
Features
x dma_fifo_ dma_
size[x] addressing[x]

Channel x (x = 0 to 3) is implemented with:

x = 0 to 3 0 0 – no FIFO. Only a single source transfer cell is internally registered.
– fixed/contiguously incremented addressing

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Table 14. LPDMA1 autonomous mode and wakeup in low-power modes

Feature Low-power modes

Autonomous mode and wakeup LPDMA1 in Sleep, Stop 0, Stop 1 and Stop 2 modes

3.19 Chrom-ART Accelerator controller (DMA2D)

The Chrom-ART Accelerator (DMA2D) is a specialized DMA dedicated to image
manipulation. It can perform the following operations:
• Filling a part or the whole of a destination image with a specific color
• Copying a part or the whole of a source image into a part or the whole of a destination
image
• Copying a part or the whole of a source image into a part or the whole of a destination
image with a pixel format conversion
• Blending a part and/or two complete source images with different pixel format and copy
the result into a part or the whole of a destination image with a different color format.
All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with
indexed or direct color mode. The DMA2D has its own dedicated memories for CLUTs (color
look-up tables).
The main DMA2D features are:
• Single AHB master bus architecture
• AHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT
accesses that are 32-bit)
• User programmable working area size
• User programmable offset for sources and destination areas expressed in pixels or
bytes expressed in pixels or bytes
• User programmable sources and destination addresses on the whole memory space
• Up to two sources with blending operation
• Alpha value can be modified (source value, fixed value or modulated value)
• User programmable source and destination color format
• Up to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct
color coding
• Two internal memories for CLUT storage in indirect color mode
• Automatic CLUT loading or CLUT programming via the CPU
• User programmable CLUT size
• Internal timer to control AHB bandwidth
• Six operating modes: register-to-memory, memory-to-memory, memory-to-memory
with pixel format conversion, memory-to-memory with pixel format conversion and
blending, memory-to memory with pixel format conversion, blending and fixed color
foreground, and memory-to memory with pixel format conversion, blending and fixed
color background
• Area filling with a fixed color
• Copy from an area to another
• Copy with pixel format conversion between source and destination images
• Copy from two sources with independent color format and blending

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• Output buffer byte swapping to support refresh of displays through parallel interface
• Abort and suspend of DMA2D operations
• Watermark interrupt on a user programmable destination line
• Interrupt generation on bus error or access conflict
• Interrupt generation on process completion

3.20 Interrupts and events

3.20.1 Nested vectored interrupt controller (NVIC)

The devices embed a NVIC that is able to manage 16 priority levels and to handle up to 125
maskable interrupt channels plus the 16 interrupt lines of the Cortex-M33.
The NVIC benefits are the following:
• closely coupled NVIC giving low-latency interrupt processing
• interrupt entry vector table address passed directly to the core
• early processing of interrupts
• processing of late arriving higher priority interrupts
• support for tail chaining
• processor state automatically saved
• interrupt entry restored on interrupt exit with no instruction overhead
• TrustZone support: NVIC registers banked across secure and non-secure states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.

3.20.2 Extended interrupt/event controller (EXTI)

The EXTI manages the individual CPU and system wakeup through configurable event
inputs. It provides wakeup requests to the power control, and generates an interrupt request
to the CPU NVIC and events to the CPU event input. For the CPU an additional event
generation block (EVG) is needed to generate the CPU event signal.
The EXTI wakeup requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run modes.
The EXTI also includes the EXTI multiplexer I/O port selection.
The EXTI main features are the following:
• All event inputs allowed to wake up the system
• Configurable events (signals from I/Os or peripherals able to generate a pulse)
– Selectable active trigger edge
– Interrupt pending status register bit independent for the rising and falling edge
– Individual interrupt and event generation mask, used for conditioning the CPU
wakeup, interrupt and event generation
– Software trigger possibility

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• TrustZone secure events

– The access to control and configuration bits of secure input events can be made
secure
• EXTI I/O port selection

3.21 Cyclic redundancy check calculation unit (CRC)

The CRC is used to get a CRC code using a configurable generator with polynomial value
and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, that
can be ulteriorly compared with a reference signature generated at link-time and that can be
stored at a given memory location.

3.22 CORDIC co-processor (CORDIC)

The CORDIC co-processor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications. It speeds up the calculation of these functions
compared to a software implementation, allowing a lower operating frequency, or freeing up
processor cycles in order to perform other tasks.
The CORDIC main features are:
• 24-bit CORDIC rotation engine
• Circular and hyperbolic modes
• Rotation and vectoring modes
• Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root,
natural logarithm
• Programmable precision
• Low-latency AHB slave interface
• Results can be read as soon as ready without polling or interrupt
• DMA read and write channels
• Multiple register read/write by DMA

3.23 Filter math accelerator (FMAC)

The FMAC performs arithmetic operations on vectors. It comprises a MAC
(multiplier/accumulator) unit, together with address generation logic that allows it to index
vector elements held in local memory.
The unit includes support for circular buffers on input and output, that allows digital filters to
be implemented. Both finite and infinite impulse response filters can be done.

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The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
The FMAC main features are:
• 16 x 16-bit multiplier
• 24 + 2-bit accumulator with addition and subtraction
• 16-bit input and output data
• 256 x 16-bit local memory
• Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
• Input and output buffers can be circular
• Filter functions: FIR, IIR (direct form 1)
• Vector functions: dot product, convolution, correlation
• AHB slave interface
• DMA read and write data channels

3.24 Flexible static memory controller (FSMC)

The FSMC includes two memory controllers:
• NOR/PSRAM memory controller
• NAND/memory controller
The FSMC is also named flexible memory controller (FMC).
The main features of the FSMC are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (four memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
– Ferroelectric RAM (FRAM)
• 8-,16-bit data bus width
• Independent chip select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO

3.24.1 LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel® 8080 and Motorola® 6800 modes, and is flexible enough to adapt to
specific LCD interfaces.
This LCD parallel interface capability makes it easy to build cost effective graphic
applications using LCD modules with embedded controllers or high-performance solutions
using external controllers with dedicated acceleration.

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3.24.2 FSMC TrustZone security

When the TrustZone security is enabled, the whole FSMC banks are secure after reset.
Non-secure area can be configured using the TZSC MPCWMx controller:
• FSMC NOR/PSRAM bank:
– Up to two non-secure area can be configured thought the TZSC MPCWM2
controller with a 64-Kbyte granularity
• FSMC NAND bank:
– Can be either configured as fully secure or fully non-secure using the TZSC
MPCWM3 controller
The FSMC registers can be configured as secure through the TZSC controller.

3.25 Octo-SPI interface (OCTOSPI)

The devices embed two OCTOSPIs. The OCTOSPI supports most external serial memories
such as serial PSRAMs, serial NAND and serial NOR Flash memories, HyperRAMs™ and
HyperFlash™ memories, with the following functional modes:
• Indirect mode: all the operations are performed using the OCTOSPI registers.
• Status-polling mode: the external memory status register is periodically read and
an interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation.
The OCTOSPI supports the following protocols with associated frame formats:
• the standard frame format with the command, address, alternate byte, dummy cycles
and data phase
• the HyperBus™ frame format
The OCTOSPI offers the following features:
• Three functional modes: Indirect, Status-polling, and Memory-mapped
• Read and write support in Memory-mapped mode
• Supports for single, dual, quad and octal communication
• Dual-quad mode, where eight bits can be sent/received simultaneously by accessing
two quad memories in parallel.
• SDR (single-data rate) and DTR (double-transfer rate) support
• Data strobe support
• Fully programmable opcode
• Fully programmable frame format
• HyperBus support
• Integrated FIFO for reception and transmission
• 8-, 16-, and 32-bit data accesses allowed
• DMA channel for Indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error

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3.25.1 OCTOSPI TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two non-secure area can be configured thought the TZSC MPCWM1 and MPCWM5
controllers with a granularity of 64 Kbytes.
The OCTOSPI registers can be configured as secure through the TZSC controller.

3.26 OCTOSPI I/O manager (OCTOSPIM)

The OCTOSPI I/O manager is a low-level interface enabling:
• efficient OCTOSPI pin assignment with a full I/O matrix (before alternate function map)
• multiplex of Single-, Dual-, Quad-, Octal-SPI interfaces over the same bus and hence
support memories embedded in a multichip package
The OCTOSPIM main features are:
• Supports up to two Single-, Dual-, Quad-, Octal-SPI interfaces
• Supports up to two ports for pin assignment
• Fully programmable I/O matrix for pin assignment by function (data/control/clock)

3.27 Delay block (DLYB)

The delay block (DLYB) is used to generate an output clock that is dephased from the input
clock. The phase of the output clock must be programmed by the user application. The
output clock is then used to clock the data received by another peripheral such as
a SDMMC or Octo-SPI interface. The delay is voltage and temperature dependent, that may
require the application to re-configure and recenter the output clock phase with the received
data.
The delay block main features are:
• Input clock frequency ranging from 25 to 160 MHz
• Up to 12 oversampling phases

3.28 Analog-to-digital converter (ADC1 and ADC4)

The devices embed two successive approximation analog-to-digital converters.

Table 15. ADC features

ADC modes/features(1) ADC1 ADC4

Resolution 14 bits 12 bits

Maximum sampling speed for 14-bit resolution 2.5 Msps 2.5 Msps
Hardware offset calibration X X
Hardware linearity calibration X -
Single-ended inputs X X
Differential inputs X -

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Table 15. ADC features (continued)

ADC modes/features(1) ADC1 ADC4

Injected channel conversion X -

Oversampling up to x1024 up to x256
Data register 32 bits 16 bits
DMA support X X
Parallel data output to MDF X -
Autonomous mode - X
Offset compensation X -
Gain compensation X -
Number of analog watchdogs 3 3
Wakeup from Stop mode - X(2)
1. X = supported.
2. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes.

3.28.1 Analog-to-digital converter 1 (ADC1)

The ADC1 is a 14-bit ADC successive approximation analog-to-digital converter.
This ADC has up to 20 multiplexed channels. A/D conversion of the various channels can
be performed in Single, Continuous, Scan or Discontinuous mode. The result of the ADC is
stored in a left-aligned or right-aligned 32-bit data register.
This ADC is mapped on the AHB bus to allow fast data handling. The analog watchdog
features allow the application to detect if the input voltage goes outside the user-defined
high or low thresholds.
A built-in hardware over sampler allows analog performances to be improved while
off-loading the related computational burden from the CPU.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.
The ADC1 main features are:
• High-performance features
– 14-, 12-, 10- or 8-bit configurable resolution
– A/D conversion time independent from the AHB bus clock frequency
– Faster conversion time by lowering resolution
– Management of single-ended or differential inputs (programmable per channels)
– Fast data handling thanks to the AHB slave bus interface
– Self-calibration (both offset and linearity)
– Channel-wise programmable sampling time
– Flexible sampling time control
– Up to four injected channels (analog inputs assignment to regular or injected
channels is fully configurable)
– Fast context switching thanks to the hardware assistant that prepares the context
of the injected channels

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– Data alignment with in-built data coherency

– Data can be managed by GPDMA for regular channel conversions with FIFO
– Data can be routed to MDF for post processing
– Four dedicated data registers for the injected channels
• Oversampler
– 32-bit data register
– Oversampling ratio adjustable from 2 to 1024
– Programmable data right and left shift
• Data preconditioning
– Gain compensation
– Offset compensation
• Low-power features
– Speed adaptive low-power mode to reduce ADC consumption when operating at
low frequency
– Slow bus frequency application while keeping optimum ADC performance
– Automatic control to avoid ADC overrun in low AHB bus clock frequency
application (auto-delayed mode)
• ADC features an external analog input channel:
– Up to 17 channels from dedicated GPIO pads
• Three additional internal dedicated channels:
– One channel for internal reference voltage (VREFINT)
– One channel for internal temperature sensor (VSENSE)
– One channel for VBAT monitoring channel (VBAT/4)
• Start-of-conversion can be initiated:
– by software for both regular and injected conversions
– by hardware triggers with configurable polarity (internal timers events or GPIO
input events) for both regular and injected conversions
• Conversion modes
– Single mode: the ADC converts a single channel. The conversion is triggered by
a special event.
– Scan mode: the ADC scans and converts a sequence of channels.
– Continuous mode: the ADC converts continuously selected inputs.
– Discontinuous mode: the ADC converts a subset of the conversion sequence.
• Interrupt generation when the ADC is ready, at end of sampling, end of conversion
(regular or injected), end of sequence conversion (regular or injected), analog
watchdog 1, 2 or 3 or when an overrun event occurs
• Three analog watchdogs
– Filtering to ignore out-of-range data
• ADC input range: VSSA < VIN < VREF+
Note: The ADC1 analog block clock frequency must be between 5 MHz and 55 MHz.

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3.28.2 Analog-to-digital converter 4 (ADC4)

The 12-bit ADC4 is a successive approximation analog-to-digital converter. It has up to
25 multiplexed channels allowing it to measure signals from 19 external and six internal
sources. A/D conversion of the various channels can be performed in Single, Continuous,
Scan or Discontinuous mode. The result of the ADC is stored in a left-aligned or
right-aligned 16-bit data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency. The ADC4 is autonomous in low-power modes down to Stop 2 mode.
A built-in hardware oversampler allows analog performances to be improved while
off-loading the related computational burden from the CPU.
The ADC4 main features are:
• High performance
– 12-, 10-, 8- or 6-bit configurable resolution
– A/D conversion time: 0.4 µs for 12-bit resolution (2.5 MHz), faster conversion
times obtained by lowering resolution
– Self-calibration
– Programmable sampling time
– Data alignment with built-in data coherency
– DMA support
• Low-power
– HCLK frequency reduced for low-power operation while still keeping optimum
ADC performance
– Wait mode: ADC overrun prevented in applications with low frequency HCLK
– Auto-off mode: ADC automatically powered off except during the active
conversion phase, dramatically reducing the ADC power consumption
– Autonomous mode: In low-power modes down to Stop 2 mode, the ADC4 is
automatically switched on when a trigger occurs to start conversion, and it is
automatically switched off after conversion. Data are transfered in SRAM
with DMA.
– ADC4 interrupts wake up the device from Stop 0, Stop 1 and Stop 2 modes.
• Analog input channels
– Up to 19 external analog inputs
– One channel for the internal temperature sensor (VSENSE)
– One channel for the internal reference voltage (VREFINT)
– One channel for the internal digital core voltage (VCORE)
– One channel for monitoring the external VBAT power supply pin
– Connection to two DAC internal channels
• Start-of-conversion can be initiated:
– By software
– By hardware triggers with configurable polarity (timer events or GPIO input
events)

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• Conversion modes
– Conversion of a single channel or scan of a sequence of channels
– Selected inputs converted once per trigger in Single mode
– Selected inputs converted continuously in Continuous mode
– Discontinuous mode
• Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events, with wakeup from Stop
capability
• Analog watchdog
• Oversampler
– 16-bit data register
– Oversampling ratio adjustable from 2 to 256
– Programmable data shift up to 8 bits
• ADC supply requirements: 1.62 to 3.6 V
• ADC input range: VSSA < VIN < VREF+
Note: The ADC4 analog block clock frequency must be between 140 kHz and 55 MHz.

3.28.3 Temperature sensor

The temperature sensor generates a voltage VSENSE that varies linearly with temperature.
The temperature sensor is internally connected to ADC1 and ADC4 input channel that is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the
temperature measurement. As the offset of the temperature sensor varies from chip to chip
due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by STMicroelectronics in the system memory area, accessible in read-only mode.

Table 16. Temperature sensor calibration values

Calibration
Description Memory address
value name

Temperature sensor 14-bit raw data acquired by ADC1

TS_CAL1 0x0BFA 0710 - 0x0BFA 0711
at 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)
Temperature sensor 14-bit raw data acquired by ADC1
TS_CAL2 0x0BFA 0742 - 0x0BFA 0743
at 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)

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3.28.4 Internal voltage reference (VREFINT)

The VREFINT provides a stable (bandgap) voltage output for the ADC and the comparators.
The VREFINT is internally connected to ADC1 and ADC4 input channels.
The precise voltage of VREFINT is individually measured for each part by
STMicroelectronics during production test and stored in the system memory area. It is
accessible in read-only mode.

Table 17. Internal voltage reference calibration values

Calibration value name Description Memory address

14-bit raw data acquired by ADC1

VREFINT_CAL 0x0BFA 07A5 - 0x0BFA 07A6
at 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)

3.28.5 VBAT battery voltage monitoring

This embedded hardware enables the application to measure the VBAT battery voltage using
ADC1 or ADC4 input channel. As the VBAT voltage may be higher than the VDDA, and thus
outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
four. As a consequence, the converted digital value is a quarter of the VBAT voltage.

3.29 Digital to analog converter (DAC)

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller.
In 12-bit mode, the data may be left- or right-aligned.
The DAC features two output channels, each with its own converter. In dual DAC channel
mode, conversions can be done independently or simultaneously when both channels are
grouped together for synchronous update operations. An input reference pin, VREF+
(shared with others analog peripherals) is available for better resolution. An internal
reference can also be set on the same input.
The DAC_OUTx pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to allow a high drive output current. An individual
calibration can be applied on each DAC output channel. The DAC output channels support
a low-power mode, the sample and hold mode.
The digital interface supports the following features:
• One DAC interface, maximum two output channels
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave and triangular-wave generation
• Sawtooth wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• Double data DMA capability to reduce the bus activity
• External triggers for conversion
• DAC output channel buffered/unbuffered modes

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• Buffer offset calibration

• Each DAC output can be disconnected from the DAC_OUTx output pin
• DAC output connection to on chip peripherals
• Sample and hold mode for low-power operation in Stop mode. The DAC voltage can
be changed autonomously with the DMA while the device is in Stop mode.
• Autonomous mode to reduce the power consumption for the system
• Voltage reference input

3.30 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer that can be used as voltage reference for
ADCs, DACs and also as voltage reference for external components through the
VREF+ pin.

Figure 6. VREFBUF block diagram

VREFINT +
VREF+

VSSA
MSv64430V2

The internal voltage reference buffer supports four voltages: 1.5 V, 1.8 V, 2.048 V and 2.5 V.
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.

3.31 Comparators (COMP)

The devices embed two rail-to-rail comparators with programmable reference voltage
(internal or external), hysteresis and speed (low speed for low power) and with selectable
output polarity.
The reference voltage can be one of the following:
• External I/O
• DAC output channels
• Internal reference voltage or submultiple (1/4, 1/2, 3/4)

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All comparators can wake up from Stop 0, Stop 1 and Stop 2 modes, generate interrupts and
breaks for the timers and can also be combined into a window comparator.

3.32 Operational amplifiers (OPAMP)

The devices embed two operational amplifiers with external or internal follower routing and
PGA capability.
The operational amplifier features:
• Low-input bias current
• Low-offset voltage
• Low-power mode
• Rail-to-rail input

3.33 Multi-function digital filter (MDF) and audio digital filter (ADF)
The table below lists the set of features implemented into the MDF and the ADF.

Table 18. MDF features

MDF modes/features(1) ADF1 MDF1
Number of filters (DFLTx) and serial interfaces (SITFx) 1 6
ADF_CKI0 / MDF_CKIy connected to pins - X
Sound activity detection (SAD) X -
RXFIFO depth (number of 24-bit words) 4 4
ADC connected to ADCITF1 - ADC1
ADC connected to ADCITF2 - -
Motor dedicated features (SCD, OLD, OEC, INT, snapshot, break) - X
Main path with CIC4, CIC5 X X
Main path with CIC1,2, 3 or FastSinc - X
RSFLT, HPF, SAT, SCALE, DLY, Discard functions X X
Autonomous in Stop mode X(2) X(3)
1. X = supported.
2. Stop 0, Stop 1 and Stop 2 modes only.
3. Stop 0 and Stop 1 modes only.

3.33.1 Multi-function digital filter (MDF)

The MDF is a high-performance module dedicated to the connection of external sigma-delta
(Σ∆) modulators. It is mainly targeted for the following applications:
• audio capture signals
• motor control
• metering
The MDF features six digital serial interfaces (SITFx) and digital filters (DFLTx) with flexible
digital processing options to offer up to 24-bit final resolution.
The DFLTx of the MDF also include the filters of the ADF (audio digital filter).

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The MDF can receive, via its serial interfaces, streams coming from various digital sensors.
The MDF supports the following standards allowing the connection of various ΣΔ modulator
sensors:
• SPI interface
• Manchester coded 1-wire interface
• PDM interface
A flexible BSMX (bitstream matrix) allows the connection of any incoming bitstream to any
filter.
The MDF converts an input data stream into clean decimated digital data words. This
conversion is done thanks to low-pass digital filters and decimation blocks.In addition it is
possible to insert a high-pass filter or DC offset correction block.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, decimation ratio, integrator length. The
maximum output data resolution is up to 24 bits. There are two conversion modes: single
conversion and continuous modes. The data can be automatically stored in a system RAM
buffer through DMA, thus reducing the software overhead.
A flexible trigger interface can be used to control the conversion start. This timing control
can trigger simultaneous conversions or insert a programmable delay between conversions.
The MDF features an OLD (out-off limit detectors) function. There is one OLD for each
digital filter chain. Independent programmable thresholds are available for each OLD,
making it very suitable for over-current detection.
A SCD (short circuit detector) is also available for every selected bitstream. The SCD is able
to detect a short-circuit condition with a very short latency. Independent programmable
thresholds are offered in order to define the short circuit condition.
All the digital processing is performed using only the kernel clock. The MDF requests the
bus interface clock (AHB clock) only when data must be transfered or when a specific event
requests the attention of the system processor.
The MDF main features are:
• AHB interface
• Six serial digital inputs:
– configurable SPI interface to connect various digital sensors
– configurable Manchester coded interface support
– compatible with PDM interface to support digital microphones
• Two common clock input/output for Σ∆ modulators
• Flexible BSMX for connection between filters and digital inputs
• Two inputs to connect the internal ADCs
• Six flexible digital filter paths, including:
– A configurable CIC filter:
- Can be split into two CIC filters: high-resolution filter and out-off limit detector
- Can be configured in Sinc4 filter
- Can be configured in Sinc5 filter
- Adjustable decimation ratio
– A reshape filter to improve the out-off band rejection and in-band ripple

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– A high-pass filter to cancel the DC offset

– An offset error cancellation
– Gain control
– Saturation blocks
– An out-off limit detector
• Short-circuit detector
• Clock absence detector
• 16- or 24-bit signed output data resolution
• Continuous or single conversion
• Possibility to delay independently each bitstream
• Various trigger possibilities
• Break generation on out-of limit or short-circuit detector events
• Autonomous functionality in Stop modes
• DMA can be used to read the conversion data
• Interrupts services

3.33.2 Audio digital filter (ADF)

The ADF is a high-performance module dedicated to the connection of external Σ∆
modulators. It is mainly targeted for the following applications:
• audio capture signals
• metering
The ADF features one digital serial interface (SITF0) and one digital filter (DFLT0) with
flexible digital processing options to offer up to 24-bit final resolution.
The DLFT0 of the ADF is a subset of the digital filters included into the MDF.
The ADF serial interface supports several standards allowing the connection of various Σ∆
modulator sensors:
• SPI interface
• Manchester coded 1-wire interface
• PDM interface
A flexible BSMX allows the connection of any incoming bitstream to any filter.
The ADF converts an input data stream into clean decimated digital data words. This
conversion is done thanks to low-pass digital filters and decimation blocks. In addition it is
possible to insert a high-pass filter or a DC offset correction block.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, decimation ratio. The maximum output data
resolution is up to 24 bits. There are two conversion modes: single conversion and
continuous modes. The data can be automatically stored in a system RAM buffer through
DMA, thus reducing the software overhead.
A SAD (sound activity detector) is available for the detection of “speech-like” signals. The
SAD is connected at the output of DFLT0. Several parameters can be programmed to adjust
properly the SAD to the sound environment. The SAD can strongly reduce the power
consumption by preventing the storage of samples into the system memory as long as the
observed signal does not match the programmed criteria.

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A flexible trigger interface can be used to control the start of conversion of the ADF.
All the digital processing is performed using only the kernel clock. The ADF requests the bus
interface clock (AHB clock) only when data must be transfered or when a specific event
requests the attention of the system processor.
The ADF main features are:
• AHB interface
• One serial digital input:
– Configurable SPI interface to connect various digital sensors
– Configurable Manchester coded interface support
– Compatible with PDM interface to support digital microphones
• Two common clocks input/output for Σ∆ modulators
• Flexible BSMX for connection between filters and digital inputs
• One flexible digital filter path, including:
– A configurable CIC filter:
- Can be configured in Sinc4 filter
- Can be configured in Sinc5 filter
- Adjustable decimation ratio
– A reshape filter to improve the out-off band rejection and in-band ripple
– A high-pass filter to cancel the DC offset
– Gain control
– Saturation blocks
• Clock absence detector
• Sound activity detector
• 16- or 24-bit signed output data resolution
• Continuous or single conversion
• Possibility to delay independently each bitstream
• Various trigger possibilities
• Autonomous mode in Stop 0, Stop 1 and Stop 2 modes
• Wakeup from Stop with all interrupts
• DMA can be used to read the conversion data
• Interrupts services

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3.34 Digital camera interface (DCMI)

The DCMI is a synchronous parallel interface able to receive a high-speed data flow from
an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats:
YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
This interface is for use with black and white cameras, X24 and X5 cameras, and it is
assumed that all preprocessing such as resizing is performed in the camera module.
The DCMI features are:
• 8-, 10-, 12- or 14-bit parallel interface
• Embedded/external line and frame synchronization
• Continuous or snapshot mode
• Crop feature
• Supports the following data formats:
– 8/10/12/14-bit progressive video: either monochrome or raw Bayer
– YCbCr 4:2:2 progressive video
– RGB 565 progressive video
– Compressed data: JPEG

3.35 Parallel synchronous slave interface (PSSI)

The PSSI and the DCMI use the same circuitry. As a result, these two peripherals cannot be
used at the same time: when using the PSSI, the DCMI registers cannot be accessed, and
vice versa. In addition, the PSSI and the DCMI share the same alternate functions and the
same interrupt vector.
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
enables the transmitter to send a data valid signal that indicates when the data is valid, and
the receiver to output a flow control signal that indicates when it is ready to sample the data.
The PSSI peripheral main features are the following:
• Slave mode operation
• 8-bit or 16-bit parallel data input or output
• 4-word (16-byte) FIFO
• Data enable (PSSI_DE) alternate function input and ready (PSSI_RDY) alternate
function output
When selected, these inputs can either enable the transmitter to indicate when the data is
valid, or allow the receiver to indicate when it is ready to sample the data, or both.

3.36 Touch sensing controller (TSC)

The TSC provides a simple solution to add capacitive sensing functionality to any
application. A capacitive sensing technology is able to detect finger presence near
an electrode that is protected from direct touch by a dielectric (such as glass or plastic). The
capacitive variation introduced by the finger (or any conductive object) is measured using
a proven implementation based on a surface charge transfer acquisition principle.

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The TSC is fully supported by the STMTouch touch sensing firmware library that is free to
use and allows touch sensing functionality to be implemented reliably in the end application.
The TSC main features are the following:
• Proven and robust surface charge transfer acquisition principle
• Supports up to 22 capacitive sensing channels
• Up to eight capacitive sensing channels can be acquired in parallel offering a very good
response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to three capacitive sensing channels to reduce the
system components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.

3.37 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and
an internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct
a non-deterministic random bit generator (NDRBG).
The true random generator:
• delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage
• can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG)
• produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise)
• embeds startup and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
• can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration)
• has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored)

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3.38 Secure advanced encryption standard hardware accelerator

(SAES)
and encryption standard hardware accelerator (AES)
The devices embed two AES accelerators: SAES and AES. The SAES with hardware
unique key embeds protection against differential power analysis (DPA) and related side
channel attacks. The SAES can share its current key register information with the faster
AES using a dedicated hardware bus.
The SAES and the AES can be used to both encrypt and decrypt data using the AES
algorithm. It is a fully compliant implementation of the advanced encryption standard (AES)
as defined by Federal Information Processing Standards Publication (FIPS PUB 197,
Nov 2001).
Multiple chaining modes are supported for key sizes of 128 or 256 bits. ECB and CBC
chaining is supported by both SAES and AES, while CTR, CCM, GCM and GMAC chaining
is only supported by the AES.
SAES and AES support DMA single transfers for incoming and outgoing data (two DMA
channels required).
The SAES supports the selection of all the following key sources, while the AES support
only the first:
• 256-bit software key, written by the application in the key registers (write only)
• 256-bit derived hardware unique key (DHUK), computed inside the SAES engine from
a non-volatile OTP based root hardware unique key (RHUK)
• 256-bit boot hardware key (BHK), stored in tamper-resistant secure backup registers,
written by a secure code during boot. Once written, this key cannot be read or write by
any application until the next product reset.
• XOR of DHUK (provisioned chip secret) and BHK (software secret)
DHUK, BHK and their XOR are not visible by any software (even secure).
Note: 128-bit key size can also be selected.
BHK key is cleared in case of tamper or RDP regression.
When the SAES is secure (respectively non-secure), DHUK secure (respectively non-
secure) is used.
The SAES peripheral is connected by hardware to the true random number generator RNG
(for side-channel resistance).
The SAES and AES peripherals support:
• Compliant implementation of standard NIST Special Publication 197, Advanced
Encryption Standard (AES) and Special Publication 800-38A, Recommendation for
Block Cipher Modes of Operation
• 128-bit data block processing
• Support for cipher keys length of 128-bit and 256-bit
• Encryption and decryption with multiple chaining modes:
– Electronic codebook (ECB) mode
– Cipher block chaining (CBC) mode

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• Additional chaining modes supported by AES only:

– Counter (CTR) mode
– Galois counter mode (GCM)
– Galois message authentication code (GMAC) mode
– Counter with CBC-MAC (CCM) mode
• 528 or 743 clock cycle latency in ECB encryption mode for SAES processing one
128-bit block of data with, respectively, 128-bit or 256-bit key
• 51 or 75 clock cycle latency in ECB encryption mode for AES processing one 128-bit
block of data with, respectively, 128-bit or 256-bit key
• Integrated round key scheduler to compute the last round key for AES ECB/CBC
decryption
• 256-bit register for storing the cryptographic key (four 32-bit registers), with key
atomicity enforcement
• 128-bit registers for storing initialization vectors (four 32-bit registers)
• One 32-bit input buffer and one 32-bit output buffer
• Automatic data flow control with support of single-transfer direct memory access (DMA)
using two channels (one for incoming data, one for processed data)
• Data swapping logic to support 1-, 8-, 16- or 32-bit data
• Possibility for software to suspend a message if the SAES/AES needs to process
another message with a higher priority (suspend/resume operation)
• SAES additional features:
– Security context enforcement for keys
– Hardware secret key encryption/ decryption (wrapped key mode) and sharing with
faster AES peripheral (Shared key mode)
– Protection against differential power analysis (DPA) and related side-channel
attacks
– Optional hardware loading of two hardware secret keys (BHK, DHUK) that can be
XORed together
On top of standard AES encryption and decryption with a key loaded by software, SAES
peripheral allows the following advanced use cases:
• Allow or deny the sharing of a key between a secure and a non-secure application,
enforced by hardware
• Encrypt once a key using side-channel resistant AES, then share it to a faster AES
engine by decrypting it (Shared key mode)
• On-chip encrypted storage using chip-unique secret DHUK
• Transport key generation by encrypting the device public unique ID with the application
secret BHK
• Binding of device secure storage keys, using the silicon unique secret key (DHUK)
XORed with the boot secret key (BHK). If BHK is lost, the whole device secure storage
is lost.
Note: Encrypted storage or derived keys that are using DHUK or BHK, cannot be used anymore
when a security breach is detected.

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Table 19. AES/SAES features

AES/SAES modes/features(1) AES SAES

ECB, CBC chaining X X

CTR, CCM, GCM chaining X -
AES 128-bit ECB encryption in cycles 51 528
DHUK and BHK key selection - X
Side-channel attacks resistance - X
Shared key between SAES and AES X
1. X = supported.

3.39 HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and
the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for
applications requiring message authentication.
The HASH computes FIPS (Federal information processing standards) approved digests of
length of 160, 224, 256 bits, for messages of up to (264 – 1) bits. It also computes 128 bits
digests for the MD5 algorithm.
The HASH main features are:
• Suitable for data authentication applications, compliant with:
– Federal Information Processing Standards Publication FIPS PUB 180-4, Secure
Hash Standard (SHA-1 and SHA-2 family)
– Federal Information Processing Standards Publication FIPS PUB 186-4, Digital
Signature Standard (DSS)
– Internet Engineering Task Force (IETF) Request For Comments RFC 1321, MD5
Message-Digest Algorithm
– Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
• Fast computation of SHA-1, SHA-224, SHA-256, and MD5
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
– 66 clock cycles for processing one 512-bit block of data using MD5 algorithm
• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message:
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit string
– Word swapping supported: bits, bytes, half-words and 32-bit words
• Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)

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• Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,
corresponding to one block size
• AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
• 8 × 32-bit words (H0 to H7) for output message digest
• Automatic data flow control with support of direct memory access (DMA) using one
channel. Single or fixed burst of 4 supported.
• Interruptible message digest computation, on a per-32-bit word basis
– Re-loadable digest registers
– Hashing computation suspend/resume mechanism, including using DMA

3.40 On-the-fly decryption engine (OTFDEC)

The OTFDEC allows the decryption of the on-the-fly AHB traffic based on the read request
address information, for example execute-in-place of a code stored encrypted. Four
independent and non-overlapping encrypted regions can be defined in OTFDEC.
OTFDEC uses AES-128 in counter mode to achieve the lowest possible latency.
As consequence, each time the content of one encrypted region is changed the entire
region must be re-encrypted with a different cryptographic context (key or initialization
vector). This constraint makes OTFDEC suitable to decrypt read-only data or code, stored in
external NOR Flash.
Note: When OTFDEC is used in conjunction with OCTOSPI, it is mandatory to access the Flash
memory using the Memory-mapped mode of the Flash memory controller.
When security is enabled in the product, OTFDEC can be programmed only by
a secure host.
The OTFDEC main features are the following:
• On-the-fly 128-bit decryption during OCTOSPI memory-mapped read operations
(single or multiple)
– Use of AES in counter (CTR) mode, with two 128-bit keystream buffers
– Support for any read size
– Physical address of the reads is used for the encryption/decryption
• Up to 4 independent encrypted regions
– Granularity of the region definition: 4096 bytes
– Region configuration write locking mechanism
– Each region has its own 128-bit key, two bytes firmware version, and eight bytes
application-defined nonce. At least one of those must be changed each time
an encryption is performed by the application.
• Encryption keys confidentiality and integrity protection
– Write-only registers, with software locking mechanism
– Availability of 8-bit CRC as public key information
• Support for OCTOSPI prefetching mechanism
• Possibility to select an enhanced encryption mode to add a proprietary layer of
protection on top of AES stream cipher (execute only)

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• AMBA® AHB slave peripheral, accessible through 32-bit word single accesses only
(otherwise an AHB bus error is generated, and write accesses are ignored)
• Secure only programming if TrustZone security is enabled
• Encryption mode

3.41 Public key accelerator (PKA)

The PKA is intended for the computation of cryptographic public key primitives, specifically
those related to RSA, Diffie-Hellmann or ECC (elliptic curve cryptography) over GF(p)
(Galois fields). To achieve high performance at a reasonable cost, these operations are
executed in the Montgomery domain.
All needed computations are performed within the accelerator, so no further
hardware/software elaboration is needed to process the inputs or the outputs.
The PKA main features are:
• Acceleration of RSA, DH and ECC over GF(p) operations, based on the Montgomery
method for fast modular multiplications. More specifically:
– RSA modular exponentiation, RSA Chinese remainder theorem (CRT)
exponentiation
– ECC scalar multiplication, point on curve check, complete addition, double base
ladder, projective to affine
– ECDSA signature generation and verification
• Capability to handle operands up to 4160 bits for RSA/DH and 640 bits for ECC
• Arithmetic and modular operations such as addition, subtraction, multiplication,
modular reduction, modular inversion, comparison, and Montgomery multiplication
• Built-in Montgomery domain inward and outward transformations
• Protection against differential power analysis (DPA) and related side-channel attacks.

3.42 Timers and watchdogs

The devices include two advanced control timers, up to seven general-purpose timers, two
basic timers, four low-power timers, two watchdog timers and two SysTick timers.
The table below compares the features of the advanced control, general-purpose and basic
timers.

Table 20. Timer feature comparison

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels

Any integer
Advanced Up, down,
TIM1, TIM8 16 bits between 1 and Yes 4 3
control Up/down
65536
Any integer
General- TIM2, TIM3, Up, down,
32 bits between 1 and Yes 4 No
purpose TIM4, TIM5 Up/down
65536

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Table 20. Timer feature comparison (continued)

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels

Any integer
General-
TIM15 16 bits Up between 1 and Yes 2 1
purpose
65536
Any integer
General- TIM16,
16 bits Up between 1 and Yes 1 1
purpose TIM17
65536
Any integer
Basic TIM6, TIM7 16 bits Up between 1 and Yes 0 No
65536

3.42.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted
dead-times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability
(0 - 100%)
• One-pulse mode output
In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in the next
section) using the same architecture, so the advanced-control timers can work together with
the TIMx timers via the Timer Link feature for synchronization or event chaining.

3.42.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15,

TIM16,TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32U585xx devices (see Table 20 for differences). Each general-purpose timer can be
used to generate PWM outputs, or act as a simple time base.
• TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers with 32-bit auto-reload up/downcounter
and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other
general-purpose timers via the Timer Link feature for synchronization or event
chaining.
The counters can be frozen in Debug mode.
All have independent DMA request generation and support quadrature encoders.

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• TIM15, 16 and 17
They are general-purpose timers with mid-range features.
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has two channels and one complementary channel
– TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse
mode output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in Debug mode.

3.42.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebase.

3.42.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4)

The devices embed four low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by HSI16, MSI, LSE, LSI or an external clock. They
are able to wake up the system from Stop mode.
LPTIM1, LPTIM3, and LPTIM4 are active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
The low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)
• Selectable clock
– Internal clock sources: LSE, LSI, HSI16, MSIK (LPTIM1, LPTIM3, LPTIM4 only) or
APB clock (LPTIM2 only)
– External clock source over LPTIM input (working with no LP oscillator running,
used by Pulse Counter application)
• 16-bit ARR autoreload register
• 16-bit capture/compare register
• Continuous/One-shot mode
• Selectable software/hardware input trigger
• Programmable digital glitch filter
• Configurable output: pulse, PWM
• Configurable I/O polarity
• Encoder mode
• Repetition counter
• Up to 2 independent channels for:
– Input capture
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Interrupt generation on 10 events

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• DMA request generation on the following events:

– Update event
– Input capture

3.42.5 Infrared interface (IRTIM)

An infrared interface (IRTIM) for remote control is available on the device. It can be used
with an infrared LED to perform remote control functions. It uses internal connections with
TIM16 and TIM17.

3.42.6 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and a 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as
a watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in Debug mode.

3.42.7 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen
in Debug mode.

3.42.8 SysTick timer

The Cortex-M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
• SysTick, secure instance
• SysTick, non-secure instance
When TrustZone is disabled, only one SysTick timer is available. This timer (secure or
non-secure) is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.

3.43 Real-time clock (RTC), tamper and backup registers

3.43.1 Real-time clock (RTC)

The RTC supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date,
month, year, in BCD (binary-coded decimal) format
• Binary mode with 32-bit free-running counter

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• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Two programmable alarms
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period
• TrustZone support:
– RTC fully securable
– Alarm A, alarm B, wakeup timer and timestamp individual secure or non-secure
configuration
– Alarm A, alarm B, wakeup timer and timestamp individual privileged protection
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be one of the following:
• 32.768 kHz external crystal (LSE)
• external resonator or oscillator (LSE)
• internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
• high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (alarm, wakeup timer, timestamp) can generate an interrupt and wakeup the
device from the low-power modes.

3.43.2 Tamper and backup registers (TAMP)

The anti-tamper detection circuit is used to protect sensitive data from external attacks. 32
32-bit backup registers are retained in all low-power modes and also in VBAT mode. The
backup registers, as well as other secrets in the device, are protected by this anti-tamper
detection circuit with eight tamper pins and eleven internal tampers. The external tamper
pins can be configured for edge detection, or level detection with or without filtering, or
active tamper that increases the security level by auto checking that the tamper pins are not
externally opened or shorted.
TAMP main features:
• A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches
and cryptographic peripherals.
• 32 32-bit backup registers:
– The backup registers (TAMP_BKPxR) are implemented in the Backup domain that
remains powered-on by VBAT when the VDD power is switched off.

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• Up to 8 tamper pins for 8 external tamper detection events:

– Active tamper mode: continuous comparison between tamper output and input to
protect from physical open-short attacks
– Flexible active tamper I/O management: from 4 meshes (each input associated to
its own exclusive output) to 7 meshes (single output shared for up to 7 tamper
inputs)
– Passive tampers: ultra-low power edge or level detection with internal pull-up
hardware management
– Configurable digital filter
• 11 internal tamper events to protect against transient or environmental perturbation
attacks:
– Backup domain voltage monitoring
– Temperature monitoring
– LSE monitoring
– RTC calendar overflow
– JTAG/SWD access if RDP different from 0
– Monotonic counter overflow
– Cryptographic peripherals fault (RNG, SAES, AES, PKA)
– Independent watchdog reset when tamper flag is already set
– 3 ADC4 watchdogs
• Each tamper can be configured in two modes:
– Hardware mode: immediate erase of secrets on tamper detection, including
backup registers erase
– Software mode: erase of secrets following a tamper detection launched by
software
• Any tamper detection can generate a RTC time stamp event.
• TrustZone support:
– Tamper secure or non-secure configuration
– Backup registers configuration in 3 configurable-size areas:
- 1 read/write secure area
- 1 write secure/read non-secure area
- 1 read/write non-secure area
– Boot secret key (BHK) only usable by secure AES peripheral, stored in backup
registers, protected against read and write access
• Tamper configuration and backup registers privilege protection
• Monotonic counter

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3.44 Inter-integrated circuit interface (I2C)

The device embeds four I2C. Refer to Table 21 for the features implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and Master modes, multimaster capability
– Standard-mode (Sm), with a bit rate up to 100 Kbit/s
– Fast-mode (Fm), with a bit rate up to 400 Kbit/s
– Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with
ACK control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBus) specification rev 1.3 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
• Autonomous functionality in Stop modes with wakeup from Stop capability
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

Table 21. I2C implementation

I2C features(1) I2C1 I2C2 I2C3 I2C4

Standard-mode (up to 100 Kbit/s) X X X X

Fast-mode (up to 400 Kbit/s) X X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X
Programmable analog and digital noise filters X X X X
SMBus/PMBus hardware support X X X X
Independent clock X X X X
Autonomous in Stop 0, Stop 1 mode with wakeup capability X X X X
Autonomous in Stop 2 mode with wakeup capability - - X -
1. X: supported

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3.45 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
and low-power universal asynchronous receiver transmitter
(LPUART)
The devices embed three universal synchronous receiver transmitters (USART1, USART2
and USART3), two universal asynchronous receiver transmitters (UART4, UART5) and one
low-power universal asynchronous receiver transmitter (LPUART1).

Table 22. USART, UART and LPUART features

USART modes/features(1) USART1/2/3 UART4/5 LPUART1

Hardware flow control for modem X X X

Continuous communication using DMA X X X
Multiprocessor communication X X X
Synchronous mode (master/slave) X - -
Smartcard mode X - -
Single-wire half-duplex communication X X X
IrDA SIR ENDEC block X X -
LIN mode X X -
(2)
Dual-clock domain and wakeup from Stop mode X X(2) X(3)
Receiver timeout interrupt X X -
Modbus communication X X -
Auto-baud rate detection X X -
Driver enable X X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X X
Tx/Rx FIFO size 8 bytes
Autonomous mode X X X
1. X = supported.
2. Wakeup supported from Stop 0 and Stop 1 modes.
3. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes.

3.45.1 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
The USART offers a flexible means to perform full-duplex data exchange with external
equipments requiring an industry standard NRZ asynchronous serial data format. A very
wide range of baud rates can be achieved through a fractional baud rate generator.
The USART supports both synchronous one-way and half-duplex single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS).
Multiprocessor communications are also supported.

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High-speed data communications up to 20 Mbauds are possible by using the DMA (direct
memory access) for multibuffer configuration.
The USART main features are:
• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to achieve the best compromise
between speed and clock tolerance
• Baud rate generator systems
• Two internal FIFOs for transmit and receive data
Each FIFO can be enabled/disabled by software and come with a status flag.
• A common programmable transmit and receive baud rate
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Auto baud rate detection
• Programmable data word length (7, 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous Master/Slave mode and clock output/input for synchronous
communications
• SPI slave transmission underrun error flag
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications: wakeup from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wakeup from stop capability
• LIN master synchronous break send capability and LIN slave break detection capability
– 13-bit break generation and 10/11-bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16-bit duration for Normal mode
• Smartcard mode
– Supports the T = 0 and T = 1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
– 0.5 and 1.5 stop bits for Smartcard operation

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• Support for Modbus communication

– Timeout feature
– CR/LF character recognition

3.45.2 Low-power universal asynchronous receiver transmitter (LPUART)

The LPUART supports bidirectional asynchronous serial communication with minimum
power consumption. It also supports half-duplex single-wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher-speed clock can be used to
reach higher baudrates.
The LPUART interface can be served by the DMA controller.
The LPUART main features are:
• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate
• From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
• Higher baud rates can be achieved by using a higher frequency clock source
• Two internal FIFOs to transmit and receive data
Each FIFO can be enabled/disabled by software and come with status flags for
FIFO states.
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Programmable data word length (7 or 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– Busy and end of transmission flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte

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• Four error detection flags:

– Overrun error
– Noise detection
– Frame error
– Parity error
• Interrupt sources with flags
• Multiprocessor communications: wakeup from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wakeup from Stop capability

3.46 Serial peripheral interface (SPI)

The devices embed three serial peripheral interfaces (SPI) that can be used to
communicate with external devices while using the specific synchronous protocol. The SPI
protocol supports half-duplex, full-duplex and simplex synchronous, serial communication
with external devices.
The interface can be configured as master or slave and can operate in multi-slave or
multi-master configurations. The device configured as master provides communication
clock (SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be
applied optionally just to setup communication with concrete slave and to assure it handles
the data flow properly. The Motorola® data format is used by default, but some other specific
modes are supported as well.
The SPI main features are:
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only
• Multi master or multi slave mode capability
• Dual-clock domain, separated clock for the peripheral kernel that can be independent
of PCLK
• Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode
• Protection of configuration and setting
• Hardware or software management of SS for both master and slave
• Adjustable minimum delays between data and between SS and data flow
• Configurable SS signal polarity and timing, MISO x MOSI swap capability
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Programmable number of data within a transaction to control SS and CRC
• Dedicated transmission and reception flags with interrupt capability
• SPI Motorola® and Texas Instruments® formats support
• Hardware CRC feature can secure communication at the end of transaction by:
– Adding CRC value in Tx mode
– Automatic CRC error checking for Rx mode

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• Error detection with interrupt capability in case of data overrun, CRC error, data
underrun at slave, mode fault at master
• Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability
• Programmable number of data in transaction
• Configurable FIFO thresholds (data packing)
• Configurable behavior at slave underrun condition (support of cascaded circular
buffers)
• Autonomous functionality in Stop modes (handling of the transaction flow and required
clock distribution) with wakeup from stop capability
• Optional status pin RDY signalizing the slave device ready to handle the data flow.

Table 23. SPI features

SPI1, SPI2 SPI3
SPI feature
(full feature set instances) (limited feature set instance)

Data size Configurable from 4 to 32-bit 8/16-bit

CRC polynomial length CRC polynomial length
CRC computation
configurable from 5 to 33-bit configurable from 9 to 17-bit
Size of FIFOs 16x 8-bit 8x 8-bit
Number of transfered data Unlimited, expandable Up to 1024, no data counter
Autonomous in Stop 0, Stop 1 mode
Yes Yes
with wakeup capability
Autonomous in Stop 2 mode with
No Yes
wakeup capability

3.47 Serial audio interfaces (SAI)

The devices embed two SAIs. Refer to Table 24: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
• Two independent audio sub-blocks that can be transmitters or receivers with their
respective FIFO
• 8-word integrated FIFOs for each audio sub-block
• Synchronous or Asynchronous mode between the audio sub-blocks
• Master or slave configuration independent for both audio sub-blocks
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
• Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and
SPDIF out
• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame
• Number of bits by frame may be configurable

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• Frame synchronization active level configurable (offset, bit length, level)

• First active bit position in the slot is configurable
• LSB first or MSB first for data transfer
• Mute mode
• Stereo/mono audio frame capability
• Communication clock strobing edge configurable (SCK)
• Error flags with associated interrupts if enabled respectively
– Overrun and underrun detection
– Anticipated frame synchronization signal detection in Slave mode
– Late frame synchronization signal detection in Slave mode
– Codec not ready for the AC’97 mode in reception
• Interruption sources when enabled:
– Errors
– FIFO requests
• DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.

Table 24. SAI implementation

SAI features(1) SAI1 SAI2

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X

Mute mode X X
Stereo/mono audio frame capability. X X
16 slots X X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X
FIFO size X (8 words) X (8 words)
SPDIF X X
PDM X -
1. X: supported

3.48 Secure digital input/output and MultiMediaCards interface

(SDMMC)
The SDMMC (SD/SDIO embedded MultiMediaCard e•MMC™ host interface) provides
an interface between the AHB bus and SD memory cards, SDIO cards and e•MMC devices.
The MultiMediaCard system specifications are available through the MultiMediaCard
association website at www.mmca.org, published by the MMCA technical committee.
SD memory card and SD I/O card system specifications are available through the SD card
Association website at www.sdcard.org.

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The SDMMC features include the following:

• Compliance with Embedded MultiMediaCard System Specification Version 5.1
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit
(HS200 SDMMC_CK speed limited to maximum allowed I/O speed) (HS400 is not
supported).
• Full compatibility with previous versions of MultiMediaCards (backward compatibility).
• Full compliance with SD memory card specifications version 6.0
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Full compliance with SDIO card specification version 4.0
Card support for two different databus modes: 1-bit (default) and 4-bit
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Data transfer up to 208 Mbyte/s for the 8-bit mode
(Depending maximum allowed I/O speed).
• Data and command output enable signals to control external bidirectional drivers
• IDMA linked list support
The MultiMediaCard/SD bus connects cards to the host.
The current version of the SDMMC supports only one SD/SDIO/e•MMC card at any one
time and a stack of e•MMC.

Table 25. SDMMC features

SDMMC modes/features(1) SDMMC1 SDMMC2

Variable delay (SDR104, HS200) X X

SDMMC_CKIN X -
SDMMC_CDIR, SDMMC_D0DIR X -
SDMMC_D123DIR X -
1. X = supported.

When SDMMC peripherals are used simultaneously:

• Only one can be used in e•MMC with 8-bit bus width.
• The SDMMC1 SDIO voltage switch use is mutually exclusive with SDMMC2 interfacing
e•MMC with 8-bit bus width, as follows:
– If SDMMC1 has to support SDIO UHS-I modes (SDR12, SDR25, SDR50,
SDR104 or DDR50), SDMMC2 cannot support e•MMC with 8-bit bus width.
– if SDMMC2 has to support e•MMC with 8-bit bus width, SDMMC1 supports only
SDIO default mode and high-speed mode.

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3.49 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN module, a shared
message RAM memory and a configuration block.
The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and
transmits FIFOs.
The FDCAN main features are:
• Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4
• CAN FD with maximum 64 data bytes supported
• CAN error logging
• AUTOSAR and J1939 support
• Improved acceptance filtering
• 2 receive FIFOs of three payloads each (up to 64 bytes per payload)
• Separate signaling on reception of high priority messages
• Configurable transmit FIFO / queue of three payload (up to 64 bytes per payload)
• Configurable transmit Event FIFO
• Programmable loop-back test mode
• Maskable module interrupts
• Two clock domains: APB bus interface and CAN core kernel clock
• Power-down support

3.50 USB on-the-go full-speed (OTG_FS)

The devices embed a USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG_FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume.
This interface requires a precise 48 MHz clock that can be generated from the internal main
PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator
(HSI48) in Automatic-trimming mode. The synchronization for this oscillator can be taken
from the USB data stream itself (SOF signalization) that allows crystal less operation.
The OTG_FS features are:
• USB-IF certified to the Universal Serial Bus Specification Rev 2.0
• On-chip full-speed PHY
• Full support (PHY) for the optional OTG (on-the-go) protocol detailed in the OTG
Supplement Rev 2.0 specification
– Integrated support for A-B device identification (ID line)
– Integrated support for host negotiation protocol (HNP) and session request
protocol (SRP)
– Allows host to turn VBUS off to conserve battery power in OTG applications
– Supports OTG monitoring of VBUS levels with internal comparators
– Supports dynamic host-peripheral switch of role

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• Software-configurable to operate as:

– SRP capable USB FS peripheral (B-device)
– SRP capable USB FS/LS host (A-device)
– USB On-The-Go Full-Speed dual role device
• Supports FS SOF and LS keep-alives with
– SOF pulse PAD connectivity
– SOF pulse internal connection to timer (TIMx)
– Configurable framing period
– Configurable end of frame interrupt
• USB 2.0 link power management (LPM) support
• Includes power saving features such as system stop during USB suspend, switch-off
of clock domains internal to the digital core, PHY and DFIFO power management.
• Dedicated RAM of 1.25 Kbytes with advanced FIFO control:
– Configurable partitioning of RAM space into different FIFOs for flexible and
efficient use of RAM
– Each FIFO able to hold multiple packets
– Dynamic memory allocation
– Configurable FIFO sizes that are not powers of two to allow the use of contiguous
memory locations
• Max guaranteed USB bandwidth for up to one frame (1 ms) without system intervention
• Support of charging port detection as described in Battery Charging Specification
revision 1.2 on the FS PHY transceiver only.
Host-mode features:
• External charge pump for VBUS voltage generation.
• Up to 12 host channels (pipes): each channel is dynamically reconfigurable to allocate
any type of USB transfer.
• Built-in hardware scheduler holding:
– Up to 12 interrupt plus isochronous transfer requests in the periodic hardware
queue
– Up to 12 control plus bulk transfer requests in the non-periodic hardware queue
• Management of a shared Rx FIFO, a periodic Tx FIFO and a non-periodic Tx FIFO for
efficient usage of the USB data RAM
Peripheral-mode features:
• 1 bidirectional control endpoint0
• 5 IN endpoints (EPs) configurable to support bulk, interrupt or isochronous transfers
• 5 OUT endpoints configurable to support bulk, interrupt or isochronous transfers
• Management of a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB
data RAM
• Management of up to 6 dedicated Tx-IN FIFOs (one for each active IN EP) to put less
load on the application
• Support for the soft disconnect feature

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3.51 USB Type-C /USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Cable and
Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB power delivery
requirements, featuring:
• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB power delivery message transmission and reception
• FRS (fast role swap) support
The digital controller handles notably:
• USB Type-C level detection with debounce, generating interrupts
• FRS detection, generating an interrupt
• Byte-level interface for USB power delivery payload, generating interrupts
(DMA compatible)
• USB power delivery timing dividers (including a clock prescaler)
• CRC generation/checking
• 4b5b encode/decode
• Ordered sets (with a programmable ordered set mask at receive)
• Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB power delivery messages and FRS signaling.

3.52 Development support

3.52.1 Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can
be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.

3.52.2 Embedded Trace Macrocell

The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high rate from
the devices through a small number of ETM pins to an external hardware trace port analyzer
(TPA) device.
Real-time instruction and data flow activity be recorded and then formatted for display on
the host computer that runs the debugger software. TPA hardware is commercially available
from common development tool vendors.
The ETM operates with third party debugger software tools.

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4 Pinout, pin description and alternate functions

4.1 Pinout/ballout schematics

Figure 7. LQFP48_SMPS pinout

PH3-BOOT0
VDD11

PA15
PA14
VDD
VSS

PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 VDD
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
VLXSMPS
VDDSMPS
VSSSMPS

VSS
PA3
PA4
PA5
PA6
PA7

VDD11

MSv62928V1

1. The above figure shows the package top view.

Figure 8. LQFP48 pinout

PH3-BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37

VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3
PA4
PA5
PA6
PA7

MSv62922V1

1. The above figure shows the package top view.

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Figure 9. UFQFPN48_SMPS pinout

PH3-BOOT0
VDD11

PA15
PA14
VDD
VSS

PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
UFQFPN48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 VDD
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
VLXSMPS
VDDSMPS
VSSSMPS

VSS
PA3
PA4
PA5
PA6
PA7

VDD11
MSv63695V3

1. The above figure shows the package top view.

Figure 10. UFQFPN48 pinout

PH3-BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37

VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
UFQFPN48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3
PA4
PA5
PA6
PA7

MSv63696V2

1. The above figure shows the package top view.

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Figure 11. LQFP64_SMPS pinout

PH3-BOOT0
VDD11

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB8

PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 VDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS

VSS
VDD

PB0
PB1
PB2
PB10
VLXSMPS
VDDSMPS
VSSSMPS
PA3

PA4
PA5
PA6
PA7

VDD11
MSv62929V1

1. The above figure shows the package top view.

Figure 12. LQFP64 pinout

PH3-BOOT0

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB9
PB8

PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD

PC4
PC5
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3

PA4
PA5
PA6
PA7

MSv62923V1

1. The above figure shows the package top view.

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Figure 13. WLCSP90-SMPS ballout

1 3 5 7 9 11 13 15 17
2 4 6 8 10 12 14 16 18

A VDD PC11 PD2 PG10 PG14 VDDIO2 PB6 PB9 VDD11

B VSS PC12 PD5 PG12 VSS PB7 PB8 VSS VDD

C VDDUSB PA14 PD0 PG9 PG13 PB4 PH3-BOOT0 PE3 VBAT

D PA12 PA13 PD1 PD4 PB3 PB5 PE4 PE6

PC14-OSC32
_IN

E PA10 PA11 PA15 PC10 PG11 PA9 PE5 PC13

PC15-
OSC32_OUT

PH1-OSC_
F PC8 PC7 PC9 PA8 PA6 PC2 PC0
OUT
PH0-OSC_IN

G PD14 PD15 PB15 PC6 PC5 PA0 PC3 PC1 NRST

H PB13 PB14 PB10 PE7 PA3 PA5 PA4 VREF+ VSSA

VSS
J VDD VSS
SMPS
PE10 PE8 PB1 PA1 PA2 VDDA

VDD VLX
K VDD11
SMPS SMPS
PE9 PB2 PB0 PA7 VDD VSS

MSv62645V2

1. The above figure shows the package top view.

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Figure 14. LQFP100_SMPS pinout

PH3-BOOT0
VDD11

PC10
PC12
PC11

PA14
PA15
VDD
VSS

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 VDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VSSSMPS
VDDSMPS
VLXSMPS
PB10
PE15
PE14
PE13
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PB0
VDD
VSS

VDD11
PB11
PE11
PA7
PA6
PA5
PA4

MSv62930V1

1. The above figure shows the package top view.

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Figure 15. LQFP100 pinout

PH3-BOOT0

PC10
PC12
PC11

PA14
PA15
VDD
VSS

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VSS
PB10
VCAP
PE15
PE14
PE13
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PB0
PC5
PC4
VDD
VSS

PE11
PA7
PA6
PA5
PA4
PA3

MSv62924V1

1. The above figure shows the package top view.

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Figure 16. UFBGA132 _SMPS ballout

1 2 3 4 5 6 7 8 9 10 11 12

A PE5 PE3 PE1 PB9 PB6 PG12 PD6 PD5 PD2 PC11 PA15 VDDUSB

PH3-
B VBAT PE4 PE2 VDD11
BOOT0
PB4 PG9 PD4 PD1 PC12 PC10 PA12

PC14-
C OSC32 PE6 PC13 PE0 PB8 PB3 PG10 PD3 PD0 PA13 PA14 PA11
_IN

PC15-
D OSC32_ PF0 PF3 VDD PB7 PB5 PD7 VDDIO2 VDD PA9 PA10 PA8
OUT

E PF2 PF1 PF4 VSS VSS PC7 PC9 PC8

PH0-
F OSC_IN
PF5 PC2 PC3 VSS VDD PG6 PG7 PC6 PG8

PH1-OSC
G _OUT
NRST PC1 PA1 VDD VSS PG4 PG2 PG3 PG5

OPAMP1
H VSSA PC0
_VINM
VSS VSS PD14 PD13 PD15

J VREF+ PA0 PC5 VDD PF14 PE8 PE10 PE12 VDD PD9 PD11 PD12

K VDDA PA2 PA7 PB2 PF11 PG1 PE7 PE14 PB10 PB13 PB14 PB15

VSS
L PA3 PA6 PA4 PB1 PF12 PF15 PE11 PE15 PB11
SMPS
PB12 PD8

OPAMP2 VDD VLX

M PA5
_VINM
PC4 PB0 PF13 PG0 PE9 PE13
SMPS SMPS
VDD11 PD10

MSv62931V2

1. The above figure shows the package top view.

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STM32U585xx Pinout, pin description and alternate functions

Figure 17. UFBGA132 ballout

1 2 3 4 5 6 7 8 9 10 11 12

A PE5 PE3 PE1 PB9 PB6 PG12 PD6 PD5 PD2 PC11 PA15 VDDUSB

PH3-
B VBAT PE4 PE2 PG15
BOOT0
PB4 PG9 PD4 PD1 PC12 PC10 PA12

PC14-
C OSC32 PE6 PC13 PE0 PB8 PB3 PG10 PD3 PD0 PA13 PA14 PA11
_IN

PC15-
D OSC32_ PF0 PF3 VDD PB7 PB5 PD7 VDDIO2 VDD PA9 PA10 PA8
OUT

E PF2 PF1 PF4 VSS VSS PC7 PC9 PC8

PH0-
F OSC_IN
PF5 PC2 PC3 VSS VDD PG6 PG7 PC6 PG8

PH1-
G OSC_ NRST PC1 PA1 VDD VSS PG4 PG2 PG3 PG5
OUT

OPAMP1
H VSSA PC0
_VINM
VSS VSS PD14 PD13 PD15

J VREF+ PA0 PC5 VDD PF14 PE8 PE10 PE12 VDD PD9 PD11 PD12

K VDDA PA2 PA7 PB2 PF11 PG1 PE7 PE14 PB10 PB13 PB14 PB15

L PA3 PA6 PA4 PB1 PF12 PF15 PE11 PE15 PB11 VCAP PB12 PD8

OPAMP2
M PA5
_VINM
PC4 PB0 PF13 PG0 PE9 PE13 PG14 PG13 PG11 PD10

MSv62925V2

1. The above figure shows the package top view.

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Figure 18. LQFP144 _SMPS pinout

PH3-BOOT0

VDDIO2
VDD11

PG15

PG14
PG13
PG12
PG10

PC12

PC10
PC11

PA15
PA14
VDD

VDD
VSS

VSS

PG9

VSS
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
119
118
117
116
115
114
113
112

110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDIO2
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VSSA 30 79 PD10
VREF+ 31 78 PD9
VDDA 32 77 PD8
PA0 33 76 PB15
PA1 34 75 PB14
PA2 35 74 PB13
PA3 36 73 VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VDD

PB0
PB1
PB2

PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10

VLXSMPS
VDDSMPS
VSSSMPS

VSS
PA4
PA5
PA6
PA7

PF11

PE11

PB11

VDD11

MSv62932V1

1. The above figure shows the package top view.

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STM32U585xx Pinout, pin description and alternate functions

Figure 19. LQFP144 pinout

PH3-BOOT0

VDDIO2
PG15

PG14
PG13
PG12

PG10

PC12

PC10
PG11

PC11

PA15
PA14
VDD

VDD
VSS

VSS

PG9

VSS
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
119
118
117
116
115
114
113
112

110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDIO2
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VSSA 30 79 PD10
VREF- 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS

PG0
PG1
VDD

PC4
PC5
PB0
PB1
PB2

PF12
VSS
VDD
PF13
PF14
PF15

PE7
PE8
PE9
VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10
VCAP
VSS
VDD
PA3

PA4
PA5
PA6
PA7

PF11

PE11

MSv62926V1

1. The above figure shows the package top view.

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Figure 20. UFBGA169_SMPS ballout

1 2 3 4 5 6 7 8 9 10 11 12 13

A PE2 PI6 VDD VDD11 PG15 VDDIO2 PG9 VDD PC11 PA15 VDD PI1 PH15

B VDD VSS PI5 VSS PB6 PB4 PD6 VSS PD0 PI4 VSS PI0 PH12

PH3-
C VBAT PE4 PI7 PE1
BOOT0
PB5 PG10 PD4 PC10 PA14 PH14 PH13 PH10

PC14-
D OSC32 PE5 PE3 PE0 PB9 PB3 PD7 PD3 PH11 PI3 PI2 PH8 VDD
_IN

PC15-
E OSC32_ PF0 PC13 PE6 PB8 PG12 PD5 PC12 PH9 PH4 PH6 VSS VDDUSB
OUT

F PF8 VSS PF1 PF2 PB7 PD1 PD2 PH7 PH5 PH2 PA10 PA13 PA12

G VDD PF7 PF9 PF5 PF3 PF4 PA8 PG7 PC9 PC8 PA9 PC7 PA11

PH0- OPAMP2
H OSC_IN
VSS NRST PF10
_VINM
PF6 PG1 PE10 PG8 PG6 PG4 VDDIO2 PC6

PH1-
J OSC_ PC0 PC1 PC2 PA7 PG0 PE9 PG3 PG5 PD14 PD15 VSS VDD
OUT

K PC3 VSSA PA0 PA5 PB0 PF12 PE8 PE14 PB10 PD12 PD10 PD13 PG2

L VREF+ VDDA PA1 PC4 PB2 PF14 PE7 PE13 PB11 PB12 PB15 PD8 PD9

OPAMP1 VSS
M _VINM
PA2 VSS PC5 PF11 PF13 VSS PE11 PE15
SMPS
VSS PB14 PD11

VLX VDD
N PA4 PA3 VDD PA6 PB1 PF15 VDD PE12
SMPS SMPS
VDD11 VDD PB13

MSv62933V3

1. The above figure shows the package top view.

104/334 DS13086 Rev 6

STM32U585xx Pinout, pin description and alternate functions

Figure 21. UFBGA169 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13

A PE2 PI6 VDD VCAP PG15 VDDIO2 PG9 VDD PC11 PA15 VDD PI1 PH15

B VDD VSS PI5 VSS PB6 PB4 PD6 VSS PD0 PI4 VSS PI0 PH12

PH3-
C VBAT PE4 PI7 PE1
BOOT0
PB5 PG10 PD4 PC10 PA14 PH14 PH13 PH10

PC14-
D OSC32_ PE5 PE3 PE0 PB9 PB3 PD7 PD3 PH11 PI3 PI2 PH8 VDD
IN

PC15-
E OSC32_ PF0 PC13 PE6 PB8 PG12 PD5 PC12 PH9 PH4 PH6 VSS VDDUSB
OUT

F PF8 VSS PF1 PF2 PB7 PD1 PD2 PH7 PH5 PH2 PA10 PA13 PA12

G VDD PF7 PF9 PF5 PF3 PF4 PA8 PG7 PC9 PC8 PA9 PC7 PA11

PH0- OPAMP2
H OSC_IN
VSS NRST PF10
_VINM
PF6 PG1 PE10 PG8 PG6 PG4 VDDIO2 PC6

PH1-
J OSC_ PC0 PC1 PC2 PA7 PG0 PE9 PG3 PG5 PD14 PD15 VSS VDD
OUT

K PC3 VSSA PA0 PA5 PB0 PF12 PE8 PE14 PB10 PD12 PD10 PD13 PG2

L VREF+ VDDA PA1 PC4 PB2 PF14 PE7 PE13 PB11 PB12 PB15 PD8 PD9

OPAMP1
M _VINM
PA2 VSS PC5 PF11 PF13 VSS PE11 PE15 PG11 VSS PB14 PD11

N PA4 PA3 VDD PA6 PB1 PF15 VDD PE12 PG14 PG13 VCAP VDD PB13

MSv62927V3

1. The above figure shows the package top view.

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147
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4.2 Pin description

Table 26. Legend/abbreviations used in the pinout table
Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during
Pin name
and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/output pin
FT 5V-tolerant I/O
TT 3.6V-tolerant I/O
Bidirectional reset pin with embedded weak pull-up
RST
resistor
Option for TT or FT I/Os(1)
_a I/O, with analog switch function supplied by VDDA
_c I/O with USB Type-C power delivery function
I/O structure
_d I/O with USB Type-C power delivery dead battery function
_f I/O, Fm+ capable
_h I/O with high-speed low-voltage mode
_s I/O supplied only by VDDIO2
_t I/O with a function supported in VBAT mode
_u I/O, with USB function supplied by VDDUSB
_v I/O very high-speed capable
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a.

106/334 DS13086 Rev 6

 STM32U585xx
Table 27. STM32U585xx pin definitions(1)
Pin number

I/O structure
UFQFPN48 SMPS

UFBGA132 SMPS

UFBGA169 SMPS
WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

TRACECLK, TIM3_ETR,
SAI1_CK1, TSC_G7_IO1,
- - - 1 B3 1 A1 - - 1 B3 1 A1 PE2 I/O FT_ha - -
LPGPIO1_P14, FMC_A23,
SAI1_MCLK_A, EVENTOUT
TRACED0, TIM3_CH1,
OCTOSPIM_P1_DQS, TAMP_IN6/
FT_
- - C15 2 A2 2 D3 - - 2 A2 2 D3 PE3 I/O - TSC_G7_IO2, LPGPIO1_P15, TAMP_
DS13086 Rev 6

hat
FMC_A19, SAI1_SD_B, OUT3
EVENTOUT
TRACED1, TIM3_CH2, SAI1_D2, WKUP1,

Pinout, pin description and alternate functions

FT_ MDF1_SDI3, TSC_G7_IO3, TAMP_IN7/
- - D14 3 B2 3 C2 - - 3 B2 3 C2 PE4 I/O -
hat DCMI_D4/PSSI_D4, FMC_A20, TAMP_
SAI1_FS_A, EVENTOUT OUT8
TRACED2, TIM3_CH3, SAI1_CK2, WKUP2,
FT_ MDF1_CKI3, TSC_G7_IO4, TAMP_IN8/
- - E13 4 A1 4 D2 - - 4 A1 4 D2 PE5 I/O -
hat DCMI_D6/PSSI_D6, FMC_A21, TAMP_
SAI1_SCK_A, EVENTOUT OUT7
WKUP3,
TRACED3, TIM3_CH4, SAI1_D1,
TAMP_IN3/
- - D16 5 C2 5 E4 - - 5 C2 5 E4 PE6 I/O FT_ht - DCMI_D7/PSSI_D7, FMC_A22,
TAMP_
SAI1_SD_A, EVENTOUT
OUT6
1 1 C17 6 B1 6 C1 1 1 6 B1 6 C1 VBAT S - - - -
- - - - - - F2 - - - - - F2 VSS S - - - -
107/334
 Table 27. STM32U585xx pin definitions(1) (continued)
108/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

WKUP2,
RTC_TS/
(2) RTC_OUT1,
2 2 E15 7 C3 7 E3 2 2 7 C3 7 E3 PC13 I/O FT (3) EVENTOUT
TAMP_IN1/
TAMP_
OUT2
PC14- (2)
DS13086 Rev 6

3 3 D18 8 C1 8 D1 3 3 8 C1 8 D1 OSC32_IN I/O FT (3) EVENTOUT OSC32_IN

(PC14)
PC15- (2)
OSC32_
4 4 E17 9 D1 9 E1 4 4 9 D1 9 E1 OSC32_OUT I/O FT (3) EVENTOUT
OUT
(PC15)
I2C2_SDA, OCTOSPIM_P2_IO0,
- - - - D2 10 E2 - - - D2 10 E2 PF0 I/O FT_fh - -
FMC_A0, EVENTOUT
I2C2_SCL, OCTOSPIM_P2_IO1,
- - - - E2 11 F3 - - - E2 11 F3 PF1 I/O FT_fh - -
FMC_A1, EVENTOUT
LPTIM3_CH2, I2C2_SMBA,
- - - - E1 12 F4 - - - E1 12 F4 PF2 I/O FT_h - OCTOSPIM_P2_IO2, FMC_A2, WKUP8
EVENTOUT
LPTIM3_IN1, OCTOSPIM_P2_IO3,
- - - - D3 13 G5 - - - D3 13 G5 PF3 I/O FT_h - -
FMC_A3, EVENTOUT
LPTIM3_ETR,
- - - - E3 14 G6 - - - E3 14 G6 PF4 I/O FT_hv - OCTOSPIM_P2_CLK, FMC_A4, -

STM32U585xx
EVENTOUT
LPTIM3_CH1,
- - - - F2 15 G4 - - - F2 15 G4 PF5 I/O FT_hv - OCTOSPIM_P2_NCLK, FMC_A5, -
EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

- - - 10 F6 16 H2 - - 10 F6 16 H2 VSS S - - - -
- - - 11 F7 17 G1 - - 11 F7 17 G1 VDD S - - - -
TIM5_ETR, TIM5_CH1,
DCMI_D12/PSSI_D12,
- - - - - 18 H6 - - - - 18 H6 PF6 I/O FT_h - OCTOSPIM_P2_NCS, -
OCTOSPIM_P1_IO3, SAI1_SD_B,
EVENTOUT
DS13086 Rev 6

TIM5_CH2, FDCAN1_RX,
- - - - - 19 G2 - - - - 19 G2 PF7 I/O FT_h - OCTOSPIM_P1_IO2, -
SAI1_MCLK_B, EVENTOUT

Pinout, pin description and alternate functions

TIM5_CH3, PSSI_D14,
- - - - - 20 F1 - - - - 20 F1 PF8 I/O FT_h - FDCAN1_TX, OCTOSPIM_P1_IO0, -
SAI1_SCK_B, EVENTOUT
TIM5_CH4, PSSI_D15,
- - - - - 21 G3 - - - - 21 G3 PF9 I/O FT_h - OCTOSPIM_P1_IO1, SAI1_FS_B, -
TIM15_CH1, EVENTOUT
OCTOSPIM_P1_CLK, PSSI_D15,
MDF1_CCK1,
- - - - - 22 H4 - - - - 22 H4 PF10 I/O FT_hv - -
DCMI_D11/PSSI_D11, SAI1_D3,
TIM15_CH2, EVENTOUT
PH0-OSC_IN
5 5 F18 12 F1 23 H1 5 5 12 F1 23 H1 I/O FT - EVENTOUT OSC_IN
(PH0)
PH1-OSC_OUT
6 6 F16 13 G1 24 J1 6 6 13 G1 24 J1 I/O FT - EVENTOUT OSC_OUT
(PH1)
7 7 G17 14 G2 25 H3 7 7 14 G2 25 H3 NRST I/O RST - - -
109/334
 Table 27. STM32U585xx pin definitions(1) (continued)
110/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

LPTIM1_IN1, OCTOSPIM_P1_IO7,
I2C3_SCL(boot), SPI2_RDY,
FT_ ADC1_IN1,
- 8 F14 15 H2 26 J2 - 8 15 H2 26 J2 PC0 I/O - MDF1_SDI4, LPUART1_RX,
fha ADC4_IN1
SDMMC1_D5, SAI2_FS_A,
LPTIM2_IN1, EVENTOUT
TRACED0, LPTIM1_CH1,
SPI2_MOSI, I2C3_SDA(boot),
DS13086 Rev 6

FT_ MDF1_CKI4, LPUART1_TX, ADC1_IN2,

- 9 G15 16 G3 27 J3 - 9 16 G3 27 J3 PC1 I/O -
fhav OCTOSPIM_P1_IO4, ADC4_IN2
SDMMC2_CK, SAI1_SD_A,
EVENTOUT
LPTIM1_IN2, SPI2_MISO,
ADC1_IN3,
- 10 F12 17 F3 28 J4 - 10 17 F3 28 J4 PC2 I/O FT_ha - MDF1_CCK1, OCTOSPIM_P1_IO5,
ADC4_IN3
LPGPIO1_P5, EVENTOUT
LPTIM1_ETR, LPTIM3_CH1,
SAI1_D1, SPI2_MOSI, ADC1_IN4,
- 11 G13 18 F4 29 K1 - 11 18 F4 29 K1 PC3 I/O FT_ha -
OCTOSPIM_P1_IO6, SAI1_SD_A, ADC4_IN4
LPTIM2_ETR, EVENTOUT
8 12 H18 19 H1 30 K2 8 12 19 H1 30 K2 VSSA S - - - -
- - - - - - - - - 20 - 31 - VREF- S - - - -
VREFBUF_
- - H16 20 J1 31 L1 - - 21 J1 32 L1 VREF+ S - - -
OUT
9 13 J17 21 K1 32 L2 9 13 22 K1 33 L2 VDDA S - - - -

STM32U585xx
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

OPAMP1_
TIM2_CH1, TIM5_CH1, TIM8_ETR, VINP,
SPI3_RDY, USART2_CTS, ADC1_IN5,
FT_
10 14 G11 22 J2 33 K3 10 14 23 J2 34 K3 PA0 I/O - UART4_TX, OCTOSPIM_P2_NCS, WKUP1,
hat
SDMMC2_CMD, AUDIOCLK, TAMP_IN2/
TIM2_ETR, EVENTOUT TAMP_
OUT1
DS13086 Rev 6

OPAMP1_
- - - - H3 - M1 - - - H3 - M1 I TT - - -
VINM
OPAMP1_
LPTIM1_CH2, TIM2_CH2,
VINM,

Pinout, pin description and alternate functions

TIM5_CH2, I2C1_SMBA,
ADC1_IN6,
FT_ SPI1_SCK, USART2_RTS_DE,
11 15 J13 23 G4 34 L3 11 15 24 G4 35 L3 PA1 I/O - WKUP3,
hat UART4_RX, OCTOSPIM_P1_DQS,
TAMP_IN5/
LPGPIO1_P0, TIM15_CH1N,
TAMP_
EVENTOUT
OUT4
TIM2_CH3, TIM5_CH3, SPI1_RDY, COMP1_
USART2_TX(boot), LPUART1_TX, INP3,
12 16 J15 24 K2 35 M2 12 16 25 K2 36 M2 PA2 I/O FT_ha - OCTOSPIM_P1_NCS, ADC1_IN7,
UCPD1_FRSTX1, TIM15_CH1, WKUP4/
EVENTOUT LSCO
TIM2_CH4, TIM5_CH4, SAI1_CK1,
OPAMP1_
USART2_RX(boot), LPUART1_RX,
TT_ VOUT,
13 17 H10 25 L1 36 N2 13 17 26 L1 37 N2 PA3 I/O - OCTOSPIM_P1_CLK,
hav ADC1_IN8,
LPGPIO1_P1, SAI1_MCLK_A,
WKUP5
TIM15_CH2, EVENTOUT
- 18 K18 26 G7 37 M3 - 18 27 G7 38 M3 VSS S - - - -
111/334

- 19 K16 27 G6 38 N3 - 19 28 G6 39 N3 VDD S - - - -
 Table 27. STM32U585xx pin definitions(1) (continued)
112/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

OCTOSPIM_P1_NCS,
ADC1_IN9,
SPI1_NSS(boot), SPI3_NSS,
ADC4_IN9,
USART2_CK,
14 20 H14 28 L3 39 N1 14 20 29 L3 40 N1 PA4 I/O TT_ha - DAC1_
DCMI_HSYNC/PSSI_DE,
OUT1,
SAI1_FS_B, LPTIM2_CH1,
WKUP2
EVENTOUT
ADC1_IN10,
CSLEEP, TIM2_CH1, TIM2_ETR,
DS13086 Rev 6

ADC4_IN10,
TIM8_CH1N, PSSI_D14,
15 21 H12 29 M1 40 K4 15 21 30 M1 41 K4 PA5 I/O TT_a - DAC1_
SPI1_SCK(boot), USART3_RX,
OUT2,
LPTIM2_ETR, EVENTOUT
WKUP6
CDSTOP, TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
OPAMP2_
DCMI_PIXCLK/PSSI_PDCK,
VINP,
SPI1_MISO(boot), USART3_CTS,
16 22 F10 30 L2 41 N4 16 22 31 L2 42 N4 PA6 I/O FT_ha - ADC1_IN11,
LPUART1_CTS,
ADC4_IN11,
OCTOSPIM_P1_IO3,
WKUP7
LPGPIO1_P2, TIM16_CH1,
EVENTOUT
- - - - M2 - H5 - - - M2 - H5 OPAMP2_VINM I TT - - -
SRDSTOP, TIM1_CH1N,
OPAMP2_
TIM3_CH2, TIM8_CH1N,
VINM,
FT_ I2C3_SCL, SPI1_MOSI(boot),
17 23 K14 31 K3 42 J5 17 23 32 K3 43 J5 PA7 I/O - ADC1_IN12,
fha USART3_TX, OCTOSPIM_P1_IO2,
ADC4_IN20,

STM32U585xx
LPTIM2_CH2, TIM17_CH1,
WKUP8
EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

COMP1_
USART3_TX, OCTOSPIM_P1_IO7, INM2,
- - - - M3 - L4 - 24 33 M3 44 L4 PC4 I/O FT_ha -
EVENTOUT ADC1_IN13,
ADC4_IN22
COMP1_
INP1,
ADC1_IN14,
DS13086 Rev 6

TIM1_CH4N, SAI1_D3, PSSI_D15, ADC4_IN23,

- - G9 - J3 - M4 - 25 34 J3 45 M4 PC5 I/O FT_at -
USART3_RX, EVENTOUT WKUP5,
TAMP_IN4/
TAMP_

Pinout, pin description and alternate functions

OUT5
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, LPTIM3_CH1, OPAMP2_
SPI1_NSS, USART3_CK, VOUT,
18 24 K12 32 M4 43 K5 18 26 35 M4 46 K5 PB0 I/O TT_ha -
OCTOSPIM_P1_IO1, ADC1_IN15,
LPGPIO1_P9, COMP1_OUT, ADC4_IN18
AUDIOCLK, EVENTOUT
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LPTIM3_CH2, COMP1_
MDF1_SDI0, USART3_RTS_DE, INM1,
19 25 J11 33 L4 44 N5 19 27 36 L4 47 N5 PB1 I/O FT_ha - LPUART1_RTS_DE, ADC1_IN16,
OCTOSPIM_P1_IO0, ADC4_IN19,
LPGPIO1_P3, LPTIM2_IN1, WKUP4
EVENTOUT
113/334
 Table 27. STM32U585xx pin definitions(1) (continued)
114/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

LPTIM1_CH1, TIM8_CH4N, COMP1_

I2C3_SMBA, SPI1_RDY, INP2,
FT_
- 26 K10 34 K4 45 L5 20 28 37 K4 48 L5 PB2 I/O - MDF1_CKI0, ADC1_IN17,
hat
OCTOSPIM_P1_DQS, WKUP1,
UCPD1_FRSTX1, EVENTOUT RTC_OUT2
OCTOSPIM_P1_NCLK,
- - - - K5 46 M5 - - - K5 49 M5 PF11 I/O FT_hv - DCMI_D12/PSSI_D12, -
DS13086 Rev 6

LPTIM4_IN1, EVENTOUT
OCTOSPIM_P2_DQS, FMC_A6,
- - - - L5 47 K6 - - - L5 50 K6 PF12 I/O FT_h - -
LPTIM4_ETR, EVENTOUT
- - - - - 48 M7 - - - - 51 M7 VSS S - - - -
- - - - - 49 N7 - - - - 52 N7 VDD S - - - -
I2C4_SMBA, UCPD1_FRSTX2,
- - - - M5 50 M6 - - - M5 53 M6 PF13 I/O FT_h - FMC_A7, LPTIM4_OUT, -
EVENTOUT
FT_ I2C4_SCL, TSC_G8_IO1, FMC_A8,
- - - - J5 51 L6 - - - J5 54 L6 PF14 I/O - ADC4_IN5
fha EVENTOUT
FT_ I2C4_SDA, TSC_G8_IO2,
- - - - L6 52 N6 - - - L6 55 N6 PF15 I/O - ADC4_IN6
fha FMC_A9, EVENTOUT
OCTOSPIM_P2_IO4,
- - - - M6 53 J6 - - - M6 56 J6 PG0 I/O FT_ha - TSC_G8_IO3, FMC_A10, ADC4_IN7
EVENTOUT

STM32U585xx
OCTOSPIM_P2_IO5,
- - - - K6 54 H7 - - - K6 57 H7 PG1 I/O FT_ha - TSC_G8_IO4, FMC_A11, ADC4_IN8
EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

TIM1_ETR, MDF1_SDI2, FMC_D4,

- - H8 35 K7 55 L7 - - 38 K7 58 L7 PE7 I/O FT_h - WKUP6
SAI1_SD_B, EVENTOUT
TIM1_CH1N, MDF1_CKI2,
- - J9 36 J6 56 K7 - - 39 J6 59 K7 PE8 I/O FT_h - FMC_D5, SAI1_SCK_B, WKUP7
EVENTOUT
TIM1_CH1, ADF1_CCK0,
MDF1_CCK0,
DS13086 Rev 6

- - K8 37 M7 57 J7 - - 40 M7 60 J7 PE9 I/O FT_hv - -

OCTOSPIM_P1_NCLK, FMC_D6,
SAI1_FS_B, EVENTOUT
- - - - - 58 - - - - - 61 - VSS S - - - -

Pinout, pin description and alternate functions

- - - - J4 59 - - - - J4 62 - VDD S - - - -
TIM1_CH2N, ADF1_SDI0,
FT_ MDF1_SDI4, TSC_G5_IO1,
- - J7 38 J7 60 H8 - - 41 J7 63 H8 PE10 I/O - -
hav OCTOSPIM_P1_CLK, FMC_D7,
SAI1_MCLK_B, EVENTOUT
TIM1_CH2, SPI1_RDY,
MDF1_CKI4, TSC_G5_IO2,
- - - 39 L7 61 M8 - - 42 L7 64 M8 PE11 I/O FT_ha - -
OCTOSPIM_P1_NCS, FMC_D8,
EVENTOUT
TIM1_CH3N, SPI1_NSS,
MDF1_SDI5, TSC_G5_IO3,
- - - 40 J8 62 N8 - - 43 J8 65 N8 PE12 I/O FT_ha - -
OCTOSPIM_P1_IO0, FMC_D9,
EVENTOUT
TIM1_CH3, SPI1_SCK,
MDF1_CKI5, TSC_G5_IO4,
- - - 41 M8 63 L8 - - 44 M8 66 L8 PE13 I/O FT_ha - -
115/334

OCTOSPIM_P1_IO1, FMC_D10,
EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)
116/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

TIM1_CH4, TIM1_BKIN2,
- - - 42 K8 64 K8 - - 45 K8 67 K8 PE14 I/O FT_h - SPI1_MISO, OCTOSPIM_P1_IO2, -
FMC_D11, EVENTOUT
TIM1_BKIN, TIM1_CH4N,
- - - 43 L8 65 M9 - - 46 L8 68 M9 PE15 I/O FT_h - SPI1_MOSI, OCTOSPIM_P1_IO3, -
FMC_D12, EVENTOUT
TIM2_CH3, LPTIM3_CH1,
DS13086 Rev 6

I2C4_SCL, I2C2_SCL(boot),
SPI2_SCK, USART3_TX,
FT_
- 27 H6 44 K9 66 K9 21 29 47 K9 69 K9 PB10 I/O - LPUART1_RX, TSC_SYNC, WKUP8
fhv
OCTOSPIM_P1_CLK,
LPGPIO1_P4, COMP1_OUT,
SAI1_SCK_A, EVENTOUT
TIM2_CH4, I2C4_SDA,
I2C2_SDA(boot), SPI2_RDY,
- - - 45 L9 67 L9 - - - L9 - L9 PB11 I/O FT_fh - USART3_RX, LPUART1_TX, -
OCTOSPIM_P1_NCS,
COMP2_OUT, EVENTOUT
20 28 K6 46 M10 68 N9 - - - - - - VLXSMPS S - - - -
21 29 K4 47 M9 69 N10 - - - - - - VDDSMPS S - - - -
22 30 J5 48 L10 70 M10 - - - - - - VSSSMPS S - - - -
- - - - - - - 22 30 48 L10 70 N11 VCAP S - - - -

STM32U585xx
23 31 K2 49 M11 71 N11 - - - - - - VDD11 S - - - -
24 32 J3 50 E9 72 M11 23 31 49 E9 71 M11 VSS S - - - -
25 33 J1 51 D4 73 N12 24 32 50 D4 72 N12 VDD S - - - -
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

TIM1_BKIN, I2C2_SMBA,
SPI2_NSS(boot), MDF1_SDI1,
USART3_CK, LPUART1_RTS_DE,
FT_
- - - - L11 - L10 25 33 51 L11 73 L10 PB12 I/O - TSC_G1_IO1, -
hav
OCTOSPIM_P1_NCLK,
SAI2_FS_A, TIM15_BKIN,
EVENTOUT
DS13086 Rev 6

TIM1_CH1N, LPTIM3_IN1,
I2C2_SCL, SPI2_SCK(boot),
MDF1_CKI1, USART3_CTS,
26 34 H2 52 K10 74 N13 26 34 52 K10 74 N13 PB13 I/O FT_f - -
LPUART1_CTS, TSC_G1_IO2,

Pinout, pin description and alternate functions

SAI2_SCK_A, TIM15_CH1N,
EVENTOUT
TIM1_CH2N, LPTIM3_ETR,
TIM8_CH2N, I2C2_SDA,
SPI2_MISO(boot), MDF1_SDI2, UCPD1_
27 35 H4 53 K11 75 M12 27 35 53 K11 75 M12 PB14 I/O FT_fd -
USART3_RTS_DE, TSC_G1_IO3, DBCC2
SDMMC2_D0, SAI2_MCLK_A,
TIM15_CH1, EVENTOUT
RTC_REFIN, TIM1_CH3N,
LPTIM2_IN2, TIM8_CH3N,
UCPD1_
(4) SPI2_MOSI(boot), MDF1_CKI2,
28 36 G5 54 K12 76 L11 28 36 54 K12 76 L11 PB15 I/O FT_c CC2,
FMC_NBL1, SDMMC2_D1,
WKUP7
SAI2_SD_A, TIM15_CH2,
EVENTOUT
USART3_TX,
- - - 55 L12 77 L12 - - 55 L12 77 L12 PD8 I/O FT_h - DCMI_HSYNC/PSSI_DE, -
FMC_D13, EVENTOUT
117/334
 Table 27. STM32U585xx pin definitions(1) (continued)
118/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

LPTIM2_IN2, USART3_RX,
DCMI_PIXCLK/PSSI_PDCK,
- - - 56 J10 78 L13 - - 56 J10 78 L13 PD9 I/O FT_h - -
FMC_D14, SAI2_MCLK_A,
LPTIM3_IN1, EVENTOUT
LPTIM2_CH2, USART3_CK,
TSC_G6_IO1, FMC_D15,
- - - 57 M12 79 K11 - - 57 M12 79 K11 PD10 I/O FT_ha - -
SAI2_SCK_A, LPTIM3_ETR,
DS13086 Rev 6

EVENTOUT
I2C4_SMBA, USART3_CTS,
TSC_G6_IO2,
- - - 58 J11 80 M13 - - 58 J11 80 M13 PD11 I/O FT_ha - ADC4_IN15
FMC_CLE/FMC_A16, SAI2_SD_A,
LPTIM2_ETR, EVENTOUT
TIM4_CH1, I2C4_SCL,
FT_ USART3_RTS_DE, TSC_G6_IO3,
- - - 59 J12 81 K10 - - 59 J12 81 K10 PD12 I/O - ADC4_IN16
fha FMC_ALE/FMC_A17, SAI2_FS_A,
LPTIM2_IN1, EVENTOUT
TIM4_CH2, I2C4_SDA,
FT_ TSC_G6_IO4, LPGPIO1_P6,
- - - 60 H11 82 K12 - - 60 H11 82 K12 PD13 I/O - ADC4_IN17
fha FMC_A18, LPTIM4_IN1,
LPTIM2_CH1, EVENTOUT
- - - - - 83 J12 - - - - 83 J12 VSS S - - - -
- - - - - 84 J13 - - - - 84 J13 VDD S - - - -
TIM4_CH3, FMC_D0,

STM32U585xx
- - G1 61 H10 85 J10 - - 61 H10 85 J10 PD14 I/O FT_h - -
LPTIM3_CH1, EVENTOUT
TIM4_CH4, FMC_D1,
- - G3 62 H12 86 J11 - - 62 H12 86 J11 PD15 I/O FT_h - -
LPTIM3_CH2, EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

SPI1_SCK, FMC_A12,
- - - - G10 87 K13 - - - G10 87 K13 PG2 I/O FT_hs - -
SAI2_SCK_B, EVENTOUT
SPI1_MISO, FMC_A13,
- - - - G11 88 J8 - - - G11 88 J8 PG3 I/O FT_hs - -
SAI2_FS_B, EVENTOUT
SPI1_MOSI, FMC_A14,
- - - - G9 89 H11 - - - G9 89 H11 PG4 I/O FT_hs - -
SAI2_MCLK_B, EVENTOUT
DS13086 Rev 6

SPI1_NSS, LPUART1_CTS,
- - - - G12 90 J9 - - - G12 90 J9 PG5 I/O FT_hs - FMC_A15, SAI2_SD_B, -
EVENTOUT
OCTOSPIM_P1_DQS,

Pinout, pin description and alternate functions

I2C3_SMBA, SPI1_RDY,
- - - - F9 91 H10 - - - F9 91 H10 PG6 I/O FT_hs - -
LPUART1_RTS_DE,
UCPD1_FRSTX1, EVENTOUT
SAI1_CK1, I2C3_SCL,
OCTOSPIM_P2_DQS,
- - - - F10 92 G8 - - - F10 92 G8 PG7 I/O FT_fhs - MDF1_CCK0, LPUART1_TX, -
UCPD1_FRSTX2, FMC_INT,
SAI1_MCLK_A, EVENTOUT
I2C3_SDA, LPUART1_RX,
- - - - F12 93 H9 - - - F12 93 H9 PG8 I/O FT_fs - -
EVENTOUT
- - - - - 94 - - - - - 94 - VSS S - - - -
- - - - - 95 H12 - - - - 95 H12 VDDIO2 S - - - -
CSLEEP, TIM3_CH1, TIM8_CH1,
MDF1_CKI3, SDMMC1_D0DIR,
- 37 G7 63 F11 96 H13 - 37 63 F11 96 H13 PC6 I/O FT_a - TSC_G4_IO1, DCMI_D0/PSSI_D0, -
119/334

SDMMC2_D6, SDMMC1_D6,
SAI2_MCLK_A, EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)
120/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

CDSTOP, TIM3_CH2, TIM8_CH2,

MDF1_SDI3, SDMMC1_D123DIR,
TSC_G4_IO2, DCMI_D1/PSSI_D1,
- 38 F4 64 E10 97 G12 - 38 64 E10 97 G12 PC7 I/O FT_a - -
SDMMC2_D7, SDMMC1_D7,
SAI2_MCLK_B, LPTIM2_CH2,
EVENTOUT
SRDSTOP, TIM3_CH3, TIM8_CH3,
DS13086 Rev 6

TSC_G4_IO3, DCMI_D2/PSSI_D2,
- 39 F2 65 E12 98 G10 - 39 65 E12 98 G10 PC8 I/O FT_a - -
SDMMC1_D0, LPTIM3_CH1,
EVENTOUT
TRACED0, TIM8_BKIN2,
TIM3_CH4, TIM8_CH4,
- 40 F6 66 E11 99 G9 - 40 66 E11 99 G9 PC9 I/O FT_a - DCMI_D3/PSSI_D3, TSC_G4_IO4, -
OTG_FS_NOE, SDMMC1_D1,
LPTIM3_CH2, EVENTOUT
MCO, TIM1_CH1, SAI1_CK2,
SPI1_RDY, USART1_CK,
29 41 F8 67 D12 100 G7 29 41 67 D12 100 G7 PA8 I/O FT_hv - OTG_FS_SOF, TRACECLK, -
SAI1_SCK_A, LPTIM2_CH1,
EVENTOUT
TIM1_CH2, SPI2_SCK,
DCMI_D0/PSSI_D0, OTG_FS_
30 42 E11 68 D10 101 G11 30 42 68 D10 101 G11 PA9 I/O FT_u -
USART1_TX(boot), SAI1_FS_A, VBUS
TIM15_BKIN, EVENTOUT

STM32U585xx
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

CRS_SYNC, TIM1_CH3,
LPTIM2_IN2, SAI1_D1,
DCMI_D1/PSSI_D1,
31 43 E1 69 D11 102 F11 31 43 69 D11 102 F11 PA10 I/O FT_u - -
USART1_RX(boot), OTG_FS_ID,
SAI1_SD_A, TIM17_BKIN,
EVENTOUT
TIM1_CH4, TIM1_BKIN2,
DS13086 Rev 6

SPI1_MISO, USART1_CTS,
32 44 E3 70 C12 103 G13 32 44 70 C12 103 G13 PA11 I/O FT_u - -
FDCAN1_RX, OTG_FS_DM(boot),
EVENTOUT
TIM1_ETR, SPI1_MOSI,

Pinout, pin description and alternate functions

OCTOSPIM_P2_NCS,
33 45 D2 71 B12 104 F13 33 45 71 B12 104 F13 PA12 I/O FT_u - -
USART1_RTS_DE, FDCAN1_TX,
OTG_FS_DP(boot), EVENTOUT
JTMS/SWDIO, IR_OUT,
PA13 (JTMS/ (5)
34 46 D4 72 C10 105 F12 34 46 72 C10 105 F12 I/O FT OTG_FS_NOE, SAI1_SD_B, -
SWDIO)
EVENTOUT
- 47 - - - - - - 47 - - - - VSS S - - - -
- 48 C1 73 A12 106 E13 - 48 73 A12 106 E13 VDDUSB S - - - -
35 - B2 74 H4 107 E12 35 - 74 H4 107 E12 VSS S - - - -
36 - A1 75 D9 108 D13 36 - 75 D9 108 D13 VDD S - - - -
JTCK/SWCLK, LPTIM1_CH1,
PA14 (JTCK/ (5) I2C1_SMBA, I2C4_SMBA,
37 49 C3 76 C11 109 C10 37 49 76 C11 109 C10 I/O FT -
SWCLK) OTG_FS_SOF, SAI1_FS_B,
EVENTOUT
121/334
 Table 27. STM32U585xx pin definitions(1) (continued)
122/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

JTDI, TIM2_CH1, TIM2_ETR,

(4) USART2_RX, SPI1_NSS,
UCPD1_
38 50 E5 77 A11 110 A10 38 50 77 A11 110 A10 PA15 (JTDI) I/O FT_c (5) SPI3_NSS, USART3_RTS_DE,
CC1
UART4_RTS_DE, SAI2_FS_B,
EVENTOUT
TRACED1, LPTIM3_ETR,
ADF1_CCK1, SPI3_SCK,
DS13086 Rev 6

USART3_TX(boot), UART4_TX,
- 51 E7 78 B11 111 C9 - 51 78 B11 111 C9 PC10 I/O FT_a - -
TSC_G3_IO2, DCMI_D8/PSSI_D8,
LPGPIO1_P8, SDMMC1_D2,
SAI2_SCK_B, EVENTOUT
LPTIM3_IN1, ADF1_SDI0,
DCMI_D2/PSSI_D2,
OCTOSPIM_P1_NCS, SPI3_MISO,
- 52 A3 79 A10 112 A9 - 52 79 A10 112 A9 PC11 I/O FT_ha - USART3_RX(boot), UART4_RX, -
TSC_G3_IO3, DCMI_D4/PSSI_D4,
UCPD1_FRSTX2, SDMMC1_D3,
SAI2_MCLK_B, EVENTOUT
TRACED3, SPI3_MOSI,
USART3_CK, UART5_TX,
FT_
- 53 B4 80 B10 113 E8 - 53 80 B10 113 E8 PC12 I/O - TSC_G3_IO4, DCMI_D9/PSSI_D9, -
hav
LPGPIO1_P10, SDMMC1_CK,
SAI2_SD_B, EVENTOUT
TIM8_CH4N, SPI2_NSS,

STM32U585xx
- - C5 81 C9 114 B9 - - 81 C9 114 B9 PD0 I/O FT_h - FDCAN1_RX, FMC_D2, -
EVENTOUT
SPI2_SCK, FDCAN1_TX, FMC_D3,
- - D6 82 B9 115 F6 - - 82 B9 115 F6 PD1 I/O FT_h - -
EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

TRACED2, TIM3_ETR,
USART3_RTS_DE, UART5_RX,
- 54 A5 83 A9 116 F7 - 54 83 A9 116 F7 PD2 I/O FT - TSC_SYNC, DCMI_D11/PSSI_D11, -
LPGPIO1_P7, SDMMC1_CMD,
LPTIM4_ETR, EVENTOUT
SPI2_SCK, DCMI_D5/PSSI_D5,
SPI2_MISO, MDF1_SDI0,
DS13086 Rev 6

- - - 84 C8 117 D8 - - 84 C8 117 D8 PD3 I/O FT_hv - USART2_CTS, -

OCTOSPIM_P2_NCS, FMC_CLK,
EVENTOUT
SPI2_MOSI, MDF1_CKI0,

Pinout, pin description and alternate functions

USART2_RTS_DE,
- - D8 85 B8 118 C8 - - 85 B8 118 C8 PD4 I/O FT_h - -
OCTOSPIM_P1_IO4, FMC_NOE,
EVENTOUT
SPI2_RDY, USART2_TX,
- - B6 86 A8 119 E7 - - 86 A8 119 E7 PD5 I/O FT_h - OCTOSPIM_P1_IO5, FMC_NWE, -
EVENTOUT
- - - - - 120 B8 - - - - 120 B8 VSS S - - - -
- - - - - 121 A8 - - - - 121 A8 VDD S - - - -
SAI1_D1, DCMI_D10/PSSI_D10,
SPI3_MOSI, MDF1_SDI1,
- - - 87 A7 122 B7 - - 87 A7 122 B7 PD6 I/O FT_hv - USART2_RX, OCTOSPIM_P1_IO6, -
SDMMC2_CK, FMC_NWAIT,
SAI1_SD_A, EVENTOUT
123/334
 Table 27. STM32U585xx pin definitions(1) (continued)
124/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

MDF1_CKI1, USART2_CK,
OCTOSPIM_P1_IO7,
- - - 88 D7 123 D7 - - 88 D7 123 D7 PD7 I/O FT_h - SDMMC2_CMD, -
FMC_NCE/FMC_NE1,
LPTIM4_OUT, EVENTOUT
OCTOSPIM_P2_IO6,
SPI3_SCK(boot), USART1_TX,
DS13086 Rev 6

- - C7 - B7 124 A7 - - - B7 124 A7 PG9 I/O FT_hs - FMC_NCE/FMC_NE2, -

SAI2_SCK_A, TIM15_CH1N,
EVENTOUT
LPTIM1_IN1, OCTOSPIM_P2_IO7,
SPI3_MISO(boot), USART1_RX,
- - A7 - C7 125 C7 - - - C7 125 C7 PG10 I/O FT_hs - -
FMC_NE3, SAI2_FS_A,
TIM15_CH1, EVENTOUT
LPTIM1_IN2, OCTOSPIM_P1_IO5,
SPI3_MOSI, USART1_CTS,
- - E9 - - - - - - - M11 126 M10 PG11 I/O FT_hs - -
SAI2_MCLK_A, TIM15_CH2,
EVENTOUT
LPTIM1_ETR,
OCTOSPIM_P2_NCS,
- - B8 - A6 126 E6 - - - A6 127 E6 PG12 I/O FT_hs - SPI3_NSS(boot), -
USART1_RTS_DE, FMC_NE4,
SAI2_SD_A, EVENTOUT
I2C1_SDA, SPI3_RDY,

STM32U585xx
- - C9 - - 127 - - - - M10 128 N10 PG13 I/O FT_fhs - USART1_CK, FMC_A24, -
EVENTOUT
LPTIM1_CH2, I2C1_SCL,
- - A9 - - 128 - - - - M9 129 N9 PG14 I/O FT_fhs - -
FMC_A25, EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

- - B10 - H9 129 - - - - H9 130 - VSS S - - - -

- - A11 - D8 130 A6 - - - D8 131 A6 VDDIO2 S - - - -
LPTIM1_CH1, I2C1_SMBA,
- - - - - 131 A5 - - - B4 132 A5 PG15 I/O FT_hs - OCTOSPIM_P2_DQS, -
DCMI_D13/PSSI_D13, EVENTOUT
JTDO/TRACESWO, TIM2_CH2,
DS13086 Rev 6

LPTIM1_CH1, ADF1_CCK0,
PB3
I2C1_SDA, SPI1_SCK, SPI3_SCK, COMP2_
39 55 D10 89 C6 132 D6 39 55 89 C6 133 D6 (JTDO/TRACES I/O FT_fa -
USART1_RTS_DE, CRS_SYNC, INM2
WO)
LPGPIO1_P11, SDMMC2_D2,

Pinout, pin description and alternate functions

SAI1_SCK_B, EVENTOUT
NJTRST, LPTIM1_CH2, TIM3_CH1,
ADF1_SDI0, I2C3_SDA,
SPI1_MISO, SPI3_MISO,
USART1_CTS, UART5_RTS_DE,
(5) COMP2_
40 56 C11 90 B6 133 B6 40 56 90 B6 134 B6 PB4 (NJTRST) I/O FT_fa TSC_G2_IO1,
INP1
DCMI_D12/PSSI_D12,
LPGPIO1_P12, SDMMC2_D3,
SAI1_MCLK_B, TIM17_BKIN,
EVENTOUT
LPTIM1_IN1, TIM3_CH2,
OCTOSPIM_P1_NCLK,
I2C1_SMBA, SPI1_MOSI,
UCPD1_
FT_ SPI3_MOSI(boot), USART1_CK,
41 57 D12 91 D6 134 C6 41 57 91 D6 135 C6 PB5 I/O - DBCC1,
havd UART5_CTS, TSC_G2_IO2,
WKUP6
DCMI_D10/PSSI_D10,
COMP2_OUT, SAI1_SD_B,
125/334

TIM16_BKIN, EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)
126/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

LPTIM1_ETR, TIM4_CH1,
TIM8_BKIN2, I2C1_SCL(boot),
COMP2_
I2C4_SCL, MDF1_SDI5,
42 58 A13 92 A5 135 B5 42 58 92 A5 136 B5 PB6 I/O FT_fa - INP2,
USART1_TX, TSC_G2_IO3,
WKUP3
DCMI_D5/PSSI_D5, SAI1_FS_B,
TIM16_CH1N, EVENTOUT
LPTIM1_IN2, TIM4_CH2,
DS13086 Rev 6

TIM8_BKIN, I2C1_SDA(boot),
I2C4_SDA, MDF1_CKI5, COMP2_
FT_ USART1_RX, UART4_CTS, INM1,
43 59 B12 93 D5 136 F5 43 59 93 D5 137 F5 PB7 I/O -
fhav TSC_G2_IO4, PVD_IN,
DCMI_VSYNC/PSSI_RDY, WKUP4
FMC_NL, TIM17_CH1N,
EVENTOUT
44 60 C13 94 B5 137 C5 44 60 94 B5 138 C5 PH3-BOOT0 I/O FT - EVENTOUT -
TIM4_CH3, SAI1_CK1, I2C1_SCL,
MDF1_CCK0, SPI3_RDY,
SDMMC1_CKIN,
45 61 B14 95 C5 138 E5 45 61 95 C5 139 E5 PB8 I/O FT_f - FDCAN1_RX(boot), WKUP5
DCMI_D6/PSSI_D6, SDMMC2_D4,
SDMMC1_D4, SAI1_MCLK_A,
TIM16_CH1, EVENTOUT
IR_OUT, TIM4_CH4, SAI1_D2,
I2C1_SDA, SPI2_NSS,

STM32U585xx
SDMMC1_CDIR,
- - A15 96 A4 139 D5 46 62 96 A4 140 D5 PB9 I/O FT_f - FDCAN1_TX(boot), -
DCMI_D7/PSSI_D7, SDMMC2_D5,
SDMMC1_D5, SAI1_FS_A,
TIM17_CH1, EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

TIM4_ETR, DCMI_D2/PSSI_D2,
- - - 97 C4 140 D4 - - 97 C4 141 D4 PE0 I/O FT_h - LPGPIO1_P13, FMC_NBL0, -
TIM16_CH1, EVENTOUT
DCMI_D3/PSSI_D3, FMC_NBL1,
- - - - A3 141 C4 - - 98 A3 142 C4 PE1 I/O FT_h - -
TIM17_CH1, EVENTOUT
- - - - - - - - - - - - A4 VCAP S - - - -
DS13086 Rev 6

46 62 A17 98 B4 142 A4 - - - - - - VDD11 S - - - -

47 63 B16 99 E4 143 B4 47 63 99 E4 143 B4 VSS S - - - -
48 64 B18 100 J9 144 A3 48 64 100 J9 144 A3 VDD S - - - -

Pinout, pin description and alternate functions

- - - - - - B11 - - - - - B11 VSS S - - - -
- - - - - - F10 - - - - - F10 PH2 I/O FT_h - OCTOSPIM_P1_IO4, EVENTOUT -
I2C2_SCL, OCTOSPIM_P2_DQS,
- - - - - - E10 - - - - - E10 PH4 I/O FT_fh - -
PSSI_D14, EVENTOUT
I2C2_SDA,
- - - - - - F9 - - - - - F9 PH5 I/O FT_f - DCMI_PIXCLK/PSSI_PDCK, -
EVENTOUT
I2C2_SMBA, OCTOSPIM_P2_CLK,
- - - - - - E11 - - - - - E11 PH6 I/O FT_hv - -
DCMI_D8/PSSI_D8, EVENTOUT
FT_ I2C3_SCL, OCTOSPIM_P2_NCLK,
- - - - - - F8 - - - - - F8 PH7 I/O - -
fhv DCMI_D9/PSSI_D9, EVENTOUT
I2C3_SDA, OCTOSPIM_P2_IO3,
- - - - - - D12 - - - - - D12 PH8 I/O FT_fh - DCMI_HSYNC/PSSI_DE, -
EVENTOUT
127/334
 Table 27. STM32U585xx pin definitions(1) (continued)
128/334

Pinout, pin description and alternate functions

Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

I2C3_SMBA, OCTOSPIM_P2_IO4,
- - - - - - E9 - - - - - E9 PH9 I/O FT_h - -
DCMI_D0/PSSI_D0, EVENTOUT
TIM5_CH1, OCTOSPIM_P2_IO5,
- - - - - - C13 - - - - - C13 PH10 I/O FT_h - -
DCMI_D1/PSSI_D1, EVENTOUT
TIM5_CH2, OCTOSPIM_P2_IO6,
- - - - - - D9 - - - - - D9 PH11 I/O FT_h - -
DCMI_D2/PSSI_D2, EVENTOUT
DS13086 Rev 6

TIM5_CH3, TIM8_CH4N,
- - - - - - B13 - - - - - B13 PH12 I/O FT_h - OCTOSPIM_P2_IO7, -
DCMI_D3/PSSI_D3, EVENTOUT
TIM8_CH1N, FDCAN1_TX,
- - - - - - C12 - - - - - C12 PH13 I/O FT - -
EVENTOUT
TIM8_CH2N, FDCAN1_RX,
- - - - - - C11 - - - - - C11 PH14 I/O FT - -
DCMI_D4/PSSI_D4, EVENTOUT
TIM8_CH3N, OCTOSPIM_P2_IO6,
- - - - - - A13 - - - - - A13 PH15 I/O FT_h - -
DCMI_D11/PSSI_D11, EVENTOUT
- - - - - - A11 - - - - - A11 VDD S - - - -
TIM5_CH4, OCTOSPIM_P1_IO5,
- - - - - - B12 - - - - - B12 PI0 I/O FT_h - SPI2_NSS, DCMI_D13/PSSI_D13, -
EVENTOUT
SPI2_SCK, OCTOSPIM_P2_IO2,
- - - - - - A12 - - - - - A12 PI1 I/O FT_h - -
DCMI_D8/PSSI_D8, EVENTOUT

STM32U585xx
TIM8_CH4, SPI2_MISO,
- - - - - - D11 - - - - - D11 PI2 I/O FT_hv - OCTOSPIM_P2_IO1, -
DCMI_D9/PSSI_D9, EVENTOUT
 Table 27. STM32U585xx pin definitions(1) (continued)

STM32U585xx
Pin number

I/O structure
UFBGA132 SMPS

UFBGA169 SMPS
UFQFPN48 SMPS

WLCSP90 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA132

UFBGA169

Notes
Additional

LQFP100

LQFP144
LQFP48

LQFP64
(function after Alternate functions
functions
reset)

TIM8_ETR, SPI2_MOSI,
- - - - - - D10 - - - - - D10 PI3 I/O FT_h - OCTOSPIM_P2_IO0, -
DCMI_D10/PSSI_D10, EVENTOUT
- - - - - - B2 - - - - - B2 VSS S - - - -
- - - - - - B1 - - - - - B1 VDD S - - - -
TIM8_BKIN, SPI2_RDY,
- - - - - - B10 - - - - - B10 PI4 I/O FT - -
DS13086 Rev 6

DCMI_D5/PSSI_D5, EVENTOUT
TIM8_CH1, OCTOSPIM_P2_NCS,
- - - - - - B3 - - - - - B3 PI5 I/O FT_h - DCMI_VSYNC/PSSI_RDY, -
EVENTOUT

Pinout, pin description and alternate functions

TIM8_CH2, OCTOSPIM_P2_CLK,
- - - - - - A2 - - - - - A2 PI6 I/O FT_hv - -
DCMI_D6/PSSI_D6, EVENTOUT
TIM8_CH3, OCTOSPIM_P2_NCLK,
- - - - - - C3 - - - - - C3 PI7 I/O FT_hv - -
DCMI_D7/PSSI_D7, EVENTOUT
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs
in output mode is limited:
- The speed must not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (for example to drive a LED).
3. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the
system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the product reference manual.
4. After reset, a pull-down resistor (Rd = 5.1 kΩ from UCPD peripheral) can be activated on PA15 and PB15 (UCPD1_CC1, UCPD1_CC2). The pull-down on PA15
(UCPD1_CC1) is activated by high level on PB5 (UCPD1_DBCC1). The pull-down on PB15 (UCPD1_CC2) is activated by high level on PB14 (UCPD1_DBCC2).
This pull-down control (dead battery support on UCPD) can be disabled by setting UCPD_DBDIS = 1 in the PWR_UCPDR register.
5. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.
129/334
 4.3 Alternate functions
130/334

Pinout, pin description and alternate functions

Table 28. Alternate function AF0 to AF7(1)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
Port OCTOSPIM_P1/ DCMI/ DCMI/I2C4/MDF1/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/
OTG_FS/SAI1/ I2C1/2/3/4/ OCTOSPIM_P1/2/ OCTOSPIM_P2/ USART1/2/3
SYS_AF TIM1/2/5/8 TIM1/2/3/4/5
SPI2/TIM1/8/ LPTIM3 SPI1/2/3 SPI3
USART2

PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - SPI3_RDY USART2_CTS

USART2_
PA1 LPTIM1_CH2 TIM2_CH2 TIM5_CH2 - I2C1_SMBA SPI1_SCK -
RTS_DE
PA2 - TIM2_CH3 TIM5_CH3 - - SPI1_RDY - USART2_TX
PA3 - TIM2_CH4 TIM5_CH4 SAI1_CK1 - - - USART2_RX
DS13086 Rev 6

OCTOSPIM_P1
PA4 - - - - SPI1_NSS SPI3_NSS USART2_CK
_NCS
PA5 CSLEEP TIM2_CH1 TIM2_ETR TIM8_CH1N PSSI_D14 SPI1_SCK - USART3_RX
DCMI_PIXCL
PA6 CDSTOP TIM1_BKIN TIM3_CH1 TIM8_BKIN K/PSSI_ SPI1_MISO - USART3_CTS
PDCK
Port A

PA7 SRDSTOP TIM1_CH1N TIM3_CH2 TIM8_CH1N I2C3_SCL SPI1_MOSI - USART3_TX

PA8 MCO TIM1_CH1 - SAI1_CK2 - SPI1_RDY - USART1_CK
PA9 - TIM1_CH2 - SPI2_SCK - DCMI_D0/PSSI_D0 - USART1_TX
PA10 CRS_SYNC TIM1_CH3 LPTIM2_IN2 SAI1_D1 - DCMI_D1/PSSI_D1 - USART1_RX
PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - USART1_CTS
OCTOSPIM_ USART1_
PA12 - TIM1_ETR - - - SPI1_MOSI
P2_NCS RTS_DE

STM32U585xx
PA13 JTMS/SWDIO IR_OUT - - - - - -
PA14 JTCK/SWCLK LPTIM1_CH1 - - I2C1_SMBA I2C4_SMBA - -
USART3_
PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS SPI3_NSS
RTS_DE
 Table 28. Alternate function AF0 to AF7(1) (continued)

STM32U585xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
Port OCTOSPIM_P1/ DCMI/ DCMI/I2C4/MDF1/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/
OTG_FS/SAI1/ I2C1/2/3/4/ OCTOSPIM_P1/2/ OCTOSPIM_P2/ USART1/2/3
SYS_AF TIM1/2/5/8 TIM1/2/3/4/5
SPI2/TIM1/8/ LPTIM3 SPI1/2/3 SPI3
USART2

PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N LPTIM3_CH1 SPI1_NSS - USART3_CK

USART3_
PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N LPTIM3_CH2 - MDF1_SDI0
RTS_DE
PB2 - LPTIM1_CH1 - TIM8_CH4N I2C3_SMBA SPI1_RDY MDF1_CKI0 -
JTDO/ USART1_
PB3 TIM2_CH2 LPTIM1_CH1 ADF1_CCK0 I2C1_SDA SPI1_SCK SPI3_SCK
TRACESWO RTS_DE
PB4 NJTRST LPTIM1_CH2 TIM3_CH1 ADF1_SDI0 I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS
DS13086 Rev 6

OCTOSPIM_
PB5 - LPTIM1_IN1 TIM3_CH2 I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK
P1_NCLK
PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL I2C4_SCL MDF1_SDI5 USART1_TX

Pinout, pin description and alternate functions

Port B

PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA I2C4_SDA MDF1_CKI5 USART1_RX

PB8 - - TIM4_CH3 SAI1_CK1 I2C1_SCL MDF1_CCK0 SPI3_RDY -
PB9 - IR_OUT TIM4_CH4 SAI1_D2 I2C1_SDA SPI2_NSS - -
PB10 - TIM2_CH3 LPTIM3_CH1 I2C4_SCL I2C2_SCL SPI2_SCK - USART3_TX
PB11 - TIM2_CH4 - I2C4_SDA I2C2_SDA SPI2_RDY - USART3_RX
PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS MDF1_SDI1 USART3_CK
PB13 - TIM1_CH1N LPTIM3_IN1 - I2C2_SCL SPI2_SCK MDF1_CKI1 USART3_CTS
USART3_
PB14 - TIM1_CH2N LPTIM3_ETR TIM8_CH2N I2C2_SDA SPI2_MISO MDF1_SDI2
RTS_DE
PB15 RTC_REFIN TIM1_CH3N LPTIM2_IN2 TIM8_CH3N - SPI2_MOSI MDF1_CKI2 -
131/334
 Table 28. Alternate function AF0 to AF7(1) (continued)
132/334

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
Port OCTOSPIM_P1/ DCMI/ DCMI/I2C4/MDF1/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/
OTG_FS/SAI1/ I2C1/2/3/4/ OCTOSPIM_P1/2/ OCTOSPIM_P2/ USART1/2/3
SYS_AF TIM1/2/5/8 TIM1/2/3/4/5
SPI2/TIM1/8/ LPTIM3 SPI1/2/3 SPI3
USART2

OCTOSPIM_
PC0 - LPTIM1_IN1 - I2C3_SCL SPI2_RDY MDF1_SDI4 -
P1_IO7
PC1 TRACED0 LPTIM1_CH1 - SPI2_MOSI I2C3_SDA - MDF1_CKI4 -
PC2 - LPTIM1_IN2 - - - SPI2_MISO MDF1_CCK1 -
PC3 - LPTIM1_ETR LPTIM3_CH1 SAI1_D1 - SPI2_MOSI - -
PC4 - - - - - - - USART3_TX
PC5 - TIM1_CH4N - SAI1_D3 PSSI_D15 - - USART3_RX
DS13086 Rev 6

PC6 CSLEEP - TIM3_CH1 TIM8_CH1 - - MDF1_CKI3 -

PC7 CDSTOP - TIM3_CH2 TIM8_CH2 - - MDF1_SDI3 -
Port C

PC8 SRDSTOP - TIM3_CH3 TIM8_CH3 - - - -

DCMI_D3/
PC9 TRACED0 TIM8_BKIN2 TIM3_CH4 TIM8_CH4 - - -
PSSI_D3
PC10 TRACED1 - LPTIM3_ETR ADF1_CCK1 - - SPI3_SCK USART3_TX
DCMI_D2/ OCTOSPIM_
PC11 - - LPTIM3_IN1 ADF1_SDI0 SPI3_MISO USART3_RX
PSSI_D2 P1_NCS
PC12 TRACED3 - - - - - SPI3_MOSI USART3_CK
PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -

STM32U585xx
 Table 28. Alternate function AF0 to AF7(1) (continued)

STM32U585xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
Port OCTOSPIM_P1/ DCMI/ DCMI/I2C4/MDF1/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/
OTG_FS/SAI1/ I2C1/2/3/4/ OCTOSPIM_P1/2/ OCTOSPIM_P2/ USART1/2/3
SYS_AF TIM1/2/5/8 TIM1/2/3/4/5
SPI2/TIM1/8/ LPTIM3 SPI1/2/3 SPI3
USART2

PD0 - - - TIM8_CH4N - SPI2_NSS - -

PD1 - - - - - SPI2_SCK - -
USART3_
PD2 TRACED2 - TIM3_ETR - - - -
RTS_DE
DCMI_D5/
PD3 - - - SPI2_SCK SPI2_MISO MDF1_SDI0 USART2_CTS
PSSI_D5
USART2_
PD4 - - - - - SPI2_MOSI MDF1_CKI0
RTS_DE
DS13086 Rev 6

PD5 - - - - - SPI2_RDY - USART2_TX

DCMI_D10/
PD6 - - - SAI1_D1 SPI3_MOSI MDF1_SDI1 USART2_RX

Pinout, pin description and alternate functions

PSSI_D10
Port D

PD7 - - - - - - MDF1_CKI1 USART2_CK

PD8 - - - - - - - USART3_TX
PD9 - - LPTIM2_IN2 - - - - USART3_RX
PD10 - - LPTIM2_CH2 - - - - USART3_CK
PD11 - - - - I2C4_SMBA - - USART3_CTS
USART3_
PD12 - - TIM4_CH1 - I2C4_SCL - -
RTS_DE
PD13 - - TIM4_CH2 - I2C4_SDA - - -
PD14 - - TIM4_CH3 - - - - -
PD15 - - TIM4_CH4 - - - - -
133/334
 Table 28. Alternate function AF0 to AF7(1) (continued)
134/334

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
Port OCTOSPIM_P1/ DCMI/ DCMI/I2C4/MDF1/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/
OTG_FS/SAI1/ I2C1/2/3/4/ OCTOSPIM_P1/2/ OCTOSPIM_P2/ USART1/2/3
SYS_AF TIM1/2/5/8 TIM1/2/3/4/5
SPI2/TIM1/8/ LPTIM3 SPI1/2/3 SPI3
USART2

PE0 - - TIM4_ETR - - - - -
PE1 - - - - - - - -
PE2 TRACECLK - TIM3_ETR SAI1_CK1 - - - -
OCTOSPIM_
PE3 TRACED0 - TIM3_CH1 - - - -
P1_DQS
PE4 TRACED1 - TIM3_CH2 SAI1_D2 - - MDF1_SDI3 -
PE5 TRACED2 - TIM3_CH3 SAI1_CK2 - - MDF1_CKI3 -
DS13086 Rev 6

PE6 TRACED3 - TIM3_CH4 SAI1_D1 - - - -

Port E

PE7 - TIM1_ETR - - - - MDF1_SDI2 -

PE8 - TIM1_CH1N - - - - MDF1_CKI2 -
PE9 - TIM1_CH1 - ADF1_CCK0 - - MDF1_CCK0 -
PE10 - TIM1_CH2N - ADF1_SDI0 - - MDF1_SDI4 -
PE11 - TIM1_CH2 - - - SPI1_RDY MDF1_CKI4 -
PE12 - TIM1_CH3N - - - SPI1_NSS MDF1_SDI5 -
PE13 - TIM1_CH3 - - - SPI1_SCK MDF1_CKI5 -
PE14 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - -
PE15 - TIM1_BKIN - TIM1_CH4N - SPI1_MOSI - -

STM32U585xx
 Table 28. Alternate function AF0 to AF7(1) (continued)

STM32U585xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
Port OCTOSPIM_P1/ DCMI/ DCMI/I2C4/MDF1/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/
OTG_FS/SAI1/ I2C1/2/3/4/ OCTOSPIM_P1/2/ OCTOSPIM_P2/ USART1/2/3
SYS_AF TIM1/2/5/8 TIM1/2/3/4/5
SPI2/TIM1/8/ LPTIM3 SPI1/2/3 SPI3
USART2

PF0 - - - - I2C2_SDA OCTOSPIM_P2_IO0 - -

PF1 - - - - I2C2_SCL OCTOSPIM_P2_IO1 - -
PF2 - - LPTIM3_CH2 - I2C2_SMBA OCTOSPIM_P2_IO2 - -
PF3 - - LPTIM3_IN1 - - OCTOSPIM_P2_IO3 - -
OCTOSPIM_
PF4 - - LPTIM3_ETR - - - -
P2_CLK
OCTOSPIM_
DS13086 Rev 6

PF5 - - LPTIM3_CH1 - - - -
P2_NCLK
DCMI_D12/P OCTOSPIM_
PF6 - TIM5_ETR TIM5_CH1 - - -
SSI_D12 P2_NCS

Pinout, pin description and alternate functions

PF7 - - TIM5_CH2 - - - - -
Port F

PF8 - - TIM5_CH3 - PSSI_D14 - - -

PF9 - - TIM5_CH4 - PSSI_D15 - - -
OCTOSPIM_
PF10 - - - PSSI_D15 - MDF1_CCK1 -
P1_CLK
OCTOSPIM_
PF11 - - - - - - -
P1_NCLK
OCTOSPIM_
PF12 - - - - - - -
P2_DQS
PF13 - - - - I2C4_SMBA - - -
PF14 - - - - I2C4_SCL - - -
PF15 - - - - I2C4_SDA - - -
135/334
 Table 28. Alternate function AF0 to AF7(1) (continued)
136/334

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
Port OCTOSPIM_P1/ DCMI/ DCMI/I2C4/MDF1/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/
OTG_FS/SAI1/ I2C1/2/3/4/ OCTOSPIM_P1/2/ OCTOSPIM_P2/ USART1/2/3
SYS_AF TIM1/2/5/8 TIM1/2/3/4/5
SPI2/TIM1/8/ LPTIM3 SPI1/2/3 SPI3
USART2

PG0 - - - - - OCTOSPIM_P2_IO4 - -
PG1 - - - - - OCTOSPIM_P2_IO5 - -
PG2 - - - - - SPI1_SCK - -
PG3 - - - - - SPI1_MISO - -
PG4 - - - - - SPI1_MOSI - -
PG5 - - - - - SPI1_NSS - -
DS13086 Rev 6

OCTOSPIM_
PG6 - - - I2C3_SMBA SPI1_RDY - -
P1_DQS
OCTOSPIM_
PG7 - - - SAI1_CK1 I2C3_SCL MDF1_CCK0 -
P2_DQS
Port G

PG8 - - - - I2C3_SDA - - -
PG9 - - - - - OCTOSPIM_P2_IO6 SPI3_SCK USART1_TX
PG10 - LPTIM1_IN1 - - - OCTOSPIM_P2_IO7 SPI3_MISO USART1_RX
OCTOSPIM_
PG11 - LPTIM1_IN2 - - - SPI3_MOSI USART1_CTS
P1_IO5
OCTOSPIM_ USART1_
PG12 - LPTIM1_ETR - - - SPI3_NSS
P2_NCS RTS_DE
PG13 - - - - I2C1_SDA - SPI3_RDY USART1_CK
PG14 - LPTIM1_CH2 - - I2C1_SCL - - -

STM32U585xx
OCTOSPIM_
PG15 - LPTIM1_CH1 - - I2C1_SMBA - -
P2_DQS
 Table 28. Alternate function AF0 to AF7(1) (continued)

STM32U585xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
Port OCTOSPIM_P1/ DCMI/ DCMI/I2C4/MDF1/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/
OTG_FS/SAI1/ I2C1/2/3/4/ OCTOSPIM_P1/2/ OCTOSPIM_P2/ USART1/2/3
SYS_AF TIM1/2/5/8 TIM1/2/3/4/5
SPI2/TIM1/8/ LPTIM3 SPI1/2/3 SPI3
USART2

PH0 - - - - - - - -
PH1 - - - - - - - -
OCTOSPIM_
PH2 - - - - - - -
P1_IO4
PH3 - - - - - - - -
OCTOSPIM_
PH4 - - - - I2C2_SCL - -
P2_DQS
DS13086 Rev 6

PH5 - - - - I2C2_SDA - - -
OCTOSPIM_
PH6 - - - - I2C2_SMBA - -
P2_CLK

Pinout, pin description and alternate functions

Port H

OCTOSPIM_
PH7 - - - - I2C3_SCL - -
P2_NCLK
PH8 - - - - I2C3_SDA OCTOSPIM_P2_IO3 - -
PH9 - - - - I2C3_SMBA OCTOSPIM_P2_IO4 - -
PH10 - - TIM5_CH1 - - OCTOSPIM_P2_IO5 - -
PH11 - - TIM5_CH2 - - OCTOSPIM_P2_IO6 - -
PH12 - - TIM5_CH3 TIM8_CH4N - OCTOSPIM_P2_IO7 - -
PH13 - - - TIM8_CH1N - - - -
PH14 - - - TIM8_CH2N - - - -
PH15 - - - TIM8_CH3N - OCTOSPIM_P2_IO6 - -
137/334
 Table 28. Alternate function AF0 to AF7(1) (continued)
138/334

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
Port OCTOSPIM_P1/ DCMI/ DCMI/I2C4/MDF1/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/
OTG_FS/SAI1/ I2C1/2/3/4/ OCTOSPIM_P1/2/ OCTOSPIM_P2/ USART1/2/3
SYS_AF TIM1/2/5/8 TIM1/2/3/4/5
SPI2/TIM1/8/ LPTIM3 SPI1/2/3 SPI3
USART2

OCTOSPIM_
PI0 - - TIM5_CH4 - SPI2_NSS - -
P1_IO5
OCTOSPIM_
PI1 - - - - - SPI2_SCK -
P2_IO2
OCTOSPIM_
PI2 - - - TIM8_CH4 - SPI2_MISO -
P2_IO1
OCTOSPIM_
PI3 - - - TIM8_ETR - SPI2_MOSI -
Port I

P2_IO0
DS13086 Rev 6

PI4 - - - TIM8_BKIN - SPI2_RDY - -

OCTOSPIM_
PI5 - - - TIM8_CH1 - - -
P2_NCS
OCTOSPIM_
PI6 - - - TIM8_CH2 - - -
P2_CLK
OCTOSPIM_
PI7 - - - TIM8_CH3 - - -
P2_NCLK
1. Refer to the next table for AF8 to AF15.

STM32U585xx
 Table 29. Alternate function AF8 to AF15(1)

STM32U585xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ LPGPIO1/

COMP1/2/FMC/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ CAN1/TSC OCTOSPIM_P1/2/ SDMMC2/ EVENOUT
SDMMC1/2 SAI1/2 TIM2/15/16/17
UART4/5 OTG_FS UCPD1/FMC

OCTOSPIM_
PA0 UART4_TX - - SDMMC2_CMD AUDIOCLK TIM2_ETR EVENTOUT
P2_NCS
OCTOSPIM_
PA1 UART4_RX - LPGPIO1_P0 - - TIM15_CH1N EVENTOUT
P1_DQS
OCTOSPIM_ UCPD1_
PA2 LPUART1_TX - - - TIM15_CH1 EVENTOUT
P1_NCS FRSTX1
PA3 LPUART1_RX - OCTOSPIM_P1_CLK LPGPIO1_P1 - SAI1_MCLK_A TIM15_CH2 EVENTOUT
DCMI_HSYNC/
PA4 - - - - SAI1_FS_B LPTIM2_CH1 EVENTOUT
PSSI_DE
DS13086 Rev 6

PA5 - - - - - - LPTIM2_ETR EVENTOUT

Port A

PA6 LPUART1_CTS - OCTOSPIM_P1_IO3 LPGPIO1_P2 - - TIM16_CH1 EVENTOUT

Pinout, pin description and alternate functions

PA7 - - OCTOSPIM_P1_IO2 - - LPTIM2_CH2 TIM17_CH1 EVENTOUT
PA8 - - OTG_FS_SOF - TRACECLK SAI1_SCK_A LPTIM2_CH1 EVENTOUT
PA9 - - - - - SAI1_FS_A TIM15_BKIN EVENTOUT
PA10 - - OTG_FS_ID - - SAI1_SD_A TIM17_BKIN EVENTOUT
PA11 - FDCAN1_RX OTG_FS_DM - - - - EVENTOUT
PA12 - FDCAN1_TX OTG_FS_DP - - - - EVENTOUT
PA13 - - OTG_FS_NOE - - SAI1_SD_B - EVENTOUT
PA14 - - OTG_FS_SOF - - SAI1_FS_B - EVENTOUT
PA15 UART4_RTS_DE - - - - SAI2_FS_B - EVENTOUT
139/334
 Table 29. Alternate function AF8 to AF15(1) (continued)
140/334

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ LPGPIO1/

COMP1/2/FMC/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ CAN1/TSC OCTOSPIM_P1/2/ SDMMC2/ EVENOUT
SDMMC1/2 SAI1/2 TIM2/15/16/17
UART4/5 OTG_FS UCPD1/FMC

PB0 - - OCTOSPIM_P1_IO1 LPGPIO1_P9 COMP1_OUT AUDIOCLK - EVENTOUT

LPUART1_
PB1 - OCTOSPIM_P1_IO0 LPGPIO1_P3 - - LPTIM2_IN1 EVENTOUT
RTS_DE
OCTOSPIM_ UCPD1_
PB2 - - - - - EVENTOUT
P1_DQS FRSTX1
PB3 - - CRS_SYNC LPGPIO1_P11 SDMMC2_D2 SAI1_SCK_B - EVENTOUT
DCMI_D12/
PB4 UART5_RTS_DE TSC_G2_IO1 LPGPIO1_P12 SDMMC2_D3 SAI1_MCLK_B TIM17_BKIN EVENTOUT
PSSI_D12
DCMI_D10/
DS13086 Rev 6

PB5 UART5_CTS TSC_G2_IO2 - COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT

PSSI_D10
PB6 - TSC_G2_IO3 DCMI_D5/PSSI_D5 - - SAI1_FS_B TIM16_CH1N EVENTOUT
Port B

DCMI_VSYNC/
PB7 UART4_CTS TSC_G2_IO4 - FMC_NL - TIM17_CH1N EVENTOUT
PSSI_RDY
PB8 SDMMC1_CKIN FDCAN1_RX DCMI_D6/PSSI_D6 SDMMC2_D4 SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT
PB9 SDMMC1_CDIR FDCAN1_TX DCMI_D7/PSSI_D7 SDMMC2_D5 SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT
PB10 LPUART1_RX TSC_SYNC OCTOSPIM_P1_CLK LPGPIO1_P4 COMP1_OUT SAI1_SCK_A - EVENTOUT
OCTOSPIM_
PB11 LPUART1_TX - - COMP2_OUT - - EVENTOUT
P1_NCS
LPUART1_RTS_ OCTOSPIM_
PB12 TSC_G1_IO1 - - SAI2_FS_A TIM15_BKIN EVENTOUT
DE P1_NCLK
PB13 LPUART1_CTS TSC_G1_IO2 - - - SAI2_SCK_A TIM15_CH1N EVENTOUT
PB14 - TSC_G1_IO3 - - SDMMC2_D0 SAI2_MCLK_A TIM15_CH1 EVENTOUT

STM32U585xx
PB15 - - - FMC_NBL1 SDMMC2_D1 SAI2_SD_A TIM15_CH2 EVENTOUT
 Table 29. Alternate function AF8 to AF15(1) (continued)

STM32U585xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ LPGPIO1/

COMP1/2/FMC/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ CAN1/TSC OCTOSPIM_P1/2/ SDMMC2/ EVENOUT
SDMMC1/2 SAI1/2 TIM2/15/16/17
UART4/5 OTG_FS UCPD1/FMC

PC0 LPUART1_RX - - - SDMMC1_D5 SAI2_FS_A LPTIM2_IN1 EVENTOUT

PC1 LPUART1_TX - OCTOSPIM_P1_IO4 - SDMMC2_CK SAI1_SD_A - EVENTOUT
PC2 - - OCTOSPIM_P1_IO5 LPGPIO1_P5 - - - EVENTOUT
PC3 - - OCTOSPIM_P1_IO6 - - SAI1_SD_A LPTIM2_ETR EVENTOUT
PC4 - - OCTOSPIM_P1_IO7 - - - - EVENTOUT
PC5 - - - - - - - EVENTOUT
SDMMC1_
PC6 TSC_G4_IO1 DCMI_D0/PSSI_D0 SDMMC2_D6 SDMMC1_D6 SAI2_MCLK_A - EVENTOUT
D0DIR
DS13086 Rev 6

SDMMC1_
PC7 TSC_G4_IO2 DCMI_D1/PSSI_D1 SDMMC2_D7 SDMMC1_D7 SAI2_MCLK_B LPTIM2_CH2 EVENTOUT
Port C

D123DIR
PC8 - TSC_G4_IO3 DCMI_D2/PSSI_D2 - SDMMC1_D0 - LPTIM3_CH1 EVENTOUT

Pinout, pin description and alternate functions

PC9 - TSC_G4_IO4 OTG_FS_NOE - SDMMC1_D1 - LPTIM3_CH2 EVENTOUT
PC10 UART4_TX TSC_G3_IO2 DCMI_D8/PSSI_D8 LPGPIO1_P8 SDMMC1_D2 SAI2_SCK_B - EVENTOUT
UCPD1_
PC11 UART4_RX TSC_G3_IO3 DCMI_D4/PSSI_D4 SDMMC1_D3 SAI2_MCLK_B - EVENTOUT
FRSTX2
PC12 UART5_TX TSC_G3_IO4 DCMI_D9/PSSI_D9 LPGPIO1_P10 SDMMC1_CK SAI2_SD_B - EVENTOUT
PC13 - - - - - - - EVENTOUT
PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT
141/334
 Table 29. Alternate function AF8 to AF15(1) (continued)
142/334

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ LPGPIO1/

COMP1/2/FMC/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ CAN1/TSC OCTOSPIM_P1/2/ SDMMC2/ EVENOUT
SDMMC1/2 SAI1/2 TIM2/15/16/17
UART4/5 OTG_FS UCPD1/FMC

PD0 - FDCAN1_RX - - FMC_D2 - - EVENTOUT

PD1 - FDCAN1_TX - - FMC_D3 - - EVENTOUT
DCMI_D11/
PD2 UART5_RX TSC_SYNC LPGPIO1_P7 SDMMC1_CMD LPTIM4_ETR - EVENTOUT
PSSI_D11
OCTOSPIM_
PD3 - - - FMC_CLK - - EVENTOUT
P2_NCS
PD4 - - OCTOSPIM_P1_IO4 - FMC_NOE - - EVENTOUT
PD5 - - OCTOSPIM_P1_IO5 - FMC_NWE - - EVENTOUT
DS13086 Rev 6

PD6 - - OCTOSPIM_P1_IO6 SDMMC2_CK FMC_NWAIT SAI1_SD_A - EVENTOUT

FMC_NCE/
PD7 - - OCTOSPIM_P1_IO7 SDMMC2_CMD LPTIM4_OUT - EVENTOUT
FMC_NE1
Port D

DCMI_HSYNC/
PD8 - - - FMC_D13 - - EVENTOUT
PSSI_DE
DCMI_PIXCLK/
PD9 - - - FMC_D14 SAI2_MCLK_A LPTIM3_IN1 EVENTOUT
PSSI_PDCK
PD10 - TSC_G6_IO1 - - FMC_D15 SAI2_SCK_A LPTIM3_ETR EVENTOUT
FMC_CLE/
PD11 - TSC_G6_IO2 - - SAI2_SD_A LPTIM2_ETR EVENTOUT
FMC_A16
FMC_ALE/
PD12 - TSC_G6_IO3 - - SAI2_FS_A LPTIM2_IN1 EVENTOUT
FMC_A17
PD13 - TSC_G6_IO4 - LPGPIO1_P6 FMC_A18 LPTIM4_IN1 LPTIM2_CH1 EVENTOUT
PD14 - - - - FMC_D0 - LPTIM3_CH1 EVENTOUT

STM32U585xx
PD15 - - - - FMC_D1 - LPTIM3_CH2 EVENTOUT
 Table 29. Alternate function AF8 to AF15(1) (continued)

STM32U585xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ LPGPIO1/

COMP1/2/FMC/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ CAN1/TSC OCTOSPIM_P1/2/ SDMMC2/ EVENOUT
SDMMC1/2 SAI1/2 TIM2/15/16/17
UART4/5 OTG_FS UCPD1/FMC

PE0 - - DCMI_D2/PSSI_D2 LPGPIO1_P13 FMC_NBL0 - TIM16_CH1 EVENTOUT

PE1 - - DCMI_D3/PSSI_D3 - FMC_NBL1 - TIM17_CH1 EVENTOUT
PE2 - TSC_G7_IO1 - LPGPIO1_P14 FMC_A23 SAI1_MCLK_A - EVENTOUT
PE3 - TSC_G7_IO2 - LPGPIO1_P15 FMC_A19 SAI1_SD_B - EVENTOUT
PE4 - TSC_G7_IO3 DCMI_D4/PSSI_D4 - FMC_A20 SAI1_FS_A - EVENTOUT
PE5 - TSC_G7_IO4 DCMI_D6/PSSI_D6 - FMC_A21 SAI1_SCK_A - EVENTOUT
PE6 - - DCMI_D7/PSSI_D7 - FMC_A22 SAI1_SD_A - EVENTOUT
PE7 - - - - FMC_D4 SAI1_SD_B - EVENTOUT
DS13086 Rev 6

Port E

PE8 - - - - FMC_D5 SAI1_SCK_B - EVENTOUT

OCTOSPIM_P1_NC
PE9 - - - FMC_D6 SAI1_FS_B - EVENTOUT

Pinout, pin description and alternate functions

LK
PE10 - TSC_G5_IO1 OCTOSPIM_P1_CLK - FMC_D7 SAI1_MCLK_B - EVENTOUT
OCTOSPIM_
PE11 - TSC_G5_IO2 - FMC_D8 - - EVENTOUT
P1_NCS
PE12 - TSC_G5_IO3 OCTOSPIM_P1_IO0 - FMC_D9 - - EVENTOUT
PE13 - TSC_G5_IO4 OCTOSPIM_P1_IO1 - FMC_D10 - - EVENTOUT
PE14 - - OCTOSPIM_P1_IO2 - FMC_D11 - - EVENTOUT
PE15 - - OCTOSPIM_P1_IO3 - FMC_D12 - - EVENTOUT
143/334
 Table 29. Alternate function AF8 to AF15(1) (continued)
144/334

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ LPGPIO1/

COMP1/2/FMC/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ CAN1/TSC OCTOSPIM_P1/2/ SDMMC2/ EVENOUT
SDMMC1/2 SAI1/2 TIM2/15/16/17
UART4/5 OTG_FS UCPD1/FMC

PF0 - - - - FMC_A0 - - EVENTOUT

PF1 - - - - FMC_A1 - - EVENTOUT
PF2 - - - - FMC_A2 - - EVENTOUT
PF3 - - - - FMC_A3 - - EVENTOUT
PF4 - - - - FMC_A4 - - EVENTOUT
PF5 - - - - FMC_A5 - - EVENTOUT
PF6 - - OCTOSPIM_P1_IO3 - - SAI1_SD_B - EVENTOUT
PF7 - FDCAN1_RX OCTOSPIM_P1_IO2 - - SAI1_MCLK_B - EVENTOUT
DS13086 Rev 6

PF8 - FDCAN1_TX OCTOSPIM_P1_IO0 - - SAI1_SCK_B - EVENTOUT

Port F

PF9 - - OCTOSPIM_P1_IO1 - - SAI1_FS_B TIM15_CH1 EVENTOUT

DCMI_D11/
PF10 - - - - SAI1_D3 TIM15_CH2 EVENTOUT
PSSI_D11
DCMI_D12/
PF11 - - - - LPTIM4_IN1 - EVENTOUT
PSSI_D12
PF12 - - - - FMC_A6 LPTIM4_ETR - EVENTOUT
UCPD1_
PF13 - - - FMC_A7 LPTIM4_OUT - EVENTOUT
FRSTX2
PF14 - TSC_G8_IO1 - - FMC_A8 - - EVENTOUT
PF15 - TSC_G8_IO2 - - FMC_A9 - - EVENTOUT

STM32U585xx
 Table 29. Alternate function AF8 to AF15(1) (continued)

STM32U585xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ LPGPIO1/

COMP1/2/FMC/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ CAN1/TSC OCTOSPIM_P1/2/ SDMMC2/ EVENOUT
SDMMC1/2 SAI1/2 TIM2/15/16/17
UART4/5 OTG_FS UCPD1/FMC

PG0 - TSC_G8_IO3 - - FMC_A10 - - EVENTOUT

PG1 - TSC_G8_IO4 - - FMC_A11 - - EVENTOUT
PG2 - - - - FMC_A12 SAI2_SCK_B - EVENTOUT
PG3 - - - - FMC_A13 SAI2_FS_B - EVENTOUT
PG4 - - - - FMC_A14 SAI2_MCLK_B - EVENTOUT
PG5 LPUART1_CTS - - - FMC_A15 SAI2_SD_B - EVENTOUT
LPUART1_ UCPD1_
PG6 - - - - - EVENTOUT
RTS_DE FRSTX1
DS13086 Rev 6

UCPD1_
PG7 LPUART1_TX - - FMC_INT SAI1_MCLK_A - EVENTOUT
FRSTX2
Port G

PG8 LPUART1_RX - - - - - - EVENTOUT

Pinout, pin description and alternate functions

FMC_NCE/
PG9 - - - - SAI2_SCK_A TIM15_CH1N EVENTOUT
FMC_NE2
PG10 - - - - FMC_NE3 SAI2_FS_A TIM15_CH1 EVENTOUT
PG11 - - - - - SAI2_MCLK_A TIM15_CH2 EVENTOUT
PG12 - - - - FMC_NE4 SAI2_SD_A - EVENTOUT
PG13 - - - - FMC_A24 - - EVENTOUT
PG14 - - - - FMC_A25 - - EVENTOUT
DCMI_D13/
PG15 - - - - - - EVENTOUT
PSSI_D13
145/334
 Table 29. Alternate function AF8 to AF15(1) (continued)
146/334

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ LPGPIO1/

COMP1/2/FMC/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ CAN1/TSC OCTOSPIM_P1/2/ SDMMC2/ EVENOUT
SDMMC1/2 SAI1/2 TIM2/15/16/17
UART4/5 OTG_FS UCPD1/FMC

PH0 - - - - - - - EVENTOUT
PH1 - - - - - - - EVENTOUT
PH2 - - - - - - - EVENTOUT
PH3 - - - - - - - EVENTOUT
PH4 - - PSSI_D14 - - - - EVENTOUT
DCMI_PIXCLK/
PH5 - - - - - - EVENTOUT
PSSI_PDCK
PH6 - - DCMI_D8/PSSI_D8 - - - - EVENTOUT
DS13086 Rev 6

PH7 - - DCMI_D9/PSSI_D9 - - - - EVENTOUT

Port H

DCMI_HSYNC/
PH8 - - - - - - EVENTOUT
PSSI_DE
PH9 - - DCMI_D0/PSSI_D0 - - - - EVENTOUT
PH10 - - DCMI_D1/PSSI_D1 - - - - EVENTOUT
PH11 - - DCMI_D2/PSSI_D2 - - - - EVENTOUT
PH12 - - DCMI_D3/PSSI_D3 - - - - EVENTOUT
PH13 - FDCAN1_TX - - - - - EVENTOUT
PH14 - FDCAN1_RX DCMI_D4/PSSI_D4 - - - - EVENTOUT
DCMI_D11/
PH15 - - - - - - EVENTOUT
PSSI_D11

STM32U585xx
 Table 29. Alternate function AF8 to AF15(1) (continued)

STM32U585xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ LPGPIO1/

COMP1/2/FMC/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ CAN1/TSC OCTOSPIM_P1/2/ SDMMC2/ EVENOUT
SDMMC1/2 SAI1/2 TIM2/15/16/17
UART4/5 OTG_FS UCPD1/FMC

DCMI_D13/
PI0 - - - - - - EVENTOUT
PSSI_D13
PI1 - - DCMI_D8/PSSI_D8 - - - - EVENTOUT
PI2 - - DCMI_D9/PSSI_D9 - - - - EVENTOUT
DCMI_D10/
PI3 - - - - - - EVENTOUT
Port I

PSSI_D10
PI4 - - DCMI_D5/PSSI_D5 - - - - EVENTOUT
DCMI_VSYNC/
PI5 - - - - - - EVENTOUT
PSSI_RDY
DS13086 Rev 6

PI6 - - DCMI_D6/PSSI_D6 - - - - EVENTOUT

PI7 - - DCMI_D7/PSSI_D7 - - - - EVENTOUT

Pinout, pin description and alternate functions

1. For AF0 to AF7 refer to the previous table.
147/334
Electrical characteristics STM32U585xx

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes, and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V.
They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have
an error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 22.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 23.

Figure 22. Pin loading conditions Figure 23. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MSv68045V1 MSv68046V1

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STM32U585xx Electrical characteristics

5.1.6 Power supply scheme

Figure 24. STM32U585xx power supply scheme (without SMPS)

VBAT
Backup circuitry
1.65 – 3.6 V (LSE, RTC, TAMP
backup registers,
VDDUSB backup SRAM)
VDDUSB
100 nF
VCAP Power switch

4.7 μF

VDD VCORE
n x VDD LDO
VCORE
regulator
VDDIO1
OUT Kernel logic

Level shifter
n x 100 nF I/O (CPU, digital
+ 1 x 10 μF GPIOs logic and
IN
memories)

n x VSS

VDDIO2
m x VDDIO2
VDDIO2
m x 100 nF OUT
Level shifter

+ 4.7 μF I/O
GPIOs logic
IN

m x VSS

VDDA
VDDA
VREF
ADCs/
100 nF VREF+ DACs/
+1 μF OPAMPs/
100 nF+ 1 μF VREF- COMPs/
VREFBUF

VSSA
MSv64358V3

Caution: If there are two VCAP pins (UFBGA169 package), each pin must be connected to a 2.2 µF
(typical) capacitor (for a total around 4.4 µF).

DS13086 Rev 6 149/334

299
Electrical characteristics STM32U585xx

Figure 25. STM32U585xQ power supply scheme (with SMPS)

VBAT Backup circuitry

1.65 – 3.6 V
(LSE, RTC, TAMP,
backup registers,
VDDUSB backup SRAM)
Power switch
VDDUSB
100 nF
VDD
VDDSMPS
Voltage regulator
10 μF
SMPS VCORE
VLXSMPS SMPS ON

2.2 μH
2 x VDD11
2 x 2.2 μF Kernel logic
VSSSMPS
SMPS OFF (CPU, digital
and memories)
VDD LDO
n x VDD

VDDIO1
OUT

Level shifter
I/O
n x 100 nF GPIOs
IN
logic
+ 10 μF

n x VSS

VDDIO2
m x VDDIO2
VDDIO2
Level shifter

m x100 nF OUT
+ 4.7 μF I/O
GPIOs logic
IN
m x VSS

VDDA
VDDA
VREF
ADCs/
100 nF VREF+ DACs/
+ 1 μF OPAMPs/
100 nF+ 1 μF VREF- COMPs/
VREFBUF

VSSA
MSv64359V3

Note: SMPS and LDO regulators provide, in a concurrent way, the VCORE supply depending on
application requirements. However, only one of them is active at the same time. When
SMPS is active, it feeds the VCORE on the two VDD11 pins supplied by the filtered SMPS
VLXSMPS output pin. A 2.2 µH coil and a 2.2 µF capacitor on each VDD11 pin are then
required. When LDO is active, it supplies the VCORE and regulates it using the same
decoupling capacitors on VDD11 pins. It is recommended to add a decoupling capacitor of
100 nF near each VDD11 pin/ball, but it is not mandatory.

150/334 DS13086 Rev 6

STM32U585xx Electrical characteristics

Caution: Each power supply pair (such as VDD/VSS or VDDA/VSSA) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.

5.1.7 Current consumption measurement

The IDD parameters given in various tables in the next sections, represent the total MCU
consumption including the current supplying VDD, VDDIO2, VDDA, VDDUSB, VBAT and
VDDSMPS (if the device embeds the SMPS).

Figure 26. Current consumption measurement

VBAT
IDD_VBAT

IDD
VDD

VDDA

VDDUSB

VDDSMPS

VDDIO2
MSv62920V2

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 30, Table 31 and Table 32
may cause permanent damage to the device. These are stress ratings only and the
functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability. Device mission profile
(application conditions) is compliant with JEDEC JESD47 qualification standard, extended
mission profiles are available on demand.

Table 30. Voltage characteristics(1)(2)

Symbol Ratings Min Max Unit

External main supply voltage (including

VDDX - VSS -0.3 4.0
VDDSMPS, VDDA, VDDUSB, VBAT, VREF+)
I/O supply when HSLV = 0 -0.3 4.0
VDDIOx(3) - VSS
I/O supply when HSLV = 1 -0.3 2.75
V
Input voltage on FT_xx pins except Min (min (VDD, VDDA, VDDUSB, VDDIO2)
VSS - 0.3
FT_c pins + 4.0, 6.0)(5)(6)
VIN(4)
Input voltage on FT_t pins in Min (min (VBAT, VDDA, VDDUSB,
VSS - 0.3
VBAT mode VDDIO2) + 4.0, 6.0) (5)(6)

DS13086 Rev 6 151/334

299
Electrical characteristics STM32U585xx

Table 30. Voltage characteristics(1)(2) (continued)

Symbol Ratings Min Max Unit

Input voltage on FT_c pins VSS - 0.3 5.5

VIN(4)
Input voltage on any other pins VSS - 0.3 4.0
V
Allowed voltage difference for
VREF+ - VDDA - 0.4
VREF+ > VDDA
Variations between different VDDx
|∆VDDx| - 50.0
power pins of the same domain
mV
Variations between all the different
|VSSx-VSS| - 50.0
ground pins(7)
1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must
always be connected to the external power supply, in the permitted range.
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
3. VDDIO1 or VDDIO2, VDDIO1 = VDD.
4. VIN maximum must always be respected. Refer to Table 31 for the maximum allowed injected current values.
5. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
6. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.
7. Including VREF- pin.

Table 31. Current characteristics

Symbol Ratings Max Unit

∑IVDD (1)
Total current into sum of all VDD power lines (source) 200
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 200
IVDD Maximum current into each VDD power pin (source)(1) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
IIO Output current sunk by any I/O and control pin 20 mA
Total output current sunk by sum of all I/Os and control pins(2) 120
∑I(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 120
IINJ(PIN)(3)(4) Injected current on FT_xx, TT_xx, RST pins -5/+0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must
always be connected to the external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 30 for the minimum
allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN) is the absolute sum of the negative
injected currents (instantaneous values).

152/334 DS13086 Rev 6

STM32U585xx Electrical characteristics

Table 32. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150

°C
TJ Maximum junction temperature 140

5.3 Operating conditions

5.3.1 General operating conditions

Table 33. General operating conditions

Symbol Parameter Conditions Min Typ Max Unit

HSLV(1) = 0 1.71(2) - 3.6

Standard operating
VDD
voltage
HSLV = 1 1.71(2) - 2.7

Supply voltage for

the internal SMPS
VDDSMPS - VDD
step-down
converter
At least one I/O in
1.08 - 3.6
PG[15:2] used, HSLV = 0
Supply voltage for
VDDIO2 At least one I/O in
PG[15:2] I/Os 1.08 - 2.7
PG[15:2] used, HSLV = 1
PG[15:2] I/Os not used 0 - 3.6
V
USB used 3.0 - 3.6
VDDUSB USB supply voltage
USB not used 0 - 3.6
COMP used 1.58 - 3.6
DAC or OPAMP used 1.60 3.6
ADC used 1.62 - 3.6
Analog supply
VDDA VREFBUF used
voltage 1.8 - 3.6
(normal mode)
ADC, DAC, COMP,
OPAMP, and VREFBUF 0 - 3.6
not used
Backup domain
VBAT - 1.65(3) - 3.6
supply voltage

DS13086 Rev 6 153/334

299
Electrical characteristics STM32U585xx

Table 33. General operating conditions (continued)

Symbol Parameter Conditions Min Typ Max Unit

All I/Os except FT_c and Min(min(VDD, VDDA, VDDUSB,

-0.3 -
TT_xx pins VDDIO2) +3.6, 5.5)(4)(5)
Min(min(VBAT, VDDA,
Input voltage on FT_t pins
VIN I/O input voltage -0.3 - VDDUSB, VDDIO2)+ 3.6,
in VBAT mode
5.5)(4)(5)
FT_c I/Os -0.3 - 5.0
V
TT_xx I/Os -0.3 - VDDIOx + 0.3
Range 1 1.15 1.21 1.27

Internal regulator Range 2 1.05 1.1 1.15

VCORE
ON Range 3 0.95 1.0 1.05
Range 4 0.81 0.9 0.99
Range 1 - - 160

AHB clock Range 2 - - 110

fHCLK
frequency Range 3 - - 55
Range 4 - - 25
MHz
Range 1 - - 160
APB1, APB2, Range 2 - - 110
fPCLKx
APB3 clock
(x = 1, 2, 3) frequency Range 3 - - 55
Range 4 - - 25
LQFP48
UFQFPN48
See Section 6.9: Package thermal
LQFP64 characteristics for application appropriate
Power dissipation WLCSP90 thermal resistance and package. The power
PD at TA = 85 °C dissipation is then calculated according to
for suffix 6(6) LQFP100 ambient temperature (TA) and maximum
UFBGA132 junction temperature (TJ) and selected thermal
resistance.
LQFP144
UFBGA169
mW
LQFP48
UFQFPN48
See Section 6.9: Package thermal
LQFP64 characteristics for application appropriate
Power dissipation WLCSP90 thermal resistance and package. The power
PD at TA = 125 °C dissipation is then calculated according
for suffix 3(6) LQFP100 ambient temperature (TA) and maximum
UFBGA132 junction temperature (TJ) and selected thermal
resistance.
LQFP144
UFBGA169

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STM32U585xx Electrical characteristics

Table 33. General operating conditions (continued)

Symbol Parameter Conditions Min Typ Max Unit

Ambient Maximum power

–40 85
temperature dissipation
for suffix 6 Low-power dissipation(7) –40 105
TA
Ambient Maximum power
–40 125 °C
temperature dissipation
for suffix 3 Low-power dissipation(7) –40 130

Junction Suffix 6 version –40 105

TJ
temperature range Suffix 3 version –40 130
1. HSLV means high-speed low-voltage mode (refer to the GPIO section of the product reference manual).
2. When RESET is released, the functionality is guaranteed down to VBORx min.
3. In VBAT mode, the functionality is guaranteed down to VBOR_VBAT min.
4. This formula has to be applied only on the power supplies related to the I/O structure described by the pin definition table.
The maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDDUSB, VDDIO2)+3.6 V, and 5.5V.
5. For operation with voltage higher than Min (VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal pull-up and pull-down resistors
must be disabled.
6. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Section 6.9: Package thermal
characteristics).
7. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see Section 6.9:
Package thermal characteristics).

5.3.2 Operating conditions at power-up/power-down

The parameters given in the table below are derived from tests performed under the
ambient temperature condition summarized in Table 33.

Table 34. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Max Unit

VDD rise-time rate - 0 ∞

µs/V
tVDD ULPMEN = 0 (default value) 20 ∞
VDD fall-time rate
Standby mode with ULPMEN = 1 250 ∞ ms/V

5.3.3 Embedded reset and power control block characteristics

The parameters given in the table below are derived from tests performed under the
ambient temperature conditions summarized in Table 33.

Table 35. Embedded reset and power control block characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Reset temporization after BOR0 is

tRSTTEMPO(2) VDD rising - - 900 μs
detected

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299
Electrical characteristics STM32U585xx

Table 35. Embedded reset and power control block characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit

Rising edge 1.6 1.66 1.71

Falling edge, range 1, 2, 3 1.58 1.64 1.69
VBOR0 Brownout reset threshold 0
Falling edge, range 4 and
1.58 1.64 1.69
low-power modes
Rising edge 1.98 2.08 2.17
VBOR1 Brownout reset threshold 1
Falling edge 1.9 2.00 2.1
Rising edge 2.18 2.29 2.39
VBOR2 Brownout reset threshold 2
Falling edge 2.08 2.18 2.25
Rising edge 2.48 2.59 2.7
VBOR3 Brownout reset threshold 3
Falling edge 2.39 2.5 2.61
Rising edge 2.76 2.88 3.0
VBOR4 Brownout reset threshold 4
Falling edge 2.67 2.79 2.9

Programmable voltage detector Rising edge 2.03 2.13 2.23

VPVD0 V
threshold 0 Falling edge 1.93 2.03 2.12
Rising edge 2.18 2.29 2.39
VPVD1 PVD threshold 1
Falling edge 2.08 2.18 2.28
Rising edge 2.33 2.44 2.55
VPVD2 PVD threshold 2
Falling edge 2.23 2.34 2.44
Rising edge 2.47 2.59 2.7
VPVD3 PVD threshold 3
Falling edge 2.39 2.50 2.61
Rising edge 2.6 2.72 2.83
VPVD4 PVD threshold 4
Falling edge 2.5 2.62 2.73
Rising edge 2.76 2.88 3.0
VPVD5 PVD threshold 5
Falling edge 2.66 2.78 2.9
Rising edge 2.83 2.96 3.08
VPVD6 PVD threshold 6
Falling edge 2.76 2.88 3.0
Vhyst_BOR0 Hysteresis voltage of BOR0 - - 20 -
Hysteresis voltage of BOR mV
Vhyst_BOR_PVD - - 80 -
(except BOR0) and PVD
tBOR_PVD
BOR/PVD sampling period ULPMEN = 1 - 30 55 ms
_sampling

Additional BOR0 consumption if

IDD_BOR0(2) Standby mode - 60 - nA
ULPMEN = 0 versus ULPMEN = 1
BOR(3) (except BOR0) and PVD
IDD_BOR_PVD(2) - - 1 1.5 µA
consumption from VDD(4)
VBOR_VBAT VBAT brownout reset threshold - 1.58 - 1.65 V

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STM32U585xx Electrical characteristics

Table 35. Embedded reset and power control block characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit

tVBAT_BOR VBAT BOR sampling period

MONEN = 0(5) - 0.5 2.5 s
_sampling in VBAT mode
Rising edge 1.61 1.68 1.75
VAVM1 VDDA voltage monitor 1 threshold
Falling edge 1.58 1.65 1.71
Rising edge 1.77 1.86 1.95
VAVM2 VDDA voltage monitor 2 threshold V
Falling edge 1.73 1.82 1.9
VIO2VM VDDIO2 voltage monitor threshold - 0.96 1.01 1.05
VUVM VDDUSB voltage monitor threshold - 1.15 1.22 1.28
Vhyst_AVM Hysteresis of VDDA voltage monitor - - 40 - mV
Voltage monitor consumption from
IDD_VM(2) VDD (AVM1, AVM2, IO2VM or UVM - - 0.4 0.6
single instance) µA
VDDA voltage monitor consumption
IDD_AVM_A(2) - - 1.25 1.85
from VDDA (resistor bridge)
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Specified by design. Not tested in production
3. BOR0 is enabled in all modes (except Shutdown), and its consumption is therefore included in the supply current
characteristics tables.
4. This is also the consumption saved in Standby mode when ULPMEN = 1.
5. VBAT brownout reset monitoring is discontinuous when MONEN = 0 in PWR_BDCR1, and is continuous when MONEN = 1.

5.3.4 Embedded voltage reference

The parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in Table 33.

Table 36. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit

Range 1, 2, 3 1.175 1.215 1.255

VREFINT(1) Internal reference voltage Range 4 and V
1.170 1.215 1.260
low-power modes
ADC sampling time when reading
tS_vrefint(2)(3) - 4 - -
the internal reference voltage
µs
(3) Start time of reference voltage buffer
tstart_vrefint - - 4 6
when the ADC is enabled
IDD(VREFINTBUF) VREFINT buffer consumption from
(3) - - 1.5 2.1 µA
VDD when converted by the ADC
Internal reference voltage spread
∆VREFINT(4) VDD = 3 V - 6 11.5 mV
over the temperature range
TCoeff(4) Average temperature coefficient –40°C < TJ < +130 °C - 40 125 ppm/°C
(3)
ACoeff Long term stability 1000 hours, TJ = 25 °C - 400 1000 ppm

DS13086 Rev 6 157/334

299
Electrical characteristics STM32U585xx

Table 36. Embedded internal voltage reference (continued)

Symbol Parameter Conditions Min Typ Max Unit
(4)
VDDCoeff Average voltage coefficient 3.0 V ≤ VDD ≤ 3.6 V - 500 2900 ppm/V
VREFINT_DIV1(3) 1/4 reference voltage - 24 25 26
(3) %
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3(3) 3/4 reference voltage - 74 75 76
1. VREFINT does not take into account package and soldering effects.
2. The shortest sampling time for the application can be determined by multiple iterations.
3. Specified by design. Not tested in production.
4. Evaluated by characterization. Not tested in production.

Figure 27. VREFINT versus temperature

MSv69159V1

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Section 5.1.7: Current consumption
measurement.

Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The Flash memory access time is adjusted with the minimum wait-state number,
depending on the fHCLK frequency (refer to the tables “Number of wait states according
to CPU clock (HCLK) frequency” available in the product reference manual).
• When the peripherals are enabled, fPCLK = fHCLK.

158/334 DS13086 Rev 6

STM32U585xx Electrical characteristics

• The voltage scaling range is adjusted to fHCLK frequency as follows:

– Voltage range 1 for 110 MHz < fHCLK ≤ 160 MHz
– Voltage range 2 for 55 MHz < fHCLK ≤ 110 MHz
– Voltage range 3 for 25 MHz < fHCLK ≤ 55 MHz
– Voltage range 4 for fHCLK ≤ 25 MHz
The parameters given in the tables below are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 33.

DS13086 Rev 6 159/334

299
160/334

Electrical characteristics
Table 37. Current consumption in Run mode on LDO, code with data processing
running from Flash memory, ICACHE ON (1-way), prefetch ON(1)
Conditions Typ Max(2)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 1.75 2.10 3.10 4.65 7.70 2.60 3.40 6.40 12.00 21.00
16 1.30 1.65 2.65 4.20 7.25 2.10 2.90 5.90 11.00 20.00
fHCLK = fMSI, 12 1.05 1.40 2.40 3.95 7.00 1.80 2.70 5.60 11.00 20.00
all peripherals and AHB/APB 4 0.49 0.82 1.85 3.40 6.40 1.20 2.00 5.00 9.80 19.00
disabled, Range 4
Flash bank 2 in power down, 2 0.37 0.70 1.70 3.25 6.30 1.10 1.90 4.90 9.60 19.00
all SRAMs enabled 1 0.30 0.63 1.65 3.20 6.20 0.94 1.80 4.80 9.60 19.00
0.4 0.26 0.59 1.60 3.15 6.15 0.89 1.80 4.80 9.50 19.00
DS13086 Rev 6

0.1 0.24 0.57 1.55 3.15 6.15 0.87 1.80 4.70 9.50 19.00
Supply 160 13.50 14.50 16.00 18.50 23.50 17.00 19.00 26.00 37.00 57.00
IDD
current in fHCLK = PLL on HSE 16 MHz in mA
(Run) Run mode Range 1 140 12.00 12.50 14.50 17.00 21.50 15.00 17.00 24.00 35.00 55.00
bypass mode,
all peripherals and AHB/APB 120 10.50 11.00 13.00 15.50 20.00 14.00 15.00 23.00 33.00 53.00
disabled, 110 8.80 9.35 10.50 1300 16.50 11.00 13.00 18.00 26.00 41.00
Flash bank 2 in power down,
Range 2 72 6.00 6.50 10.00 10.00 14.00 7.80 9.30 15.00 23.00 38.00
all SRAMs enabled
64 5.40 5.95 9.50 9.50 13.50 7.10 8.70 14.00 22.00 38.00
fHCLK = fHSE bypass mode, 55 4.25 4.65 5.90 7.75 11.50 5.60 6.70 11.00 17.00 29.00
all peripherals and AHB/APB
disabled, Range 3
Flash bank 2 in power down, 32 2.70 3.10 4.30 6.10 9.60 3.80 5.00 8.80 15.00 27.00
all SRAMs enabled
1. The current consumption from SRAM is similar.

STM32U585xx
2. Evaluated by characterization. Not tested in production.
 Table 38. Current consumption in Run mode on SMPS, code with data processing

STM32U585xx
running from Flash memory, ICACHE ON (1-way), prefetch ON(1)
Conditions Typ at VDD = 1.8 V Max at 1.71 V ≤ VDD ≤ 3.6 V(2)(3)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 1.15 1.35 2.05 3.10 5.20 2.30 2.40 4.50 7.80 15.00
16 0.88 1.10 1.75 2.80 4.90 1.60 2.00 4.20 7.50 15.00
fHCLK = fMSI, 12 0.62 0.97 1.60 2.65 4.70 1.30 1.80 4.00 7.30 14.00
all peripherals and AHB/APB 4 0.34 0.56 1.20 2.20 4.40 0.77 1.40 3.50 6.80 14.00
disabled, Range 4
Flash bank 2 in power down, 2 0.22 0.46 1.15 2.20 4.25 0.64 1.30 3.50 6.80 14.00
all SRAMs enabled 1 0.18 0.40 1.10 2.15 4.20 0.60 1.20 3.40 6.70 14.00
0.4 0.16 0.36 1.05 2.10 4.20 0.57 1.10 3.40 6.70 14.00
0.1 0.15 0.34 1.05 2.10 4.20 0.55 1.10 3.40 6.70 14.00
DS13086 Rev 6

Supply 160 10.50 11.00 12.50 14.50 18.00 14.00 15.00 21.00 28.00 44.00
IDD
current in fHCLK = PLL on HSE 16 MHz in mA
(Run) Run mode Range 1 140 9.30 9.85 11.00 13.00 16.50 13.00 14.00 19.00 27.00 42.00
bypass mode,
all peripherals and AHB/APB 120 8.50 9.05 10.50 12.50 16.50 11.00 13.00 18.00 26.00 42.00
disabled, 110 6.95 7.40 8.55 10.00 13.00 8.90 9.90 14.00 20.00 32.00
Flash bank 2 in power down,
Range 2 72 4.35 4.70 5.65 7.10 9.80 6.00 6.80 11.00 17.00 28.00
all SRAMs enabled
64 3.95 4.30 5.25 6.65 9.40 5.40 6.30 11.00 16.00 27.00
fHCLK = fHSE bypass mode, 55 3.05 3.40 4.25 5.60 7.95 4.10 4.90 7.90 13.00 21.00
all peripherals and AHB/APB
disabled, Range 3

Electrical characteristics
Flash bank 2 in power down, 32 1.85 2.10 2.85 3.95 6.15 2.70 3.40 6.20 11.00 19.00
all SRAMs enabled
1. The current consumption from SRAM is similar.
2. Evaluated by characterization. Not tested in production.
3. The maximum value is at VDD = 1.71 V in Run mode on SMPS.
161/334
 Table 39. Current consumption in Run mode on SMPS, code with data processing
162/334

Electrical characteristics
running from Flash memory, ICACHE ON (1-way), prefetch ON, VDD = 3.0 V(1)
Conditions Typ at VDD = 3.0 V Max at VDD = 3.0 V(2)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 0.73 0.91 1.30 2.00 3.45 2.30 2.40 3.10 4.80 9.10
16 0.60 0.71 1.15 1.80 3.25 1.60 1.90 2.70 4.60 8.80
fHCLK = fMSI, 12 0.45 0.65 1.05 1.70 3.15 1.30 1.60 2.60 4.50 8.70
all peripherals and AHB/APB 4 0.23 0.38 0.82 1.50 2.80 0.60 0.97 2.30 4.30 8.40
disabled, Range 4
Flash bank 2 in power down, 2 0.17 0.31 0.74 1.40 2.85 0.49 0.84 2.20 4.20 8.40
all SRAMs enabled 1 0.15 0.29 0.73 1.40 2.80 0.46 0.81 2.20 4.20 8.40
0.4 0.13 0.27 0.72 1.40 2.75 0.44 0.79 2.20 4.20 8.30
0.1 0.12 0.26 0.72 1.35 2.75 0.44 0.78 2.20 4.10 8.30
DS13086 Rev 6

Supply 160 7.15 7.55 8.55 9.90 12.50 14.00 15.00 16.00 19.00 28.00
IDD
current in fHCLK = PLL on HSE 16 MHz in mA
(Run) Run mode Range 1 140 6.35 6.75 7.70 9.05 11.50 13.00 13.00 15.00 17.00 27.00
bypass mode,
all peripherals and AHB/APB 120 5.80 6.20 7.20 8.60 11.00 11.00 12.00 13.00 17.00 26.00
disabled, 110 4.40 4.70 5.40 6.35 8.20 8.90 9.20 11.00 13.00 19.00
Flash bank 2 in power down,
Range 2 72 3.05 3.35 4.05 5.10 7.00 6.00 6.20 7.40 11.00 18.00
all SRAMs enabled
64 2.80 3.10 3.80 4.80 6.70 5.40 5.70 6.90 11.00 18.00
fHCLK = fHSE bypass mode, 55 2.20 2.45 3.05 3.95 5.55 4.00 4.40 5.40 7.90 14.00
all peripherals and AHB/APB
disabled, Range 3
Flash bank 2 in power down, 32 1.40 1.60 2.15 2.95 4.50 2.60 3.00 4.30 6.80 13.00
all SRAMs enabled
1. The current consumption from SRAM is similar.

STM32U585xx
2. Evaluated by characterization. Not tested in production.
 Table 40. Typical current consumption in Run mode on LDO, with different codes

STM32U585xx
running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON
Conditions Typ Typ

Symbol
Parameter Unit Unit
- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 1.65 1.65 1.65 68.8 68.8 68.8
fHCLK = fMSI = 24 MHz,
CoreMark 1.55 1.60 1.60 64.6 66.7 66.7
all peripherals disabled,
Supply SecureMark 1.80 1.80 1.80 75.0 75.0 75.0
IDD Flash bank 2 in power down, µA/
current in Range 4 mA
(Run) Run mode SRAM2 enabled, Dhrystone 2.1 1.65 1.65 1.65 68.8 68.8 68.8 MHz
SRAM1, SRAM3, SRAM4 in
Fibonacci 1.30 1.30 1.30 54.2 54.2 54.2
power down
while(1) 1.20 1.20 1.20 50.0 50.0 50.0

Table 41. Typical current consumption in Run mode on LDO, with different codes
DS13086 Rev 6

running from Flash memory, ICACHE ON (1-way), prefetch ON(1)

Conditions Typ Typ
Symbol

Parameter Unit Unit

- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 1.75 1.75 1.75 72.9 72.9 72.9
CoreMark 1.65 1.65 1.65 68.8 68.8 68.8
fHCLK = fMSI = 24 MHz,
Supply SecureMark 1.85 1.85 1.90 77.1 77.1 79.2
IDD all peripherals disabled, µA/
current in Range 4 mA
(Run) Run mode Flash bank 2 in power down, Dhrystone 2.1 1.75 1.75 1.75 72.9 72.9 72.9 MHz
all SRAMs enabled
Fibonacci 1.40 1.40 1.40 58.3 58.3 58.3

Electrical characteristics
While(1) 1.30 1.30 1.30 54.2 54.2 54.2
163/334
 Table 41. Typical current consumption in Run mode on LDO, with different codes
164/334

Electrical characteristics
running from Flash memory, ICACHE ON (1-way), prefetch ON(1) (continued)
Conditions Typ Typ

Symbol
Parameter Unit Unit
- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 13.50 13.50 13.50 84.4 84.4 84.4
fHCLK = fPLL = 160 MHz,
CoreMark 13.50 13.50 13.50 84.4 84.4 84.4
PLL on HSE 16 MHz in bypass
mode, SecureMark 15.00 15.00 15.00 93.8 93.8 93.8
Range 1
all peripherals disabled, Dhrystone 2.1 14.00 14.00 14.00 87.5 87.5 87.5
Flash bank 2 in power down,
Fibonacci 10.50 10.50 10.50 65.6 65.6 65.6
all SRAMs enabled
While(1) 10.00 10.00 10.00 62.5 62.5 62.5
Reduced Code 8.80 8.80 8.85 80.0 80.0 80.5
fHCLK = fPLL = 110 MHz,
CoreMark 8.60 8.65 8.65 78.2 78.6 78.6
DS13086 Rev 6

PLL on HSE 16 MHz in bypass

Supply mode, SecureMark 9.65 9.70 9.70 87.7 88.2 88.2
IDD µA/
current in Range 2 mA
(Run) Run mode all peripherals disabled, Dhrystone 2.1 9.05 9.05 9.10 82.3 82.3 82.7 MHz
Flash bank 2 in power down,
Fibonacci 6.80 6.80 6.80 61.8 61.8 61.8
all SRAMs enabled
While(1) 6.55 6.55 6.60 59.5 59.5 60.0
Reduced Code 4.15 4.25 4.25 75.5 77.3 77.3
CoreMark 4.15 4.20 4.25 75.5 76.4 77.3
fHCLK = fHSE = 55 MHz,
all peripherals disable, SecureMark 4.65 4.70 4.75 84.5 85.5 86.4
Range 3
Flash bank 2 in power down, Dhrystone 2.1 4.35 4.40 4.40 79.1 80.0 80.0
all SRAMs enabled
Fibonacci 3.25 3.30 3.35 59.1 60.0 60.9
While(1) 3.05 3.10 3.15 55.5 56.4 57.3
1. The current consumption from SRAM is similar.

STM32U585xx
 STM32U585xx
Table 42. Typical current consumption in Run mode on SMPS, with different codes
running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON
Conditions Typ Typ

Symbol
Parameter Unit Unit
- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 1.10 0.69 0.64 45.8 28.5 26.5
fHCLK = fMSI = 24 MHz,
CoreMark 1.05 0.68 0.61 43.8 28.3 25.4
all peripherals disabled,
Supply SecureMark 1.20 0.79 0.72 50.0 32.9 30.0
IDD Flash bank 2 in power down, µA/
current in Range 4 mA
(Run) SRAM2 enabled, Dhrystone 2.1 1.10 0.69 0.64 45.8 28.5 26.7 MHz
Run mode
SRAM1, SRAM3, SRAM4 in
Fibonacci 0.89 0.59 0.51 37.1 24.4 21.3
power down
while(1) 0.77 0.54 0.47 32.1 22.3 19.5
DS13086 Rev 6

Table 43. Typical current consumption in Run mode on SMPS, with different codes
running from Flash memory, ICACHE ON (1-way), prefetch ON(1)
Conditions Typ Typ
Symbol

Parameter Unit Unit

- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 1.15 0.73 0.68 47.9 30.2 28.3
CoreMark 1.10 0.72 0.66 45.8 30.0 27.5
fHCLK = fMSI = 24 MHz,
Supply SecureMark 1.25 0.85 0.77 52.1 35.2 32.1
IDD all peripherals disabled, µA/
current in Range 4 mA
(Run) Flash bank 2 in power down, Dhrystone 2.1 1.15 0.75 0.69 47.9 31.0 28.8 MHz
Run mode
all SRAMs enabled

Electrical characteristics
Fibonacci 0.97 0.65 0.58 40.4 26.9 24.2
while(1) 0.89 0.61 0.55 36.9 25.2 22.7
165/334
 Table 43. Typical current consumption in Run mode on SMPS, with different codes
166/334

Electrical characteristics
running from Flash memory, ICACHE ON (1-way), prefetch ON(1) (continued)
Conditions Typ Typ

Symbol
Parameter Unit Unit
- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 10.50 7.15 6.70 65.6 44.7 41.9
fHCLK = fPLL = 160 MHz,
CoreMark 10.50 7.05 6.55 65.6 44.1 40.9
PLL on HSE 16 MHz in bypass
mode, SecureMark 11.50 7.85 7.35 71.9 49.1 45.9
Range 1
all peripherals disabled, Dhrystone 2.1 11.00 7.40 6.90 68.8 46.3 43.1
Flash bank 2 in power down,
Fibonacci 8.25 5.65 5.30 51.6 35.3 33.1
all SRAMs enabled
while(1) 7.90 5.45 5.10 49.4 34.1 31.9
Reduced Code 6.40 4.40 4.15 58.2 40.0 37.7
fHCLK = fPLL = 110 MHz,
CoreMark 6.25 4.30 4.05 56.8 39.1 36.8
DS13086 Rev 6

PLL on HSE 16 MHz in bypass

Supply mode, SecureMark 7.00 4.80 4.50 63.6 43.6 40.9
IDD µA/
current in Range 2 mA
(Run) all peripherals disabled, Dhrystone 2.1 6.55 4.50 4.25 59.5 40.9 38.6 MHz
Run mode
Flash bank 2 in power down,
Fibonacci 5.00 3.50 3.30 45.5 31.8 30.0
all SRAMs enabled
while(1) 4.80 3.35 3.20 43.6 30.5 29.1
Reduced Code 3.05 2.20 2.15 55.5 40.0 39.1
CoreMark 3.05 2.20 2.10 55.5 40.0 38.2
fHCLK = fHSE = 55 MHz,
all peripherals disabled, SecureMark 3.40 2.45 2.30 61.8 44.5 41.8
Range 3
Flash bank 2 in power down, Dhrystone 2.1 3.20 2.30 2.20 58.2 41.8 40.0
all SRAMs enabled
Fibonacci 2.40 1.80 1.75 43.6 32.7 31.8
while(1) 2.30 1.70 1.65 41.8 30.9 30.0
1. The current consumption from SRAM is similar.

STM32U585xx
 Table 44. Current consumption in Sleep mode on LDO, Flash memory in power down

STM32U585xx
Conditions Typ Max(1)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 0.61 0.94 1.95 3.50 6.50 1.20 2.10 5.00 9.70 19.00
16 0.49 0.81 1.80 3.35 6.40 1.10 1.90 4.90 9.50 19.00
12 0.43 0.75 1.75 3.30 6.30 0.95 1.90 4.80 9.50 19.00

fHCLK = fMSI, 4 0.25 0.58 1.55 3.10 6.15 0.76 1.70 4.60 9.30 19.00
Range 4
all peripherals disabled 2 0.22 0.55 1.55 3.10 6.10 0.72 1.60 4.60 9.30 19.00
1 0.21 0.53 1.55 3.05 6.10 0.71 1.60 4.60 9.20 19.00
0.4 0.19 0.52 1.50 3.05 6.05 0.69 1.60 4.50 9.20 19.00
Supply
IDD current in 0.1 0.19 0.52 1.50 3.05 6.10 0.69 1.60 4.50 9.20 19.00
mA
(Sleep) Sleep
DS13086 Rev 6

160 4.35 4.95 6.65 9.10 13.50 6.10 8.10 15.00 26.00 46.00
mode
Range 1 140 3.90 4.50 6.15 8.65 13.50 5.60 7.60 15.00 25.00 46.00
fHCLK = PLL on HSE 16 MHz 120 3.45 4.05 5.75 8.20 13.00 5.10 7.10 14.00 25.00 46.00
in bypass mode,
all peripherals disabled 110 3.25 3.75 5.20 7.35 11.50 4.50 6.00 12.00 20.00 35.00
Range 2 72 2.15 2.65 4.05 6.15 10.00 3.30 4.80 9.90 18.00 34.00
64 2.00 2.50 3.90 6.00 9.95 3.20 4.70 9.80 18.00 33.00

fHCLK = fHSE bypass mode, 55 1.45 1.85 3.05 4.85 8.40 2.30 3.40 7.30 14.00 26.00
Range 3
all peripherals disabled 32 1.00 1.40 2.60 4.40 7.85 1.80 2.90 6.80 13.00 25.00
1. Evaluated by characterization. Not tested in production.

Electrical characteristics
167/334
 Table 45. Current consumption in Sleep mode on SMPS, Flash memory in power down
168/334

Electrical characteristics
Conditions Typ at VDD = 1.8 V Max at 1.71 V ≤ VDD ≤ 3.6 V(1) (2)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 0.41 0.63 1.25 2.25 4.40 0.73 1.40 3.60 6.80 14.00
16 0.27 0.53 1.20 2.20 4.30 0.57 1.30 3.50 6.70 14.00
12 0.24 0.48 1.15 2.20 4.25 0.53 1.20 3.50 6.70 14.00

fHCLK = fMSI, 4 0.14 0.34 1.05 2.05 4.10 0.42 1.10 3.40 6.50 13.00
Range 4
all peripherals disabled 2 0.12 0.34 1.05 2.05 4.10 0.39 1.00 3.40 6.50 13.00
1 0.11 0.33 1.05 2.05 4.10 0.38 0.99 3.40 6.50 13.00
0.4 0.10 0.31 1.05 2.05 4.10 0.38 0.97 3.40 6.50 13.00
Supply 0.1 0.10 0.31 1.05 2.05 4.10 0.37 0.97 3.40 6.50 13.00
IDD
current in mA
DS13086 Rev 6

(Sleep) Sleep mode 160 3.50 3.95 5.20 7.00 10.50 4.80 6.20 12.00 19.00 34.00
Range 1 140 3.10 3.60 4.80 6.60 10.00 4.30 5.80 12.00 19.00 34.00
fHCLK = PLL on HSE 16 MHz 120 2.80 3.25 4.50 6.30 9.70 4.00 5.40 11.00 19.00 33.00
in bypass mode,
all peripherals disabled 110 2.60 3.00 4.10 5.75 8.65 3.50 4.70 8.80 15.00 26.00
Range 2 72 1.65 2.00 2.90 4.30 7.00 2.40 3.50 7.40 13.00 24.00
64 1.55 1.90 2.80 4.20 6.90 2.30 3.40 7.30 13.00 24.00

fHCLK = fHSE bypass mode, 55 1.10 1.40 2.25 3.55 5.90 1.70 2.50 5.60 9.80 19.00
Range 3
all peripherals disabled 32 0.85 1.10 1.90 3.15 5.60 1.40 2.20 5.10 9.40 18.00
1. Evaluated by characterization. Not tested in production.
2. The maximum value is at VDD = 1.71 V in Sleep mode on SMPS.

STM32U585xx
 Table 46. Current consumption in Sleep mode on SMPS,

STM32U585xx
Flash memory in power down, VDD = 3.0 V
Conditions Typ at VDD = 3.0 V Max at VDD = 3.0 V(1)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 0.26 0.40 0.83 1.50 2.80 0.66 1.20 2.20 4.20 8.20
16 0.20 0.33 0.77 1.40 2.80 0.54 0.99 2.10 4.10 8.20
12 0.17 0.31 0.75 1.40 2.75 0.49 0.92 2.10 4.10 8.10

fHCLK = fMSI, 4 0.10 0.24 0.66 1.30 2.70 0.30 0.71 2.00 3.90 8.10
Range 4
all peripherals disabled 2 0.08 0.22 0.66 1.30 2.65 0.27 0.68 2.00 3.90 8.00
1 0.08 0.22 0.66 1.30 2.65 0.26 0.67 2.00 3.90 8.00
0.4 0.07 0.21 0.65 1.30 2.65 0.26 0.64 2.00 3.90 8.00
Supply 0.1 0.07 0.21 0.65 1.30 2.65 0.26 0.65 2.00 3.90 8.00
DS13086 Rev 6

IDD
current in mA
(Sleep) Sleep mode 160 2.50 2.85 3.75 5.05 7.40 4.50 5.00 7.40 13.00 22.00
Range 1 140 2.25 2.60 3.50 4.75 7.15 4.00 4.60 7.20 12.00 22.00
fHCLK = PLL on HSE 16 MHz 120 2.05 2.40 3.25 4.55 6.90 3.60 4.20 6.90 12.00 21.00
in bypass mode,
all peripherals disabled 110 1.95 2.25 3.00 4.10 6.05 3.20 3.60 5.70 9.30 17.00
Range 2 72 1.30 1.55 2.20 3.20 5.10 2.20 2.60 4.80 8.30 16.00
64 1.20 1.45 2.15 3.15 5.00 2.00 2.50 4.70 8.20 16.00

fHCLK = fHSE bypass mode, 55 0.92 1.10 1.70 2.55 4.15 1.40 1.90 3.60 6.30 12.00
Range 3
all peripherals disabled 32 0.70 0.89 1.45 2.30 3.95 1.10 1.60 3.30 6.00 12.00

Electrical characteristics
1. Evaluated by characterization. Not tested in production.
169/334
 Table 47. SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and SMPS
170/334

Electrical characteristics
Conditions Typ Max
Symbol Parameter Unit
Voltage fHCLK
- 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
scaling (MHz)

Range 4 24 0.02 0.05 0.16 0.33 0.68 0.06 0.15 0.48 1.00 2.05
SRAM1 supply current in Range 1 160 0.04 0.10 0.28 0.55 1.07 0.15 0.30 0.83 1.65 3.20
IDD
Run/Sleep mode (SRAM1PD = 1
(SRAM1) versus SRAM1PD = 0) Range 2 110 0.03 0.08 0.23 0.47 0.94 0.11 0.24 0.70 1.41 2.82
Range 3 55 0.02 0.06 0.19 0.40 0.81 0.08 0.19 0.58 1.20 2.43
LDO
Range 4 24 0.04 0.13 0.41 0.87 1.78 0.15 0.39 1.24 2.62 5.34
SRAM3 supply current in Range 1 160 0.11 0.26 0.73 1.44 2.80 0.39 0.79 2.18 4.31 8.40
IDD
Run/Sleep mode (SRAM3PD = 1
(SRAM3) versus SRAM3PD = 0) Range 2 110 0.08 0.21 0.60 1.22 2.44 0.28 0.62 1.81 3.67 7.32
Range 3 55 0.06 0.16 0.50 1.04 2.09 0.20 0.49 1.50 3.11 6.28
mA
DS13086 Rev 6

Range 4 24 0.01 0.02 0.06 0.10 0.26 0.02 0.06 0.19 0.31 0.78
SRAM1 supply current in Range 1 160 0.02 0.05 0.14 0.28 0.55 0.07 0.15 0.43 0.84 1.64
IDD
Run/Sleep mode (SRAM1PD = 1
(SRAM1) versus SRAM1PD = 0) Range 2 110 0.01 0.04 0.12 0.23 0.46 0.05 0.12 0.36 0.70 1.37

SMPS, Range 3 55 0.01 0.03 0.09 0.18 0.36 0.04 0.09 0.27 0.55 1.09
VDD = 3.0 V Range 4 24 0.02 0.05 0.17 0.32 0.69 0.06 0.16 0.51 0.95 2.07
SRAM3 supply current in Range 1 160 0.06 0.13 0.37 0.73 1.43 0.20 0.40 1.12 2.20 4.28
IDD
Run/Sleep mode (SRAM3PD = 1
(SRAM3) versus SRAM3PD = 0) Range 2 100 0.04 0.10 0.30 0.61 1.19 0.14 0.31 0.91 1.84 3.57
Range 3 55 0.03 0.08 0.23 0.48 0.95 0.09 0.23 0.70 1.45 2.86

STM32U585xx
 Table 47. SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and SMPS (continued)

STM32U585xx
Conditions Typ Max
Symbol Parameter Unit
Voltage fHCLK
- 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
scaling (MHz)

Range 4 24 0.01 0.03 0.11 0.17 0.43 0.04 0.11 0.34 0.55 1.37
SRAM1 supply current in Range 1 160 0.03 0.09 0.24 0.47 0.91 0.13 0.27 0.75 1.47 2.88
IDD
Run/Sleep mode (SRAM1PD = 1
(SRAM1) versus SRAM1PD = 0) Range 2 110 0.02 0.07 0.20 0.39 0.76 0.09 0.21 0.63 1.23 2.41
Range 3 55 0.02 0.05 0.15 0.31 0.60 0.06 0.16 0.48 0.97 1.91
SMPS(1) mA
Range 4 24 0.03 0.09 0.28 0.53 1.15 0.11 0.28 0.89 1.66 3.62
SRAM3 supply current in Range 1 160 0.09 0.22 0.62 1.22 2.38 0.35 0.71 1.96 3.87 7.52
IDD
Run/Sleep mode (SRAM3PD = 1
(SRAM3) versus SRAM3PD = 0) Range 2 100 0.06 0.17 0.51 1.02 1.98 0.24 0.54 1.60 3.22 6.26
Range 3 55 0.04 0.13 0.39 0.80 1.59 0.16 0.40 1.24 2.54 5.01
DS13086 Rev 6

1. The typical value is measured at VDD = 1.8 V. The maximum value is for 1.71 V ≤ VDD ≤ 3.6 V and is at VDD = 1.71 V in Run/Sleep mode on SMPS.

Table 48. Static power consumption of Flash banks, when supplied by LDO/SMPS
Typ Max
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

IDD Flash bank 1 static consumption in normal mode

(1) 45.0 50.0 50.0 50.0 100.0 100.0 100.0 100.0 100.0 150.0
(Flash_Bank1) (PD1 = 1 versus PD1 = 0)

IDD Flash bank 2 static consumption in normal mode

(1) 45.0 50.0 50.0 50.0 100.0 100.0 100.0 100.0 100.0 150.0
(Flash_Bank2) (PD2 = 1 versus PD2 = 0) µA

Electrical characteristics
One Flash bank additional static consumption in
IDD
(2) normal mode versus low-power mode 25.0 25.0 25.0 25.0 50.0 40.0 40.0 40.0 40.0 70.0
(Flash_Bank_LPM)
(LPM = 0 versus LPM = 1)
1. When one bank is in power down, this consumption is saved. When Flash memory is in power down in Sleep mode (SLEEP_PD =1 ), Bank 1 and Bank 2 are in
power down.
2. If no bank is in power-down, the Flash memory additional static consumption in normal mode versus low-power mode is 2 x IDD(Flash_Bank_LPM).
171/334
 Table 49. Current consumption in Stop 0 mode on LDO
172/334

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 110 280 770 1500 3000 400 840 2400 4500 9000
Supply current in Stop 0 mode,
regulator in Range 4, 2.4 115 290 805 1600 3050 420 870 2500 4800 9200
RTC disabled, 3.0 115 295 820 1600 3150 420 890 2500 4800 9500
8-Kbyte SRAM2 + ICACHE 3.3 115 295 820 1600 3150 420 890 2500 4800 9500
retained
3.6 115 295 825 1600 3150 420 890 2500 4800 9500
IDD(Stop 0) µA
1.8 125 305 840 1650 3300 460 920 2600 5000 9900
Supply current in Stop 0 mode, 2.4 125 315 875 1750 3400 460 950 2700 5300 11000
regulator in Range 4,
3.0 125 320 895 1800 3500 460 960 2700 5400 11000
RTC disabled,
All SRAMs retained 3.3 130 320 890 1750 3500 470 960 2700 5300 11000
DS13086 Rev 6

3.6 130 320 895 1800 3500 470 960 2700 5400 11000
1. Evaluated by characterization. Not tested in production.

STM32U585xx
 Table 50. Current consumption in Stop 0 mode on SMPS

STM32U585xx
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 54.5 160 535 1050 2100 200 480 1700 3200 6300
Supply current in Stop 0 mode,
regulator in Range 4, 2.4 38.5 115 360 890 1650 140 350 1100 2700 5000
RTC disabled, 3.0 39.5 115 340 685 1400 150 350 1100 2100 4200
8-Kbyte SRAM2 + ICACHE 3.3 37.0 105 315 640 1300 140 320 950 2000 3900
retained
3.6 35.5 100 295 605 1200 130 300 890 1900 3600
IDD(Stop 0) µA
1.8 61.5 175 515 1200 2350 230 530 1600 3600 7100
Supply current in Stop 0 mode, 2.4 43.5 125 400 930 1850 160 380 1200 2800 5600
regulator in Range 4,
3.0 44.5 125 370 770 1550 170 380 1200 2400 4700
RTC disabled,
All SRAM retained 3.3 41.5 115 345 705 1400 150 350 1100 2200 4200
DS13086 Rev 6

3.6 40.0 110 325 665 1350 150 330 980 2000 4100
1. Evaluated by characterization. Not tested in production.

Table 51. Current consumption in Stop 1 mode on LDO

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 82.0 250 755 1500 3000 300 750 2300 4500 9000
Supply current in Stop 1 mode, 2.4 83.5 250 750 1500 3050 310 750 2300 4500 9200

Electrical characteristics
RTC disabled, (2)
IDD (Stop 1) 3.0 87.5 255 755 1550 3050 320 770 2300 4700 9200 µA
8-Kbyte SRAM2 + ICACHE
retained 3.3 84.0 250 755 1550 3050 310 750 2300 4700 9200
3.6 95.5 255 760 1550 3050 350 770 2300 4700 9200
173/334
 Table 51. Current consumption in Stop 1 mode on LDO (continued)
174/334

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 89.0 255 760 1550 3100 330 770 2300 4700 9300
2.4 94.0 265 795 1600 3200 340 800 2400 4800 9600
Supply current in Stop 1 mode,
IDD (Stop 1) RTC disabled, 3.0 100.0 270 815 1650 3300 370 810 2500 5000 9900
All SRAMs retained
3.3 100.0 275 815 1650 3300 370 830 2500 5000 9900
3.6 110.0 275 825 1650 3300 400 830 2500 5000 9900
1.8 81.5 240 695 1400 2800 - - - - -
Supply current in Stop 1 mode, 2.4 88.5 245 730 1450 2900 - - - - -
RTC(3) clocked by LSI 32 kHz,
3.0 93.0 245 745 1500 2950 - - - - -
8-Kbyte SRAM2 + ICACHE
retained 3.3 89.0 250 745 1500 2950 - - - - -
DS13086 Rev 6

3.6 87.5 250 755 1500 2950 - - - - -

µA
1.8 81.0 240 715 1450 2800 - - - - -
Supply current in Stop 1 mode,
2.4 81.5 245 720 1450 2800 - - - - -
RTC(3) clocked by LSE
IDD(Stop 1 bypassed at 32768 Hz,
3.0 90.5 245 720 1450 2800 - - - - -
with RTC)
8-Kbyte SRAM2 + ICACHE
3.3 83.5 245 725 1450 2800 - - - - -
retained
3.6 94.0 255 730 1450 2850 - - - - -
1.8 83.5 245 730 1500 2950 - - - - -
Supply current in Stop 1 mode,
RTC(3) clocked by LSE quartz in 2.4 84.0 240 730 1500 2950 - - - - -
medium low-drive mode,
3.0 88.0 245 735 1500 2950 - - - - -
LSESYSEN = 0 in RCC_BDCR,
8-Kbyte SRAM2 + ICACHE 3.3 84.5 245 735 1500 2950 - - - - -
retained
3.6 84.5 250 740 1500 2950 - - - - -

STM32U585xx
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
 Table 52. Current consumption during wakeup from Stop 1 mode on LDO

STM32U585xx
Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Wakeup clock is MSI 24 MHz 2.08

Electrical charge consumed during wakeup from
QDD(wakeup from Stop 1) Wakeup clock is HSI 16 MHz 3.0 2.03 nAs
Stop 1 mode
Wakeup clock is MSI 1 MHz 4.80

Table 53. Current consumption in Stop 1 mode on SMPS

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 54.5 160 535 1050 2100 200 480 1700 3200 6300
DS13086 Rev 6

Supply current in Stop 1 mode, 2.4 38.5 115 350 890 1650 140 350 1100 2700 5000
RTC disabled, (2)
3.0 39.5 115 340 685 1400 150 350 1100 2100 4200
8-Kbyte SRAM2 + ICACHE
retained 3.3 37.0 105 315 640 1300 140 320 950 2000 3900
3.6 35.5 100 295 600 1200 130 300 890 1800 3600
IDD(Stop 1) µA
1.8 61.5 175 515 1200 2350 230 530 1600 3600 7100
2.4 43.5 125 390 930 1850 160 380 1200 2800 5600
Supply current in Stop 1 mode,
RTC disabled, 3.0 44.0 125 370 770 1550 160 380 1200 2400 4700
All SRAMs retained
3.3 41.5 115 345 705 1400 150 350 1100 2200 4200
3.6 39.5 110 325 665 1350 150 330 980 2000 4100

Electrical characteristics
175/334
 Table 53. Current consumption in Stop 1 mode on SMPS (continued)
176/334

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 54.5 160 535 1050 2100 - - - - -

Supply current in Stop 1 mode, 2.4 39.0 115 350 890 1650 - - - - -
RTC(3) clocked by LSI 32 kHz,
3.0 40.0 115 340 685 1400 - - - - -
8-Kbyte SRAM2 + ICACHE
retained 3.3 37.5 110 315 640 1300 - - - - -
3.6 36.0 100 295 600 1200 - - - - -
1.8 65.0 180 535 1050 2100 - - - - -
Supply current in Stop 1 mode,
2.4 50.0 140 415 850 1700 - - - - -
RTC(3) clocked by LSE
IDD(Stop 1
bypassed at 32768 Hz, 3.0 42.0 120 345 705 1400 - - - - - µA
with RTC)
8-Kbyte SRAM2 + ICACHE
3.3 39.0 110 320 655 1250 - - - - -
retained
DS13086 Rev 6

3.6 38.0 105 300 620 1200 - - - - -

1.8 54.0 155 610 1050 2100 - - - - -
Supply current in Stop 1 mode,
RTC(3) clocked by LSE quartz 2.4 39.5 150 490 875 1600 - - - - -
in medium low-drive mode,
3.0 39.5 115 335 680 1350 - - - - -
LSESYSEN = 0 in RCC_BDCR,
8-Kbyte SRAM2 + ICACHE 3.3 37.0 105 310 630 1250 - - - - -
retained
3.6 35.5 100 295 590 1150 - - - - -
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.

STM32U585xx
 STM32U585xx
Table 54. Current consumption during wakeup from Stop 1 mode on SMPS
Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Wakeup clock is MSI 24 MHz 1.10

Electrical charge consumed during wakeup from
QDD(wakeup from Stop 1) Wakeup clock is HSI 16 MHz 3.0 0.38 nAs
Stop 1 mode
Wakeup clock is MSI 1 MHz 1.33

Table 55. Current consumption in Stop 2 mode on LDO

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 8.90 23.5 70.0 145 305 33.0 71.0 210.0 440.0 920.0
DS13086 Rev 6

Supply current in Stop 2 mode, 2.4 8.90 23.5 70.5 145 310 33.0 71.0 220.0 440.0 930.0
RTC disabled, (2)
3.0 9.05 24.0 71.5 150 315 33.0 72.0 220.0 450.0 950.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 9.30 24.5 73.0 150 320 34.0 74.0 220.0 450.0 960.0
3.6 10.00 26.0 75.5 155 325 37.0 78.0 230.0 470.0 980.0
IDD(Stop 2) µA
1.8 20.00 48.5 145.0 310 680 73.0 150.0 440.0 930.0 2100.0
2.4 20.00 48.5 145.0 315 680 73.0 150.0 440.0 950.0 2100.0
Supply current in Stop 2 mode,
RTC disabled, 3.0 20.50 48.5 145.0 315 685 74.0 150.0 440.0 950.0 2100.0
All SRAMs retained
3.3 20.50 49.5 150.0 315 690 74.0 150.0 450.0 950.0 2100.0
3.6 22.00 51.0 150.0 320 700 80.0 160.0 450.0 960.0 2100.0

Electrical characteristics
177/334
 Table 55. Current consumption in Stop 2 mode on LDO (continued)
178/334

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 9.45 24.0 71.5 150 315 35.0 72.0 220.0 450.0 950.0
Supply current in Stop 2 mode, 2.4 9.50 24.0 71.5 150 315 35.0 72.0 220.0 450.0 950.0
RTC(3) clocked by LSI 32 kHz,
3.0 9.60 24.5 73.0 150 320 35.0 74.0 220.0 450.0 960.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 9.30 25.0 74.0 155 325 34.0 75.0 230.0 470.0 980.0
3.6 11.00 26.5 77.0 160 335 40.0 80.0 240.0 480.0 1100.0
1.8 9.15 23.5 70.0 145 305 33.0 71.0 210.0 440.0 920.0
Supply current in Stop 2 mode, 2.4 9.20 23.5 70.5 145 310 34.0 71.0 220.0 440.0 930.0
RTC(3) clocked by LSI 250 Hz,
3.0 9.20 24.0 71.5 150 315 34.0 72.0 220.0 450.0 950.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 9.50 24.5 73.0 150 320 35.0 74.0 220.0 450.0 960.0
DS13086 Rev 6

IDD(Stop 2 3.6 10.50 26.0 76.0 155 325 38.0 78.0 230.0 470.0 980.0
µA
with RTC) 1.8 9.15 24.0 71.5 150 315 33.0 72.0 220.0 450.0 950.0
Supply current in Stop 2 mode,
2.4 9.20 24.0 71.5 150 315 34.0 72.0 220.0 450.0 950.0
RTC(3) clocked by LSE
bypassed at 32768 Hz, 3.0 9.50 24.0 72.5 150 320 35.0 72.0 220.0 450.0 960.0
8-Kbyte SRAM2 + ICACHE
3.3 9.50 25.0 74.0 155 325 35.0 75.0 230.0 470.0 980.0
retained
3.6 10.50 26.5 76.5 160 335 38.0 80.0 230.0 480.0 1100.0
1.8 9.35 23.5 70.5 145 305 - - - - -
Supply current in Stop 2 mode,
2.4 9.40 24.0 71.0 150 310 - - - - -
RTC(3) clocked by LSE quartz in
medium low-drive mode, 3.0 9.25 24.0 72.0 150 315 - - - - -
8-Kbyte SRAM2 + ICACHE
3.3 9.65 25.0 73.5 150 320 - - - - -
retained
3.6 10.50 26.5 76.0 155 325 - - - - -

STM32U585xx
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
 Table 56. SRAM static power consumption in Stop 2 when supplied by LDO

STM32U585xx
Typ Max(1)
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

SRAM1 64-Kbyte page x static consumption

IDD(SRAM1_64kB)(2) 0.8 2.0 6.0 13.2 28.6 3.0 6.0 18.0 40.0 86.0
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
SRAM2 8-Kbyte page 1 static consumption
IDD(SRAM2_8KB)(3) 0.2 0.4 1.4 3.1 6.5 0.7 1.4 4.4 10.0 20.0
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
SRAM2 56-Kbyte page 2 static consumption
IDD(SRAM2_56KB)(3) 1.0 2.6 8.0 17.6 37.9 3.6 7.7 25.0 53.0 120.0
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
SRAM3 64-Kbyte page x static consumption
IDD(SRAM3_64kB)(4) 0.8 1.9 5.7 12.6 27.5 3.0 5.8 18.0 38.0 83.0
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)
SRAM4 static consumption
IDD(SRAM4) 0.3 0.6 1.8 3.9 8.2 1.0 1.8 5.4 12.0 25.0 µA
(SRAM4PDS = 1 versus SRAM4PDS = 0)
DS13086 Rev 6

ICACHE SRAM static consumption

IDD(ICRAM) 0.1 0.4 1.3 2.9 5.7 0.5 1.3 4.0 8.6 18.0
(ICRAMPDS = 1 versus ICRAMPDS = 0)
DCACHE1 SRAM static consumption
IDD(DC1RAM) 0.1 0.2 0.7 1.5 3.0 0.3 0.7 2.3 4.6 9.1
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
DMA2D SRAM static consumption
IDD(DMA2DRAM) 0.0 0.1 0.3 0.5 0.7 0.2 0.3 1.0 1.6 2.0
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)
FMAC, FDCAN and USB SRAM static consumption
IDD(PRAM) 0.0 0.1 0.4 0.7 1.1 0.2 0.4 1.3 2.3 3.2
(PRAMPDS = 1 versus PRAMPDS = 0)
PKA SRAM static consumption
IDD(PKARAM) 0.1 0.2 0.6 1.2 2.1 0.3 0.5 1.9 3.6 6.3
(PKARAMPDS = 1 versus PKARAMPDS = 0)

Electrical characteristics
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).
4. SRAM3 total consumption is 8 × IDD(SRAM3_64KB).
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 Table 57. Current consumption during wakeup from Stop 2 mode on LDO
180/334

Electrical characteristics
Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Wakeup clock is MSI 24 MHz 0.81

Electrical charge consumed during wakeup from
QDD(wakeup from Stop 2) Wakeup clock is HSI 16 MHz 3.0 0.79 nAs
Stop 2 mode
Wakeup clock is MSI 1 MHz 1.98

Table 58. Current consumption in Stop 2 mode on SMPS

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 5.30 14.0 42.0 88.5 195 19.0 42.0 130.0 270.0 580.0
DS13086 Rev 6

Supply current in Stop 2 mode, 2.4 3.50 9.6 29.5 63.5 140 13.0 29.0 87.0 190.0 410.0
RTC disabled, (2)
3.0 3.90 10.0 31.5 68.0 150 14.0 30.0 93.0 200.0 440.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 3.90 10.0 30.5 65.5 145 14.0 30.0 89.0 190.0 420.0
3.6 4.55 11.0 31.0 65.0 145 16.0 32.0 89.0 190.0 420.0
IDD(Stop 2) µA
1.8 12.00 28.5 83.5 180.0 440 44.0 86.0 250.0 540.0 1400.0
2.4 7.85 19.5 58.5 125.0 280 29.0 59.0 180.0 380.0 830.0
Supply current in Stop 2 mode,
RTC disabled, 3.0 8.55 20.5 61.0 130.0 290 31.0 61.0 190.0 390.0 860.0
ALL SRAMs retained
3.3 8.20 19.5 57.5 125.0 275 30.0 58.0 170.0 370.0 810.0
3.6 8.55 19.5 56.0 120.0 265 30.0 57.0 170.0 360.0 780.0

STM32U585xx
 Table 58. Current consumption in Stop 2 mode on SMPS (continued)

STM32U585xx
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 5.60 14.0 42.0 89.0 195 20.0 42.0 130.0 270.0 580.0
Supply current in Stop 2 mode, 2.4 3.85 10.0 30.0 63.5 140 14.0 30.0 89.0 190.0 410.0
RTC(3) clocked by LSI 32 kHz,
3.0 4.35 10.5 32.0 68.5 150 16.0 31.0 94.0 200.0 440.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 4.40 10.5 31.0 66.0 145 16.0 31.0 91.0 200.0 420.0
3.6 5.15 11.5 31.5 66.0 145 18.0 33.0 91.0 190.0 420.0
1.8 5.40 14.0 42.0 89.0 195 20.0 42.0 130.0 270.0 580.0
Supply current in Stop 2 mode, 2.4 3.60 9.8 30.0 63.5 135 13.0 29.0 89.0 190.0 400.0
RTC(3) clocked by LSI 250 Hz,
3.0 4.00 10.5 31.5 68.0 150 15.0 31.0 93.0 200.0 440.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 4.05 10.5 31.0 65.5 145 15.0 31.0 91.0 190.0 420.0
DS13086 Rev 6

IDD(Stop 2 3.6 4.75 11.0 31.5 65.5 145 17.0 32.0 91.0 190.0 420.0
µA
with RTC) 1.8 5.50 14.0 42.0 89.0 195 20.0 42.0 130.0 270.0 580.0
Supply current in Stop 2 mode,
2.4 3.70 9.9 30.0 63.5 140 14.0 30.0 89.0 190.0 410.0
RTC(3) clocked by LSE
bypassed at 32768 Hz, 3.0 4.15 10.5 32.0 68.0 150 15.0 31.0 94.0 200.0 440.0
8-Kbyte SRAM2 + ICACHE
3.3 4.20 10.5 31.0 66.0 145 15.0 31.0 91.0 200.0 420.0
retained
3.6 4.90 11.0 31.5 65.5 145 17.0 32.0 91.0 190.0 420.0
1.8 5.50 14.0 41.5 88.0 190 - - - - -
Supply current in Stop 2 mode,
2.4 3.80 9.9 30.0 63.0 135 - - - - -
RTC(3) clocked by LSE quartz in

Electrical characteristics
medium low-drive mode, 3.0 4.15 10.5 31.5 67.5 145 - - - - -
8-Kbyte SRAM2 + ICACHE
3.3 4.20 10.5 31.0 65.0 140 - - - - -
retained
3.6 4.85 11.0 31.5 65.0 140 - - - - -
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
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 Table 59. SRAM static power consumption in Stop 2 when supplied by SMPS
182/334

Electrical characteristics
Typ Max(1)
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

SRAM1 64-Kbyte page x static consumption

IDD(SRAM1_64kB)(2) 0.4 0.9 2.6 5.5 12.7 1.5 2.7 7.7 17.0 39.0
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
SRAM2 8-Kbyte page 1 static consumption
IDD(SRAM2_8KB)(3) 0.1 0.2 0.6 1.2 2.9 0.3 0.6 2.0 3.7 10.0
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
SRAM2 56-Kbyte page 2 static consumption
IDD(SRAM2_56KB)(3) 0.5 1.1 3.4 7.5 16.7 1.7 3.4 11.0 23.0 50.0
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
SRAM3 64-Kbyte page x static consumption
IDD(SRAM3_64kB)(4) 0.4 0.8 2.4 5.3 12.2 1.4 2.5 7.3 16.0 37.0
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)
SRAM4 static consumption
IDD(SRAM4) 0.1 0.3 0.7 1.5 3.7 0.4 0.8 2.2 4.6 12.0 µA
(SRAM4PDS = 1 versus SRAM4PDS = 0)
DS13086 Rev 6

ICACHE SRAM static consumption

IDD(ICRAM) 0.1 0.2 0.5 1.0 2.6 0.3 0.5 2.0 3.1 7.9
(ICRAMPDS = 1 versus ICRAMPDS = 0)
DCACHE1 SRAM static consumption
IDD(DC1RAM) 0.0 0.1 0.3 0.4 1.3 0.2 0.3 1.0 1.4 4.0
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
DMA2D SRAM static consumption
IDD(DMA2DRAM) 0.0 0.0 0.1 0.2 0.4 0.1 0.1 0.2 0.6 1.1
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)
FMAC, FDCAN and USB SRAM static consumption
IDD(PRAM) 0.0 0.0 0.1 0.2 0.6 0.1 0.1 0.3 0.6 1.8
(PRAMPDS = 1 versus PRAMPDS = 0)
PKA SRAM static consumption
IDD(PKARAM) 0.0 0.1 0.2 0.3 1.0 0.1 0.2 0.6 0.9 2.9
(PKARAMPDS = 1 versus PKARAMPDS = 0)
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).

STM32U585xx
4. SRAM3 total consumption is 8 × IDD(SRAM3_64KB).
 STM32U585xx
Table 60. Current consumption during wakeup from Stop 2 mode on SMPS
Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Wakeup clock is MSI 24 MHz 0.57

Electrical charge consumed during wakeup from
QDD(wakeup from Stop 2) Wakeup clock is HSI 16 MHz 3.0 0.18 nAs
Stop 2 mode
Wakeup clock is MSI 1 MHz 1.19

Table 61. Current consumption in Stop 3 mode on LDO

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 5.15 14.5 49.0 110 240 19.0 44.0 150.0 330.0 710.0
DS13086 Rev 6

Supply current in Stop 3 mode, 2.4 5.15 15.0 49.5 110 240 19.0 45.0 150.0 330.0 710.0
RTC disabled,
3.0 5.60 15.0 50.5 110 245 20.0 45.0 150.0 330.0 720.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 5.30 15.5 51.5 115 250 19.0 46.0 160.0 340.0 740.0
3.6 6.80 17.0 54.0 115 255 24.0 50.0 160.0 340.0 750.0
IDD(Stop 3) µA
1.8 12.00 35.5 125.0 290 665 44.0 110.0 380.0 870.0 2000.0
2.4 12.00 36.0 125.0 295 670 44.0 110.0 380.0 890.0 2000.0
Supply current in Stop 3 mode,
RTC disabled, (2)
3.0 13.00 36.5 130.0 300 675 47.0 110.0 390.0 900.0 2100.0
all SRAMs retained
3.3 14.50 37.0 130.0 300 685 52.0 120.0 390.0 900.0 2100.0
3.6 14.50 39.0 135.0 305 695 52.0 120.0 410.0 910.0 2100.0

Electrical characteristics
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 Table 61. Current consumption in Stop 3 mode on LDO (continued)
184/334

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 5.45 15.0 49.5 110 240 20.0 45.0 150.0 330.0 710.0
Supply current in Stop 3 mode, 2.4 5.55 15.0 50.0 110 240 20.0 45.0 150.0 330.0 710.0
RTC(3) clocked by LSI 32 kHz,
3.0 6.05 15.5 51.0 110 245 22.0 46.0 160.0 330.0 720.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 5.80 16.0 52.0 115 250 21.0 48.0 160.0 340.0 740.0
3.6 7.35 18.0 54.5 120 255 26.0 53.0 160.0 360.0 750.0
1.8 5.25 15.0 49.5 110 240 19.0 45.0 150.0 330.0 710.0
Supply current in Stop 3 mode, 2.4 5.30 15.0 49.5 110 240 19.0 45.0 150.0 330.0 710.0
RTC(3) clocked by LSI 250 Hz,
3.0 5.75 15.0 50.5 110 245 21.0 45.0 150.0 330.0 720.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 5.40 16.0 52.0 115 250 19.0 48.0 160.0 340.0 740.0
DS13086 Rev 6

IDD(Stop 3 3.6 6.95 17.5 54.5 115 255 25.0 51.0 160.0 340.0 750.0
µA
with RTC) 1.8 5.35 15.0 49.5 110 240 20.0 45.0 150.0 330.0 710.0
Supply current in Stop 3 mode,
2.4 5.40 15.0 49.5 110 240 20.0 45.0 150.0 330.0 710.0
RTC(3) clocked by LSE
bypassed at 32768 Hz, 3.0 5.90 15.5 50.5 110 245 21.0 46.0 150.0 330.0 720.0
8-Kbyte SRAM2 + ICACHE
3.3 5.55 16.0 52.0 115 250 20.0 48.0 160.0 340.0 740.0
retained
3.6 7.20 17.5 54.5 115 255 25.0 51.0 160.0 340.0 750.0
1.8 5.35 15.0 48.5 105 230 - - - - -
Supply current in Stop 3 mode,
2.4 5.45 15.0 49.0 110 235 - - - - -
RTC(3) clocked by LSE quartz in
medium low-drive mode, 3.0 5.95 15.5 50.5 110 240 - - - - -
8-Kbyte SRAM2 + ICACHE
3.3 6.55 16.0 51.5 110 245 - - - - -
retained
3.6 7.20 17.5 54.0 115 250 - - - - -

STM32U585xx
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
 STM32U585xx
Table 62. SRAM static power consumption in Stop 3 when supplied by LDO
Typ Max(1)
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

SRAM1 64-Kbyte page x static consumption

IDD(SRAM1_64kB)(2) 0.7 1.8 6.4 15.3 35.6 2.7 5.3 20.0 46.0 110.0
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
SRAM2 8-Kbyte page 1 static consumption
IDD(SRAM2_8KB)(3) 0.2 0.7 2.4 5.8 12.8 1.0 2.1 7.1 18.0 39.0
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
SRAM2 56-Kbyte page 2 static consumption
IDD(SRAM2_56KB)(3) 0.9 2.2 7.8 18.5 41.7 3.2 6.5 24.0 56.0 130.0
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
SRAM3 64-Kbyte page x static consumption
IDD(SRAM3_64kB)(4) 0.7 1.7 6.1 14.8 34.2 2.6 5.2 19.0 45.0 110.0
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)
SRAM4 static consumption
IDD(SRAM4) 0.2 0.5 1.7 4.0 8.9 0.8 1.5 5.1 12.0 27.0 µA
(SRAM4PDS = 1 versus SRAM4PDS = 0)
DS13086 Rev 6

ICACHE SRAM static consumption

IDD(ICRAM) 0.0 0.3 1.3 2.9 6.3 0.0 1.1 3.9 8.9 19.0
(ICRAMPDS = 1 versus ICRAMPDS = 0)
DCACHE1 SRAM static consumption
IDD(DC1RAM) 0.0 0.0 0.0 0.3 1.2 0.0 0.0 0.0 1.0 3.7
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
DMA2D SRAM static consumption
IDD(DMA2DRAM) 0.0 0.1 0.3 0.6 1.1 0.2 0.2 1.0 1.9 3.4
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)
FMAC, FDCAN and USB SRAM static consumption
IDD(PRAM) 0.1 0.1 0.4 0.8 1.5 0.2 0.3 1.3 2.3 4.6
(PRAMPDS = 1 versus PRAMPDS = 0)
PKA SRAM static consumption
IDD(PKARAM) 0.1 0.2 0.6 1.3 2.8 0.3 0.5 1.9 4.0 8.4
(PKARAMPDS = 1 versus PKARAMPDS = 0)

Electrical characteristics
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).
4. SRAM3 total consumption is 8 × IDD(SRAM3_64KB).
185/334
186/334

Electrical characteristics
Table 63. Current consumption during wakeup from Stop 3 mode on LDO
Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Wakeup clock is MSI 24 MHz 19.2

Electrical charge consumed during wakeup from
QDD(wakeup from Stop 3) Wakeup clock is HSI 16 MHz 3.0 18.2 nAs
Stop 3 mode
Wakeup clock is MSI 1 MHz 61.8

Table 64. Current consumption in Stop 3 mode on SMPS

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 2.10 6.55 22.5 50.5 115.0 7.4 20.0 66.0 150.0 340.0
DS13086 Rev 6

Supply current in Stop 3 mode, 2.4 1.85 5.95 20.5 46.5 110.0 6.5 18.0 60.0 140.0 320.0
RTC disabled,
3.0 1.70 5.30 18.5 42.0 98.5 5.9 16.0 54.0 130.0 280.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 1.80 5.55 18.5 41.5 97.0 6.1 16.0 53.0 120.0 280.0
3.6 2.65 6.55 19.5 42.5 98.0 8.6 19.0 55.0 120.0 280.0
IDD(Stop 3) µA
1.8 5.20 15.50 55.0 130.0 355.0 19.0 47.0 170.0 390.0 1100.0
2.4 4.55 14.00 50.0 115.0 275.0 17.0 42.0 150.0 350.0 820.0
Supply current in Stop 3 mode,
RTC disabled, (2)
3.0 3.90 12.00 42.5 100.0 235.0 14.0 36.0 130.0 300.0 690.0
all SRAMs retained
3.3 3.65 11.50 40.5 95.0 225.0 13.0 34.0 120.0 280.0 660.0
3.6 4.50 12.00 40.5 92.5 215.0 16.0 35.0 120.0 270.0 630.0

STM32U585xx
 Table 64. Current consumption in Stop 3 mode on SMPS (continued)

STM32U585xx
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 2.40 6.85 22.5 51.0 120.0 8.5 21.0 66.0 150.0 350.0
Supply current in Stop 3 mode, 2.4 2.25 6.30 21.0 47.0 110.0 8.0 19.0 62.0 140.0 320.0
RTC(3) clocked by LSI 32 kHz,
3.0 2.15 5.80 19.0 42.5 99.0 7.5 17.0 55.0 130.0 290.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 2.30 6.05 19.0 42.0 97.5 7.9 18.0 55.0 120.0 280.0
3.6 3.20 7.10 20.0 43.0 98.5 11.0 20.0 56.0 130.0 280.0
1.8 2.20 6.70 22.5 50.5 115.0 7.8 20.0 66.0 150.0 340.0
Supply current in Stop 3 mode, 2.4 2.00 6.10 20.5 47.0 110.0 7.1 18.0 60.0 140.0 320.0
RTC(3) clocked by LSI 250 Hz,
3.0 1.85 5.45 18.5 42.0 98.5 6.5 16.0 54.0 130.0 280.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 1.90 5.70 18.5 41.5 97.0 6.4 17.0 53.0 120.0 280.0
DS13086 Rev 6

IDD(Stop 3 3.6 2.80 6.70 20.0 42.5 98.0 9.2 19.0 56.0 120.0 280.0
µA
with RTC) 1.8 2.30 6.80 22.5 51.0 120.0 8.2 21.0 66.0 150.0 350.0
Supply current in Stop 3 mode,
2.4 2.10 6.20 21.0 47.0 110.0 7.4 19.0 62.0 140.0 320.0
RTC(3) clocked by LSE bypassed
at 32768 Hz, 3.0 2.00 5.60 18.5 42.0 99.0 7.0 17.0 54.0 130.0 290.0
8-Kbyte SRAM2 + ICACHE
3.3 2.05 5.85 18.5 42.0 97.5 7.0 17.0 53.0 120.0 280.0
retained
3.6 3.00 6.90 20.0 43.0 98.5 9.9 20.0 56.0 130.0 280.0
1.8 2.35 6.80 22.5 50.0 115.0 - - - - -
Supply current in Stop 3 mode,
2.4 2.15 6.25 21.0 46.5 105.0 - - - - -
RTC(3) clocked by LSE quartz in

Electrical characteristics
medium low-drive mode, 3.0 2.05 5.70 18.5 42.0 96.0 - - - - -
8-Kbyte SRAM2 + ICACHE
3.3 2.25 5.95 18.5 41.5 95.0 - - - - -
retained
3.6 3.05 6.95 20.0 42.5 96.0 - - - - -
1. Evaluated by characterization and not tested in production, unless otherwise specificed.
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.
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 Table 65. SRAM static power consumption in Stop 3 when supplied by SMPS
188/334

Electrical characteristics
Typ Max(1)
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

SRAM1 64-Kbyte page x static consumption

IDD(SRAM1_64kB)(2) 0.2 0.6 2.2 5.4 12.6 0.7 2.0 8.0 17.0 38.0
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
SRAM2 8-Kbyte page 1 static consumption
IDD(SRAM2_8KB)(3) 0.1 0.2 0.8 2.0 4.6 0.2 1.0 2.5 5.9 14.0
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
SRAM2 56-Kbyte page 2 static consumption
IDD(SRAM2_56KB)(3) 0.2 0.7 2.7 6.4 14.8 1.0 3.0 8.0 20.0 45.0
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
SRAM3 64-Kbyte page x static consumption
IDD(SRAM3_64kB)(4) 0.2 0.6 2.1 5.0 12.0 1.0 2.0 6.3 16.0 36.0
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)
SRAM4 static consumption
IDD(SRAM4) 0.0 0.1 0.6 1.4 3.0 0.5 1.0 2.0 4.1 8.9 µA
(SRAM4PDS = 1 versus SRAM4PDS = 0)
DS13086 Rev 6

ICACHE SRAM static consumption

IDD(ICRAM) 0.0 0.1 0.4 1.0 2.0 0.1 1.0 2.0 3.0 6.1
(ICRAMPDS = 1 versus ICRAMPDS = 0)
DCACHE1 SRAM static consumption
IDD(DC1RAM) 0.0 0.1 0.2 0.5 0.9 1.2 1.0 1.0 1.5 2.6
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
DMA2D SRAM static consumption
IDD(DMA2DRAM) 0.0 0.0 0.0 0.1 0.1 0.4 0.1 0.1 0.4 0.4
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)
FMAC, FDCAN and USB SRAM static consumption
IDD(PRAM) 0.0 0.0 0.1 0.2 0.3 0.0 0.1 1.0 0.7 0.8
(PRAMPDS = 1 versus PRAMPDS = 0)
PKA SRAM static consumption
IDD(PKARAM) 0.0 0.1 0.2 0.4 0.7 0.0 1.0 1.0 1.3 2.1
(PKARAMPDS = 1 versus PKARAMPDS = 0)
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
3. ???SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).

STM32U585xx
4. SRAM3 total consumption is 8 × IDD(SRAM3_64KB).
 STM32U585xx
Table 66. Current consumption during wakeup from Stop 3 mode on SMPS
Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Wakeup clock is MSI 24 MHz 7.44

Electrical charge consumed during wakeup from
QDD(wakeup from Stop 3) Wakeup clock is HSI 16 MHz 3.0 7.25 nAs
Stop 3 mode
Wakeup clock is MSI 1 MHz 26.0
DS13086 Rev 6

Electrical characteristics
189/334
 Table 67. Current consumption in Standby mode
190/334

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 0.21 0.71 3.30 9.10 28.40 0.55 1.70 7.40 20.00 58.00
2.4 0.21 0.74 3.47 9.54 29.70 0.58 1.80 7.90 22.00 61.00
No IWDG
3.0 0.36 1.08 4.41 11.50 34.20 1.10 2.70 11.00 27.00 73.00
ULPMEN = 1
3.3 0.64 1.69 5.68 13.70 38.40 2.00 4.20 14.00 32.00 83.00
3.6 1.51 3.04 8.07 17.40 44.20 4.80 7.70 20.00 41.00 98.00
1.8 0.28 0.76 3.28 8.95 27.70 0.63 1.70 7.40 20.00 57.00
2.4 0.29 0.83 3.52 9.46 29.10 0.67 1.90 7.90 22.00 61.00
No IWDG
3.0 0.43 1.16 4.43 11.40 33.40 1.10 2.80 11.00 27.00 72.00
ULPMEN = 0
3.3 0.75 1.75 5.68 13.60 37.40 2.20 4.30 14.00 32.00 82.00
DS13086 Rev 6

Supply current in
Standby mode (backup 3.6 1.58 3.10 8.07 17.20 43.30 4.90 7.70 20.00 41.00 97.00
IDD(Standby) µA
registers retained), 1.8 0.52 1.03 3.55 9.04 26.57 0.79 1.90 7.20 19.00 57.00
RTC disabled
with IWDG 2.4 0.64 1.18 3.81 9.51 27.47 0.93 2.10 7.80 20.00 61.00
clocked by
LSI 32 kHz 3.0 0.87 1.62 4.81 11.48 31.63 1.50 3.10 11.00 25.00 72.00
ULPMEN = 0 3.3 1.23 2.26 6.12 13.68 35.58 2.60 4.60 14.00 30.00 83.00
3.6 2.13 3.67 8.55 17.34 41.46 5.30 8.10 20.00 39.00 97.00
1.8 0.38 0.88 3.44 9.15 28.00 0.77 1.90 7.60 21.00 57.00
with IWDG 2.4 0.40 0.94 3.63 9.58 29.20 0.79 2.00 8.00 22.00 61.00
clocked by
3.0 0.55 1.28 4.55 11.50 33.50 1.30 2.90 11.00 27.00 72.00
LSI 250 Hz
ULPMEN = 0 3.3 0.87 1.90 5.83 13.70 37.50 2.30 4.40 14.00 32.00 82.00
3.6 1.71 3.26 8.22 17.30 43.30 5.10 7.90 20.00 41.00 97.00

STM32U585xx
 Table 67. Current consumption in Standby mode (continued)

STM32U585xx
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 0.56 1.05 3.60 9.29 28.10 0.81 1.90 7.50 20.00 57.00
RTC(2) clocked 2.4 0.64 1.18 3.88 9.82 29.40 0.93 2.20 8.20 22.00 61.00
by LSI 32 kHz,
3.0 0.88 1.61 4.88 11.80 33.80 1.50 3.20 11.00 27.00 72.00
no IWDG(3)
ULPMEN = 0 3.3 1.25 2.26 6.19 14.10 37.80 2.60 4.70 14.00 33.00 83.00
3.6 2.13 3.67 8.63 17.70 43.70 5.30 8.20 20.00 42.00 97.00
1.8 0.39 0.88 3.44 9.14 28.00 0.77 1.90 7.60 21.00 57.00
RTC(2) clocked 2.4 0.40 0.94 3.63 9.58 29.20 0.79 2.00 8.00 22.00 61.00
by LSI 250 Hz,
3.0 0.56 1.29 4.56 11.50 33.40 1.30 2.90 11.00 27.00 72.00
no IWDG
ULPMEN = 0 3.3 0.89 1.90 5.83 13.70 37.50 2.30 4.40 14.00 32.00 82.00
DS13086 Rev 6

Supply current in
IDD(Standby with Standby mode (backup 3.6 1.73 3.27 8.23 17.30 43.30 5.10 7.90 20.00 41.00 97.00
registers retained), µA
RTC) 1.8 0.47 0.96 3.51 9.22 28.10 0.95 2.10 7.70 21.00 57.00
RTC enabled RTC(2) clocked
2.4 0.50 1.04 3.75 9.72 29.40 1.10 2.30 8.30 22.00 61.00
by LSE
bypassed at 3.0 0.69 1.42 4.71 11.70 33.80 1.60 3.30 11.00 27.00 73.00
32768 Hz
3.3 1.04 2.06 6.00 13.90 37.80 2.70 4.80 15.00 33.00 83.00
ULPMEN = 0
3.6 1.91 3.46 8.43 17.60 43.70 5.50 8.30 21.00 42.00 98.00
1.8 0.47 0.97 3.50 9.14 27.20 - - - - -
RTC(2) clocked
2.4 0.50 1.05 3.72 9.60 28.20 - - - - -
by LSE quartz

Electrical characteristics
in medium 3.0 0.66 1.40 4.66 11.50 32.50 - - - - -
low-drive mode
3.3 0.98 2.01 5.93 13.70 36.50 - - - - -
ULPMEN = 0
3.6 1.82 3.37 8.32 17.40 42.30 - - - - -
191/334
 Table 67. Current consumption in Standby mode (continued)
192/334

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 0.44 0.97 3.55 9.45 29.20 - - - - -

RTC(2) clocked
Supply current in 2.4 0.47 1.03 3.80 10.00 30.00 - - - - -
by LSE quartz
IDD(Standby with Standby mode (backup
in medium 3.0 0.62 1.37 4.75 12.35 35.20 - - - - -
RTC) registers retained),
low-drive mode
RTC enabled 3.3 0.98 1.96 6.00 14.45 38.90 - - - - -
ULPMEN = 1
3.6 1.77 3.40 8.50 17.80 45.40 - - - - -
1.8 0.13 0.22 0.53 1.15 2.50 0.47 0.66 1.60 3.50 7.50
Supply current to be 2.4 0.12 0.19 0.47 1.04 2.30 0.45 0.56 1.50 3.20 6.90
added in Standby mode
IDD(BKPSRAM) - 3.0 0.13 0.19 0.47 1.00 2.30 0.47 0.58 1.50 3.00 7.00
when backup SRAM is
retained 3.3 0.09 0.20 0.48 1.00 2.40 0.31 0.60 1.50 3.00 7.20
DS13086 Rev 6

3.6 0.10 0.20 0.48 1.00 2.20 0.37 0.60 1.50 3.00 6.70
µA
1.8 1.62 4.09 11.92 25.75 55.60 5.90 13.00 36.00 78.00 170.00
Supply current to be 2.4 1.62 4.05 11.88 25.74 55.60 5.90 13.00 36.00 78.00 170.00
added in Standby mode
IDD(SRAM2) 3.0 1.64 4.02 11.87 25.80 55.70 6.00 13.00 36.00 78.00 170.00
when full SRAM2 and
BKPSRAM are retained 3.3 1.65 4.02 11.82 25.70 55.70 6.00 13.00 36.00 78.00 170.00
3.6 1.68 3.99 11.73 25.50 55.20 6.10 12.00 36.00 77.00 170.00
LDO
1.8 0.58 1.41 4.02 8.55 18.20 2.10 4.30 13.00 26.00 55.00
Supply current to be
2.4 0.63 1.37 3.95 8.44 17.90 2.30 4.10 12.00 26.00 54.00
added in Standby mode
IDD(SRAM2_8K) when SRAM2 8-Kbyte 3.0 0.63 1.36 3.93 8.40 17.90 2.30 4.10 12.00 26.00 54.00
page 1 and BKPSRAM
3.3 0.60 1.35 3.90 8.30 17.80 2.20 4.10 12.00 25.00 54.00
are retained
3.6 0.69 1.35 3.73 8.10 17.30 2.50 4.10 12.00 25.00 52.00

STM32U585xx
 Table 67. Current consumption in Standby mode (continued)

STM32U585xx
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 0.97 2.23 6.55 14.25 31.40 3.50 6.70 20.00 43.00 95.00
Supply current to be 2.4 0.63 1.48 4.40 9.44 19.50 2.30 4.50 14.00 29.00 59.00
added in Standby mode
IDD(SRAM2) 3.0 0.67 1.51 4.50 9.90 21.60 2.50 4.60 14.00 30.00 65.00
when full SRAM2 and
BKPSRAM are retained 3.3 0.56 1.35 4.05 8.90 19.60 2.10 4.10 13.00 27.00 59.00
3.6 0.55 1.19 3.53 7.80 17.40 2.00 3.60 11.00 24.00 53.00
SMPS µA
1.8 0.34 0.78 2.21 4.75 10.40 1.30 2.40 6.70 15.00 32.00
Supply current to be
2.4 0.24 0.52 1.45 3.04 6.80 0.85 1.60 4.40 9.20 21.00
added in Standby mode
IDD(SRAM2_8K) when SRAM2 8-Kbyte 3.0 0.25 0.50 1.45 3.10 6.80 0.89 1.50 4.40 9.30 21.00
page 1 and BKPSRAM
3.3 0.17 0.42 1.23 2.70 6.00 0.63 1.30 3.70 8.10 18.00
are retained
DS13086 Rev 6

3.6 0.18 0.33 0.86 2.10 4.80 0.65 0.99 2.60 6.30 15.00
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration but LPCAL = 1 in RTC_CALR.
3. Current consumption with IWDG enabled is similar.

Table 68. Current consumption during wakeup from Standby mode

Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Electrical characteristics
Electrical charge consumed during wakeup from Wakeup clock is MSI 4 MHz 404
QDD(wakeup from Standby) 3.0 nAs
Standby mode Wakeup clock is MSI 1 MHz 602
193/334
 Table 69. Current consumption in Shutdown mode
194/334

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 0.16 0.62 2.65 7.05 18.50 0.49 1.60 6.70 18.00 47.00
Supply current in 2.4 0.17 0.68 2.85 7.65 20.00 0.53 1.70 7.20 20.00 50.00
Shutdown mode (backup (2)
IDD(Shutdown) registers retained), - 3.0 0.31 1.05 3.85 9.75 25.00 0.95 2.70 9.70 25.00 63.00
RTC disabled 3.3 0.64 1.65 5.15 12.00 29.00 2.00 4.20 13.00 30.00 73.00
3.6 1.55 3.05 7.60 15.50 35.00 4.90 7.70 19.00 39.00 88.00
1.8 0.33 0.80 2.85 7.25 19.00 0.67 1.80 6.90 18.00 47.00
2.4 0.37 0.88 3.10 7.85 20.50 0.75 2.00 7.40 20.00 51.00
RTC(3) clocked by
LSE bypassed at 3.0 0.57 1.30 4.15 10.00 25.50 1.30 2.90 10.00 25.00 64.00 µA
32768 Hz
3.3 0.94 2.00 5.50 12.50 29.50 2.40 4.60 14.00 31.00 74.00
DS13086 Rev 6

Supply current in
IDD(Shutdown Shutdown mode (backup 3.6 1.90 3.45 8.00 16.00 35.50 5.20 8.10 20.00 40.00 89.00
with RTC) registers retained), 1.8 0.39 0.87 3.00 7.60 20.00 - - - - -
RTC enabled
RTC(3) clocked by 2.4 0.43 0.93 3.20 8.05 21.00 - - - - -
LSE quartz in
3.0 0.57 1.25 4.10 9.95 25.50 - - - - -
medium low-drive
mode 3.3 0.89 1.90 5.40 12.00 29.50 - - - - -
3.6 1.75 3.25 7.80 16.00 35.50 - - - - -
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production.
3. RTC with default configuration but LPCAL = 1 in RTC_CALR.

Table 70. Current consumption during wakeup from Shutdown mode

Conditions Typ

STM32U585xx
Symbol Parameter Unit
- VDD (V) 25°C

QDD(wakeup from Electrical charge consumed during wakeup from

Wakeup clock is MSI 4 MHz 3.0 3.75 μAs
Shutdown) Shutdown mode
 Table 71. Current consumption in VBAT mode

STM32U585xx
Conditions Typ Max(1)
Symbol Parameter Unit
- VBAT (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 0.12 0.27 1.00 2.60 7.70 0.36 0.67 2.50 6.50 20.00
Supply current in VBAT 2.4 0.13 0.29 1.05 2.70 8.10 0.39 0.72 2.70 6.80 21.00
mode (backup registers
IDD(VBAT) retained), - 3.0 0.16 0.37 1.30 3.20 9.10 0.50 0.93 3.30 8.00 23.00
RTC disabled 3.3 0.25 0.56 1.80 4.25 11.50 0.78 1.40 4.50 11.00 29.00
3.6 0.46 0.89 2.35 5.00 13.00 1.50 2.30 5.90 13.00 33.00
1.8 0.40 0.56 1.30 2.80 7.65 0.68 0.99 2.90 6.80 20.00
2.4 0.48 0.65 1.45 3.05 8.30 0.78 1.20 3.10 7.20 21.00
RTC(2) clocked
by LSE bypassed 3.0 0.62 0.85 1.80 3.75 9.65 1.10 1.50 3.80 8.70 24.00
at 32768 Hz
3.3 0.78 1.10 2.35 4.90 12.50 1.40 2.00 5.20 12.00 30.00
DS13086 Rev 6

3.6 1.10 1.55 3.00 5.80 13.50 2.20 3.00 6.60 14.00 34.00
µA
1.8 0.31 0.47 1.20 2.70 7.55 0.89 1.30 3.10 6.90 20.00
Supply current in VBAT RTC(2) clocked
2.4 0.36 0.53 1.30 2.95 8.15 1.10 1.40 3.40 7.50 21.00
by LSE bypassed
IDD(VBAT with mode (backup registers
at 32768 Hz, 3.0 0.46 0.69 1.65 3.55 9.50 1.40 1.90 4.20 9.00 24.00
RTC) retained),
LPCAL = 1 in
RTC enabled 3.3 0.60 0.93 2.20 4.70 12.00 1.80 2.40 5.60 12.00 31.00
RTC_CALR
3.6 0.87 1.35 2.80 5.60 13.50 2.60 3.50 7.10 15.00 34.00
1.8 0.45 0.61 1.35 2.95 8.25 - - - - -
2.4 0.51 0.67 1.45 3.15 8.60 - - - - -
RTC(2) clocked

Electrical characteristics
by LSE quartz in 3.0 0.60 0.81 1.75 3.65 9.60 - - - - -
medium low-drive
3.3 0.71 1.00 2.25 4.80 12.50 - - - - -
3.6 0.96 1.40 2.85 5.60 13.50 - - - - -
195/334
 Table 71. Current consumption in VBAT mode (continued)
196/334

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
- VBAT (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

1.8 0.37 0.52 1.25 2.90 8.15 - - - - -

RTC(2) clocked
Supply current in VBAT by LSE quartz in 2.4 0.39 0.56 1.35 3.00 8.45 - - - - -
IDD(VBAT with mode (backup registers medium low-drive
retained), 3.0 0.44 0.66 1.60 3.50 9.45 - - - - -
RTC) mode,
RTC enabled LPCAL = 1 in 3.3 0.54 0.85 2.10 4.60 12.00 - - - - -
RTC_CALR
3.6 0.76 1.20 2.65 5.40 13.50 - - - - -
µA
1.8 0.12 0.19 0.41 0.85 1.75 0.26 0.44 1.10 2.50 5.20
2.4 0.12 0.19 0.45 0.95 1.90 0.26 0.45 1.30 2.80 5.60
Supply current to be added
IDD(BKPSRAM) in VBAT mode when backup - 3.0 0.12 0.20 0.50 1.05 2.40 0.28 0.49 1.40 3.10 7.10
SRAM is retained
3.3 0.13 0.22 0.50 1.10 2.50 0.31 0.54 1.40 3.20 7.40
DS13086 Rev 6

3.6 0.14 0.22 0.50 1.20 2.50 0.36 0.55 1.40 3.50 7.40
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration except otherwise specified

STM32U585xx
STM32U585xx Electrical characteristics

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up or pull-down generate current consumption when the
pin is externally held to the opposite level. The value of this current consumption can be
simply computed by using the pull-up/pull-down resistors values given in Section 5.3.14: I/O
port characteristics.
For the output pins, any internal or external pull-up or pull-down or external load must also
be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of the ADC input pins, that must be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the on-chip peripheral current consumption (see Table 72 for peripheral
current consumption in Run mode), the I/Os used by an application also contribute to the
current consumption. When an I/O pin switches, it uses the current from the I/O supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal
and external) connected to the pin:

I SW = V DDIOx × f SW × C

where:
• ISW is the current sunk by a switching I/O to charge/discharge the capacitive load.
• VDDIOx is the I/O supply voltage.
• fSW is the I/O switching frequency.
• C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS.
• CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

DS13086 Rev 6 197/334

299
Electrical characteristics STM32U585xx

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the table below. The MCU is
placed under the following conditions:
• All I/O pins are in analog mode.
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• The ambient operating temperature and supply voltage conditions are summarized
in Table 33.
• The power consumption of the digital part of the on-chip peripherals is given in the table
below. The power consumption of the analog part of the peripherals (where applicable)
is indicated in each related section of the datasheet.

Table 72. Typical dynamic current consumption of peripherals

LDO SMPS
Range1

Range2

Range3

Range4

Range1

Range2

Range3

Range4
Bus Peripheral Unit

Stop 1
Stop 2

Stop 1
Stop 2
AHB1 1.81 1.64 1.48 1.34 - 0.87 0.74 0.61 0.48 -
BKPRAM 0.90 0.80 0.74 0.67 - 0.44 0.37 0.31 0.24 -
CORDIC 0.56 0.51 0.45 0.41 - 0.27 0.23 0.19 0.15 -
CRC 0.34 0.30 0.27 0.25 - 0.17 0.14 0.12 0.09 -
DCACHE1 0.74 0.65 0.60 0.56 - 0.36 0.31 0.25 0.19 -
DMA2D 1.95 1.76 1.60 1.46 - 0.94 0.80 0.67 0.52 -
FLASH 2.21 2.01 1.82 1.65 - 1.07 0.91 0.76 0.59 -
FMAC 2.24 2.03 1.84 1.68 - 1.08 0.92 0.77 0.59 -
AHB1

GPDMA1 3.71 3.38 3.05 2.75 - 1.80 1.52 1.27 0.98 -

GTZC1 0.39 0.34 0.31 0.30 - 0.18 0.16 0.13 0.10 - µA/
ICACHE 0.76 0.68 0.63 0.57 - 0.37 0.32 0.26 0.20 - MHz

MDF1 7.65 6.95 6.27 5.67 - 3.69 3.12 2.61 2.01 -

MDF1 indep(1) 0.84 0.76 0.68 0.63 - 0.4 0.34 0.29 0.22 -
RAMCFG 1.26 1.14 1.03 0.96 - 0.61 0.52 0.43 0.33 -
SRAM1 0.82 0.73 0.67 0.62 - 0.40 0.34 0.28 0.22 -
TSC 1.11 1.00 0.91 0.83 - 0.54 0.46 0.38 0.29 -
AHB2-1 2.08 1.88 1.71 1.54 - 1.00 0.85 0.71 0.55 -
AHB2-1

ADC1 2.01 1.84 1.65 1.52 - 0.97 0.82 0.69 0.53 -

ADC1 indep(1) 1.43 1.30 1.17 1.06 - 0.69 0.58 0.48 0.37 -
AES 2.36 2.17 1.94 1.75 - 1.14 0.97 0.81 0.62 -

198/334 DS13086 Rev 6

STM32U585xx Electrical characteristics

Table 72. Typical dynamic current consumption of peripherals (continued)

LDO SMPS

Range1

Range2

Range3

Range4

Range1

Range2

Range3

Range4
Bus Peripheral Unit

Stop 1
Stop 2

Stop 1
Stop 2
DCMI 4.68 4.28 3.87 3.50 - 2.26 1.92 1.61 1.24 -
GPIOA 0.08 0.07 0.07 0.05 - 0.04 0.03 0.03 0.02 -
GPIOB 0.06 0.05 0.04 0.04 - 0.03 0.02 0.02 0.01 -
GPIOC 0.11 0.11 0.08 0.08 - 0.05 0.05 0.04 0.03 -
GPIOD 0.07 0.07 0.06 0.06 - 0.04 0.03 0.03 0.02 -
GPIOE 0.04 0.05 0.03 0.03 - 0.02 0.02 0.01 0.01 -
GPIOF 0.07 0.08 0.06 0.05 - 0.04 0.03 0.03 0.02 -
GPIOG 0.22 0.21 0.17 0.16 - 0.11 0.09 0.07 0.05 -
GPIOH 0.22 0.21 0.17 0.17 - 0.11 0.09 0.07 0.06 -
GPIOI 0.12 0.13 0.10 0.09 - 0.06 0.05 0.04 0.03 -
HASH1 1.18 1.10 0.98 0.88 - 0.57 0.49 0.41 0.31 -
AHB2-1

OTFDEC1 1.86 1.72 1.52 1.38 - 0.90 0.76 0.64 0.49 -

OTFDEC2 2.05 1.89 1.68 1.52 - 0.99 0.84 0.70 0.54 -
PKA 7.93 7.24 6.54 5.91 - 3.83 3.24 2.72 2.09 -
RNG 0.82 0.76 0.67 0.60 - 0.39 0.33 0.28 0.21 - µA/
RNG indep (1)
0.10 0.06 0.06 0.06 - 0.06 0.02 0.02 0.02 - MHz

SAES 2.80 2.57 2.30 2.08 - 1.35 1.14 0.96 0.74 -

SDMMC1 12.26 11.18 10.11 9.15 - 5.92 5.01 4.20 3.24 -
SDMMC1 indep(1) 1.47 1.34 1.22 1.09 - 0.71 0.60 0.50 0.40 -
SDMMC2 12.48 11.39 10.29 9.31 - 6.02 5.10 4.28 3.30 -
(1)
SDMMC2 indep 1.59 1.44 1.31 1.18 - 0.76 0.65 0.54 0.44 -
SRAM2 1.18 1.10 0.97 0.88 - 0.57 0.48 0.40 0.32 -
SRAM3 1.31 1.22 1.07 0.97 - 0.63 0.54 0.45 0.35 -
USB_OTG_FS 10.47 9.58 8.67 7.83 - 5.05 4.30 3.61 2.77 -
AHB2-2 0.79 0.74 0.64 0.58 - 0.38 0.32 0.26 0.20 -
FMC 5.34 4.87 4.42 3.99 - 2.58 2.19 1.84 1.42 -
AHB2-2

OCTOSPI1 1.58 1.45 1.29 1.18 - 0.76 0.64 0.54 0.42 -

OCTOSPI1 indep(1) 1.11 1.01 0.91 0.83 - 0.54 0.45 0.38 0.29 -
OCTOSPI2 0.79 0.72 0.65 0.58 - 0.39 0.32 0.28 0.21 -
OCTOSPI2 indep(1) 0.91 0.83 0.75 0.68 - 0.44 0.37 0.31 0.24 -

DS13086 Rev 6 199/334

299
Electrical characteristics STM32U585xx

Table 72. Typical dynamic current consumption of peripherals (continued)

LDO SMPS

Range1

Range2

Range3

Range4

Range1

Range2

Range3

Range4
Bus Peripheral Unit

Stop 1
Stop 2

Stop 1
Stop 2
ADC4 0.96 0.87 0.79 0.72 0.98 0.46 0.39 0.33 0.26 0.35
(1)
ADC4 indep 2.52 2.28 2.06 1.85 1.86 1.21 1.03 0.86 0.66 0.66
ADF1 0.97 0.87 0.79 0.72 0.97 0.47 0.39 0.33 0.25 0.34
ADF1 indep(1) 0.35 0.31 0.28 0.26 0.21 0.17 0.14 0.12 0.09 0.07
AHB3 0.34 0.34 0.28 0.24 - 0.17 0.14 0.11 0.09 -
DAC1 1.88 1.70 1.55 1.39 1.66 0.91 0.76 0.64 0.50 0.59
AHB3

DAC1 indep(1) 1.30 1.17 1.06 0.96 0.92 0.63 0.52 0.44 0.34 0.33
GTZC2 0.34 0.32 0.30 0.29 - 0.16 0.14 0.12 0.11 -
LPDMA1 0.43 0.39 0.36 0.32 0.58 0.21 0.17 0.14 0.11 0.20
LPGPIO1 0.10 0.09 0.09 0.08 0.26 0.05 0.04 0.03 0.03 0.09
PWR 0.13 0.12 0.10 0.09 - 0.06 0.05 0.04 0.03 -
µA/
SRAM4 0.45 0.40 0.37 0.34 0.26 0.21 0.18 0.15 0.12 0.09
MHz
APB1 1.50 1.39 1.23 1.10 - 0.73 0.61 0.51 0.40 -
CRS 0.30 0.27 0.25 0.22 - 0.15 0.12 0.10 0.08 -
DTS 2.07 1.89 1.72 1.53 - 1.00 0.85 0.71 0.55 -
FDCAN1 5.09 4.64 4.21 3.79 - 2.46 2.08 1.75 1.35 -
FDCAN1 indep(1) 2.70 2.41 2.20 1.99 - 1.30 1.10 0.93 0.71 -
APB1

I2C1 0.98 0.90 0.81 0.72 - 0.48 0.40 0.34 0.26 -

I2C1 indep(1) 2.26 2.06 1.86 1.69 - 1.09 0.92 0.78 0.59 -
I2C2 3.24 2.95 2.67 2.40 - 1.57 1.33 1.11 0.86 -
(1)
I2C2 indep 2.30 2.09 1.90 1.72 - 1.11 0.94 0.79 0.61 -
I2C4 1.26 1.15 1.04 0.92 - 0.61 0.52 0.43 0.33 -
I2C4 indep(1) 2.43 2.21 2.00 1.81 - 1.17 0.99 0.84 0.64 -

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Table 72. Typical dynamic current consumption of peripherals (continued)

LDO SMPS

Range1

Range2

Range3

Range4

Range1

Range2

Range3

Range4
Bus Peripheral Unit

Stop 1
Stop 2

Stop 1
Stop 2
LPTIM2 1.71 1.56 1.42 1.26 - 0.83 0.70 0.59 0.46 -
(1)
LPTIM2 indep 4.20 3.83 3.48 3.15 - 2.03 1.72 4.95 1.11 -
SPI2 1.90 1.73 1.57 1.40 - 0.92 0.77 0.66 0.51 -
SPI2 indep(1) 0.81 0.75 0.68 0.62 - 0.40 0.33 0.28 0.21 -
TIM2 4.01 3.64 3.31 2.99 - 1.93 1.64 1.37 1.06 -
TIM3 4.51 4.10 3.72 3.35 - 2.18 1.84 1.55 1.19 -
TIM4 4.27 3.88 3.52 3.16 - 2.06 1.74 1.46 1.12 -
TIM5 3.95 3.60 3.27 2.93 - 1.91 1.62 1.36 1.04 -
TIM6 0.95 0.86 0.78 0.69 - 0.46 0.39 0.33 0.25 -
TIM7 0.90 0.82 0.75 0.65 - 0.44 0.37 0.31 0.24 -
APB1

UART4 1.86 1.70 1.54 1.39 - 0.90 0.76 0.64 0.50 -

(1)
UART4 indep 3.47 3.17 2.87 2.60 - 1.68 1.42 1.19 0.93 -
UART5 1.93 1.76 1.60 1.44 - 0.94 0.79 0.66 0.51 - µA/
UART5 indep(1) 3.57 3.25 2.95 2.67 - 1.72 1.46 1.23 0.95 - MHz

UCPD1 1.60 1.46 1.33 1.17 - 0.78 0.66 0.55 0.43 -

USART2 5.53 5.04 4.57 4.12 - 2.67 2.26 1.91 1.46 -
(1)
USART2 indep 3.57 3.24 2.95 2.65 - 1.72 1.46 1.22 0.94 -
USART3 2.10 1.91 1.73 1.57 - 1.02 0.86 0.72 0.56 -
USART3 indep(1) 4.24 3.86 3.5 3.17 - 2.05 1.73 1.45 1.12 -
WWDG 0.37 0.34 0.31 0.25 - 0.18 0.15 0.13 0.10 -
APB2 0.60 0.58 0.50 0.42 - 0.29 0.25 0.20 0.16 -
SAI1 2.10 1.90 1.73 1.55 - 1.01 0.86 0.72 0.55 -
SAI1 indep(1) 1.36 1.23 1.11 0.95 - 0.66 0.55 0.46 0.34 -
APB2

SAI2 1.98 1.80 1.64 1.48 - 0.96 0.81 0.68 0.53 -

(1)
SAI2 indep 1.25 1.14 1.02 0.92 - 0.60 0.51 0.43 0.40 -
SPI1 2.17 1.97 1.79 1.63 - 1.05 0.89 0.75 0.57 -

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Table 72. Typical dynamic current consumption of peripherals (continued)

LDO SMPS

Range1

Range2

Range3

Range4

Range1

Range2

Range3

Range4
Bus Peripheral Unit

Stop 1
Stop 2

Stop 1
Stop 2
SPI1 indep(1) 0.97 0.88 0.79 0.72 - 0.47 0.39 0.33 0.25 -
TIM1 6.14 5.59 5.08 4.60 - 2.96 2.52 2.11 1.63 -
TIM15 3.37 3.06 2.79 2.51 - 1.63 1.38 1.16 0.89 -
TIM16 2.60 2.36 2.15 1.94 - 1.25 1.06 0.90 0.69 -
APB2

TIM17 2.40 2.18 1.99 1.79 - 1.16 0.98 0.82 0.63 -

TIM8 6.24 5.69 5.16 4.66 - 3.01 2.55 2.15 1.65 -
USART1 2.38 2.16 1.96 1.76 - 1.14 0.97 0.81 0.62 -
USART1 indep(1) 4.48 4.09 3.71 3.35 - 2.17 1.84 1.54 1.19 -
APB3 0.49 0.48 0.40 0.36 - 0.24 0.20 0.16 0.13 -
COMP 0.20 0.18 0.16 0.14 0.15 0.10 0.08 0.06 0.05 0.05
I2C3 0.79 0.71 0.65 0.58 0.59 0.38 0.32 0.27 0.20 0.21
I2C3 indep(1) 1.84 1.66 1.50 1.36 1.36 0.89 0.75 0.63 0.48 0.48
LPTIM1 0.98 0.89 0.81 0.72 0.73 0.48 0.40 0.33 0.25 0.26 µA/
LPTIM1 indep(1) 3.08 2.81 2.49 2.29 2.33 1.46 1.24 1.04 0.81 0.83 MHz
LPTIM3 1.07 0.98 0.89 0.80 0.80 0.52 0.44 0.37 0.28 0.28
LPTIM3 indep(1) 2.85 2.61 2.36 2.15 2.19 1.43 1.22 0.98 0.77 0.78
LPTIM4 0.58 0.52 0.48 0.42 0.43 0.28 0.24 0.20 0.15 0.15
APB3

LPTIM4 indep(1) 1.67 1.50 1.38 1.26 1.30 0.8 0.70 0.57 0.44 0.46
LPUART1 1.18 1.07 0.97 0.87 0.88 0.57 0.48 0.41 0.31 0.31
LPUART1 indep(1) 1.96 1.78 1.62 1.45 1.46 0.95 0.80 0.67 0.52 0.52
OPAMP 0.19 0.17 0.16 0.12 0.14 0.09 0.07 0.07 0.04 0.05
RTC 2.33 2.12 1.92 1.73 1.63 1.12 0.95 0.80 0.61 0.58
SPI3 1.48 1.34 1.22 1.10 1.10 0.71 0.61 0.51 0.38 0.39
SPI3 indep(1) 0.57 0.52 0.47 0.42 0.42 0.28 0.24 0.20 0.15 0.15
SYSCFG 0.29 0.27 0.24 0.22 0.14 0.12 0.10 0.08
VREFBUF 0.13 0.11 0.10 0.08 0.09 0.06 0.05 0.04 0.03 0.03
1. indep = independent clock domain.

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5.3.6 Wakeup time from low-power modes and voltage scaling

transition times
The wakeup times given in the table below are the latency between the event and the
execution of the first user instruction (FSTEN = 1 in PWR_CR3 if not mentioned).
The device goes in low-power mode after the WFE (wait for event) instruction.

Table 73. Low-power mode wakeup timings on LDO(1)

Typ Max
Mode Parameter Conditions Unit
(3 V, 30 °C) (3 V)

Nb of
Wakeup time from SLEEP_PD = 0 14 17 CPU
twu(Sleep) cycles
Sleep to Run mode
SLEEP_PD = 1 with MSI = 24 MHz 8.1 8.8
Wakeup in FLASH,
range 4, FLASHFWU = 1
MSI 24 MHz 2.35 2.5
and SRAM4FWU = 1 in
PWR_CR2
Wakeup in FLASH, MSI 24 MHz 11.0 12.0
Wakeup time from
range 4, FLASHFWU = 0
twu(Stop 0) Stop 0 to Run mode HSI 16 MHz 11.0 12.0
and SRAM4FWU = 0 in
All SRAMs retained PWR_CR2 MSI 1 MHz 37.0 39.0
Wakeup in SRAM2, MSI 24 MHz 4.75 5.00
range 4, FLASHFWU = 0
HSI 16 MHz 6.75 7.4
and SRAM4FWU = 0 in
PWR_CR2 MSI 1 MHz 34.00 36.0 µs
Wakeup in FLASH,
FLASHFWU = 1 and
MSI 24 MHz 13.0 15.0
SRAM4FWU = 1 in
PWR_CR2
Wakeup in FLASH, MSI 24 MHz 22.0 24.0
Wakeup time from
FLASHFWU = 0 and
twu(Stop 1) Stop 1 to Run mode HSI 16 MHz 21.5 24.0
SRAM4FWU = 0 in
All SRAMs retained PWR_CR2 MSI 1 MHz 48.0 51.0
Wakeup in SRAM2, MSI 24 MHz 15.5 18.0
range 4, FLASHFWU = 0
HSI 16 MHz 17.5 20.0
and SRAM4FWU = 0 in
PWR_CR2 MSI 1 MHz 45.0 48.0

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Table 73. Low-power mode wakeup timings on LDO(1) (continued)

Typ Max
Mode Parameter Conditions Unit
(3 V, 30 °C) (3 V)

Wakeup in FLASH,
SRAM4FWU = 1 in MSI 24 MHz 20.0 23.0
PWR_CR2
MSI 24 MHz 23.0 25.0(2)
Wakeup in FLASH,
Wakeup time from
SRAM4FWU = 0 in HSI 16 MHz 22.5 25.0
twu(Stop 2) Stop 2 to Run mode
PWR_CR2
All SRAMs retained MSI 1 MHz 57.0 60.0
MSI 24 MHz 16.5 19.0
Wakeup in SRAM2,
range 4, SRAM4FWU = 0 HSI 16 MHz 18.5 21.0
in PWR_CR2
MSI 1 MHz 54.0 57.0
Wakeup in FLASH,
MSI 24 MHz 68.0 130
FSTEN = 0 in PWR_CR3
MSI 24 MHz 28.50 37.0
Wakeup in FLASH,
Wakeup time from HSI 16 MHz 28.0 36.0
FSTEN = 1 in PWR_CR3
twu(Stop 3) Stop 3 to Run mode
MSI 1 MHz 68.50 91.0 µs
All SRAMs retained
Wakeup in SRAM2, MSI 24 MHz 22.50 31.0
range 4, FLASHFWU = 0
HSI 16 MHz 24.0 32.0
and SRAM4FWU = 0 in
PWR_CR2 MSI 1 MHz 64.5 85.0
Wakeup in FLASH,
MSI 4 MHz 64.5 110
Wakeup time from FSTEN = 0 in PWR_CR3
twu(Standby
Standby with SRAM2
with SRAM2) Wakeup in FLASH, MSI 4 MHz 64.5 83.0
to Run mode
FSTEN = 1 in PWR_CR3 MSI 1 MHz 155 240
Wakeup in FLASH,
MSI 4 MHz 340 420
FSTEN = 0 in PWR_CR3
Wakeup time from
twu(Standby)
Standby to Run mode Wakeup in FLASH, MSI 4 MHz 100 130
FSTEN = 1 in PWR_CR3 MSI 1 MHz 210 290
Wakeup time from
twu(Shutdown) - MSI 4 MHz 610 710
Shutdown to Run mode
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Tested in production at 130°C.

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Table 74. Low-power mode wakeup timings on SMPS(1)

Typ
Max
Mode Parameter Conditions (3 V, Unit
(3 V)
30 °C)

Nb of
Wakeup time from Sleep SLEEP_PD = 0 14 17 CPU
twu(Sleep) cycles
to Run mode
SLEEP_PD = 1 with MSI = 24 MHz 8.1 8.8
Wakeup in FLASH, range 4,
FLASHFWU = 1 and
MSI 24 MHz 2.35 2.5
SRAM4FWU = 1 in
PWR_CR2
Wakeup in FLASH, range 4, MSI 24 MHz 11.0 12.0
Wakeup time from Stop 0
FLASHFWU = 0 and
twu(Stop 0) to Run mode HSI 16 MHz 11.0 12.0
SRAM4FWU = 0 in
All SRAMs retained PWR_CR2 MSI 1 MHz 37.0 39.0
Wakeup in SRAM2, range 4, MSI 24 MHz 4.75 5.0
FLASHFWU = 0 and
HSI 16 MHz 6.75 7.4
SRAM4FWU = 0 in
PWR_CR2 MSI 1 MHz 34.0 36.0
Wakeup in FLASH,
FLASHFWU = 1 and
MSI 24 MHz 7.7 8.3
SRAM4FWU = 1 in
PWR_CR2
Wakeup in FLASH MSI 24 MHz 16.5 18.0 µs
Wakeup time from Stop 1
FLASHFWU = 0 and
twu(Stop 1) to Run mode HSI 16 MHz 16.0 18.0
SRAM4FWU = 0 in
All SRAMs retained PWR_CR2 MSI 1 MHz 42.5 45.0
Wakeup in SRAM2, range 4, MSI 24 MHz 10.0 11.0
FLASHFWU = 0 and
HSI 16 MHz 12.0 13.0
SRAM4FWU = 0 in
PWR_CR2 MSI 1 MHz 39.5 42.0
Wakeup in FLASH
SRAM4FWU = 1 in MSI 24 MHz 17.5 19.0
PWR_CR2
MSI 24 MHz 20.5 22.0
Wakeup in FLASH
Wakeup time from Stop 2
SRAM4FWU = 0 in HSI 16 MHz 20.0 22.0
twu(Stop 2) to Run mode
PWR_CR2
All SRAMs retained MSI 1 MHz 54.0 70.0
MSI 24 MHz 14.0 16.0
Wakeup in SRAM2, range 4,
SRAM4FWU = 0 in HSI 16 MHz 16.0 18.0
PWR_CR2
MSI 1 MHz 51.5 74.0

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Table 74. Low-power mode wakeup timings on SMPS(1) (continued)

Typ
Max
Mode Parameter Conditions (3 V, Unit
(3 V)
30 °C)

Wakeup in FLASH,
MSI 24 MHz 130 160
FSTEN = 0 in PWR_CR3
MSI 24 MHz 32.5 37.0
Wakeup in FLASH,
Wakeup time from Stop 3 HSI 16 MHz 32.0 36.0
FSTEN = 1 in PWR_CR3
twu(Stop 3) to Run mode
MSI 1 MHz 72.5 94.0
All SRAMs retained
MSI 24 MHz 26.5 31.0
Wakeup in SRAM2, range 4 HSI 16 MHz 28.0 32.0
MSI 1 MHz 68.5 89.0
Wakeup in FLASH, µs
MSI 4 MHz 61.5 80.0
Wakeup time from FSTEN = 0 in PWR_CR3
twu(Standby
Standby with SRAM2 to
with SRAM2) Wakeup in FLASH, MSI 4 MHz 61.5 80.0
Run mode
FSTEN = 1 in PWR_CR3 MSI 1 MHz 150 240
Wakeup in FLASH,
MSI 4 MHz 340 420
FSTEN = 0 in PWR_CR3
Wakeup time from
twu(Standby)
Standby to Run mode Wakeup in FLASH, MSI 4 MHz 100 130
FSTEN = 1 in PWR_CR3 MSI 1 MHz 210 290
Wakeup time from
twu(Shutdown) - MSI 4 MHz 610 710
Shutdown to Run mode
1. Evaluated by characterization. Not tested in production.

Table 75. Regulator mode transition times(1)

Symbol Parameter Conditions Typ (3 V, 30 °C) Max (3 V) Unit
(3)
Range 4 16.0 20.0
Range 3 15.0 17.0
tLDO(2) SMSP to LDO transition time
Range 2 14.0 18.0
Range 1 14.0 16.0
µs
Range 4 14.0 16.0(3)
Range 3 17.0 20.0
tSMPS(2) LDO to SMPS transition time
Range 2 16.0 19.0
Range 1 16.0 19.0

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Table 75. Regulator mode transition times(1) (continued)

Symbol Parameter Conditions Typ (3 V, 30 °C) Max (3 V) Unit

LDO 19.0 21.0

Range 4 to range 3
SMPS 25.0 38.0
LDO 13.0 15.0
Range 3 to range 2
SMPS 13.0 23.0
tVOST(4) µs
LDO 12.0 14.0
Range 2 to range 1
SMPS 12.0 17.0
LDO 42.0 47.0
Range 4 to range 1
SMPS 48.0 76.0
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Time to REGS change in PWR_SVMSR.
3. Tested in production at 30°C.
4. Time to VOSRDY = 1 in PWR_VOSR.

Table 76. Wakeup time using USART/LPUART(1)

Symbol Parameter Typ Max Unit

Wakeup time needed to calculate the maximum USART/LPUART baudrate that

tWUUSART (2)
is needed to wake up from Stop mode when the USART/LPUART kernel clock - μs
tWULPUART
source is HSI16/MSI.
1. Specified by design. Not tested in production.
2. This wakeup time is the HSI16 (see Table 81) or the MSI (see Table 82) oscillator maximum startup time.

5.3.7 External clock timing characteristics

High-speed external user clock generated from an external source
In bypass mode, the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14: I/O port
characteristics. However, the recommended clock input waveform is shown in the figure
below.

Table 77. High-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock source Voltage scaling range 1, 2, 3 - - 55

fHSE_ext MHz
frequency Voltage scaling range 4 - - 25
VHSEH OSC_IN input pin high-level voltage - 0.7 × VDD - VDD
V
VHSEL OSC_IN input pin low level voltage - VSS - 0.3 × VDD

tw(HSEH) Voltage scaling range 1, 2, 3 7 - -

OSC_IN high or low time ns
tw(HSEL) Voltage scaling range 4 18 - -
1. Specified by design. Not tested in production.

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Figure 28. AC timing diagram for high-speed external clock source

VHSE
tw(HSEH)

VHSEH
70%
30%
VHSEL
t
THSE tw(HSEL)
MSv67850V3

Low-speed external user clock generated from an external source

In bypass mode, the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14: I/O port
characteristics. However, the recommended clock input waveform is shown in Figure 29
and Figure 30.

Table 78. Low-speed external user clock characteristics(1)

Symbol Parameter Min Typ Max Unit

fLSE_ext User external clock source frequency 5 32.768 40 kHz

VLSE_ext_PP OSC32_IN peak-to-peak amplitude 0.3 - VSW(2)
V
VLSE_ext OSC32_IN input range 0 - VSW(2)
tw(LSEH)
OSC32_IN high or low time for square signal input 10 - - μs
tw(LSEL)
1. Specified by design. Not tested in production.
2. VSW = VDD when VDD is above VBOR0, and VSW=VBAT when VDD is below VBOR0.

Figure 29. AC timing diagram for low-speed external square clock source
VLSE_ext
tw(LSEH)
VLSEH
70%
VLSE_ext_PP
30%
VLSEL
t
tLSE = 1/fLSE_ext tw(LSEL)
MSv67851V3

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Figure 30. AC timing diagram for low-speed external sinusoidal clock source
VLSE_ext

VLSE_ext_PP

tLSE_ext = 1/fLSE_ext
MSv69160V1

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in the table below.
In the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins, in order to minimize the output distortion and startup
stabilization time. Refer to the crystal resonator manufacturer for more details on the
resonator characteristics (frequency, package, accuracy).

Table 79. HSE oscillator characteristics(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 - 50 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 8
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 4 MHz - 670 -
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 8 MHz - 530 -
HSE current
IDD(HSE) VDD = 3 V, Rm = 45 Ω, CL = 10 pF @ 8 MHz - 580 - μA
consumption
VDD = 3 V, Rm = 30 Ω, CL = 5 pF @ 48 MHz - 980 -
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 48 MHz - 1700 -
VDD = 3 V, Rm = 30 Ω, CL = 20 pF @ 48 MHz - 2700 -
Maximum critical crystal
Gmcritmax Startup - - 1.5 mA/V
transconductance Gm
tsu(HSE)
(4) Startup time VDD stabilized - 2 - ms

1. Specified by design. Not tested in production.

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2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see the figure below). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance that is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note ‘Oscillator design guide
for STM8AF/AL/S, STM32 MCUs and MPUs’ (AN2867).

Figure 31. Typical application with a 8 MHz crystal

Resonator with integrated

capacitors
CL1

OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain

REXT (1) OSC_OUT

CL2

MS19876V1

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in the table below. In the application,
the resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. Refer to
the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

Table 80. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

LSEDRV[1:0] = 01, medium low-drive capability - 350 -

LSE current
IDD(LSE) LSEDRV[1:0] = 10, medium high-drive capability - 450 - nA
consumption
LSEDRV[1:0] = 11, high-drive capability - 600 -

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Table 80. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (continued)

Symbol Parameter Conditions(2) Min Typ Max Unit

LSEDRV[1:0] = 01, medium low-drive capability - - 0.75

Maximum critical
Gmcritmax LSEDRV[1:0] = 10, medium high-drive capability - - 1.7 µA/V
crystal Gm
LSEDRV[1:0] = 11, high-drive capability - - 2.7
Internal stray
CS_PARA parasitic - - 3 - pF
capacitance(3)
tSU(LSE)(4) Startup time VDD is stabilized - 2 - s
1. Specified by design. Not tested in production.
2. Refer to the note below this table.
3. CS_PARA is the equivalent capacitance seen by the crystal due to OSC32_IN and OSC32_OUT internal parasitic
capacitances.
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note ‘Oscillator design guide
for STM8AF/AL/S, STM32 MCUs and MPUs’ (AN2867).

Figure 32. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors
CL1
OSC32_IN fLSE
32.768 kHz resonator Drive
CS programmable
amplifier

OSC32_OUT
CL2
Note: CL1 and CL2 are external load capacitances. Cs (stray capacitance) is the sum of the device OSC32_IN/OSC32_OUT pins
equivalent parasitic capacitance (CS_PARA), and the PCB parasitic capacitance. MSv70418V1

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.

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5.3.8 Internal clock timing characteristics

The parameters given in the table below are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 33. The provided curves
are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Table 81. HSI16 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI16 VDD = 3.0 V, TJ = 30 °C 15.92 16 16.08

TJ = –10 °C to 100 °C,
HSI16 frequency after factory 15.84 - 16.16
1.58 ≤ VDD ≤ 3.6 V MHz
fHSI16(1) calibration
TJ = –40 °C to 130 °C,
15.65 - 16.25
1.58 ≤ VDD ≤ 3.6 V
TRIM(2) HSI16 user trimming step - 18 29 40 kHz
DuCy(HSI16)(2) Duty cycle - 45 - 55 %
(2)
tsu(HSI16) HSI16 oscillator startup time - - 2.5 3.6
μs
tstab(HSI16)(2) HSI16 oscillator stabilization time At 1% of target frequency - 4 6
IDD(HSI16)(2) HSI16 oscillator power consumption - - 150 210 μA
1. Evaluated by characterization. Not tested in production. It does not take into account package and soldering effects.
2. Specified by design. Not tested in production.

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Multi-speed internal (MSI) RC oscillator

Table 82. MSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

MSI range 0
47.74 48 48.70
(MSIRC0)
MSI range 1 23.87 24 24.35
MSI range 2 15.91 16 16.23
MSI range 3 11.93 12 12.17
MSI range 4
3.98 4 4.06
(MSIRC1)
MSI range 5 1.99 2 2.03 MHz
MSI range 6 1.33 1.33 1.35
MSI range 7 0.99 1 1.01
MSI mode
MSI range 8
3.05 3.08 3.12
(MSIRC2)
MSI range 9 1.53 1.54 1.56
MSI range 10 1.02 1.03 1.04
MSI range 11 0.76 0.77 0.78
MSI range 12
397.68 400 405.71
(MSIRC3)
MSI frequency
VDD = 3 V MSI range 13 198.84 200 202.86
fMSI after factory kHz
TJ = 30 °C
calibration MSI range 14 132.56 133 135.24
MSI range 15 99.42 100 101.43
MSI range 0
- 48.005 -
(MSIRC0)
MSI range 1 - 24.003 -
MSI range 2 - 16.002 -
MSI range 3 - 12.001 -
MSI range 4
- 3.998 -
PLL (MSIRC1)
mode(2) MSI range 5 - 1.999 - MHz
XTAL =
32.768 kHz MSI range 6 - 1.333 -
MSI range 7 - 0.999 -
MSI range 8
- 3.08 -
(MSIRC2)
MSI range 9 - 1.54 -
MSI range 10 - 1.027 -
MSI range 11 - 0.77 -

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Table 82. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

MSI range 12
- 393 - MHz
(MSIRC3)
MSI frequency PLL mode
VDD = 3 V MSI range 13 - 196.6 -
fMSI (cont’d) after factory XTAL =
TJ = 30 °C
calibration 32.768 kHz MSI range 14 - 131 - kHz
MSI range 15 - 98.3 -
MSI range 0, 4, 8, or 12 38 - 62
(3)
DuCy(MSI) Duty cycle MSI range 2, 6, 10, or 14 31 - 69
Other MSI ranges 48 - 52
User trimming
TRIM - - 0.4 -
step
MSI oscillator
frequency drift
(4) over
∆TEMP(MSI) MSI mode TJ = –40 to 130 °C -4 - 2
temperature
(reference is
30 °C)

MSI range 1.58 ≤ VDD ≤ 3.6 V -4 - 1

%
0 to 3 2.4 ≤ VDD ≤ 3.6 V -1 - 1

MSI range 1.58 ≤ VDD ≤ 3.6 V -3 - 1

MSI oscillator
4 to 7 2.4 ≤ VDD ≤ 3.6 V -1 - 1
frequency drift
∆VDD(MSI)(4) MSI mode
over VDD 1.58 ≤ VDD ≤ 3.6 V -3 - 1
MSI range
(reference is 3V)
8 to 11 2.4 ≤ VDD ≤ 3.6 V -1 - 1

MSI range 1.58 ≤ VDD ≤ 3.6 V -3 - 1

12 to 15 2.4 ≤ VDD ≤ 3.6 V -1 - 1
MSI frequency
∆FSAMPLING variation in
(3)(4) MSI mode TJ = –40 to 130 °C - - 0.2
(MSI) sampling mode
(MSIBIAS = 1)
MSI range 0 - 60 -
RMS MSI range 4 - 160 -
CC
cycle-to-cycle PLL mode
jitter(MSI)(3) MSI range 8 - 200 -
jitter
MSI range 12 - 1100 -
ps
MSI range 0 - 40 -
MSI range 4 - 130 -
P jitter(MSI)(3) RMS period jitter PLL mode
MSI range 8 - 170 -
MSI range 12 - 800 -

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Table 82. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

13
MSIRC0
MSI range 0 to 3 - - cycles +
11 MSI
cycles
4
MSIRC1
MSI range 4 to 7 - - cycles +
11 MSI
MSI oscillator cycles
tsu(MSI)(3)
startup time(5) 4

cycles
MSIRC2
MSI range 8 to 11 - - cycles +
11 MSI
cycles
4
MSIRC3
MSI range 12 to 15 - - cycles +
11 MSI
cycles
3
MSI oscillator destina-
tswitch(MSI)(3) - - -
transition time(6) tion MSI
cycles
Continuous
- - 10
Normal mode(7)
Final frequency µs
mode Sampling
- - 200
mode(8)
MSI oscillator PLL mode,
tstab(MSI)(3) All MSI 1% of final
stabilization time MSIPLL - - 0.8 ms
ranges frequency
FAST = 0
PLL mode,
cycles
MSIPLL All MSI ranges 2
FAST = 1
MSI range 0 to 3 - 6.6 -
MSI range 4 to 7 - 1.6 -
MSI PLL-mode LDO
oscillator power MSI range 8 to 11 - 1.4 -
MSIPLL
consumption MSI range 12 to 15 - 0.8 -
IDD(MSI_OFF EN = 1 and
(3) when MSI is µA
_PLLFAST) MSIPLL MSI range 0 to 3 - 4.7 -
disabled with
FAST = 1
PLL accuracy MSI range 4 to 7 - 1.4 -
retention SMPS
MSI range 8 to 11 - 1.3 -
MSI range 12 to 15 - 0.8 -

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Table 82. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

21 + 2.5
MSI range 0 to 3 - -
µA/MHz
LDO
19 + 2.5
MSI range 4 to 15 - -
Continuous µA/MHz
mode(7) 21 + 1,3
MSI range 0 to 3 - -
µA/MHz
SMPS(9)
19 + 1,3
MSI range 4 to 15 - -
MSI oscillator µA/MHz
IDD(MSI)(3) power 3 + 2.5 µA
consumption Range 0 to 3 - -
µA/MHz
LDO 1+
Range 4 to 15 - 2.5µA/ -
Sampling MHz
mode(8)
3+1
Range 0 to 3 - -
µA/MHz
SMPS
1+1
Range 4 to 15 - -
µA/MHz
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. In PLL mode, the MSI accuracy is the LSE crystal accuracy.
3. Specified by design. Not tested in production.
4. This is a deviation for an individual part once the initial frequency has been measured.
5. The MSI startup time is the time when the four MSIRCs are in power down.
6. This delay is the time to switch from one MSIRC to another one. In case the destination MSIRC is in power down, the total
delay is tsu(MSI) + tswitch(MSI).
7. The MSI is in continuous mode when the internal regulator is in voltage range 1, 2 or 3.
8. The MSI is in sampling mode when MSIBIAS = 1 in RCC_ICSCR1, and the regulator is in voltage range 4, or when the
device is in Stop 1 or Stop 2 mode.
9. SMPS efficiency in range 1, based on VCORE current = 19.4 mA (CoreMark current on VCORE at 160 MHz).

High-speed internal 48 MHz (HSI48) RC oscillator

Table 83. HSI48 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI48 HSI48 frequency after factory calibration VDD = 3.0 V, TJ = 30 °C 47.5 48 48.5 MHz

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Table 83. HSI48 oscillator characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit
(1)
TRIM User trimming step - - 0.12 0.18
USER TRIM
User trimming coverage ±63 steps ±4.5 ±7.56 -
COVERAGE(2)
DuCy(HSI48)(1) Duty cycle - 45 - 55
Accuracy of the HSI48 oscillator over %
ACCHSI48_REL 1.58 V ≤ VDD ≤ 3.6 V,
(2) temperature (factory calibrated) -3 - 2
TJ = –40 to 125 °C
Reference is 3 V and 30 °C(3).
3.0 V ≤ VDD ≤ 3.6 V - 0.025 0.05
∆VDD(HSI48)(1) HSI48 frequency drift with VDD(4)
1.58 V ≤ VDD ≤ 3.6 V - 0.05 0.1
Next transition jitter
NT jitter(1) - - ±0.15 -
Accumulated jitter on 28 cycles(5)
ns
Paired transition jitter
PT jitter(1) - - ±0.25 -
Accumulated jitter on 56 cycles(5)
tsu(HSI48)(1) HSI48 oscillator startup time - - 2.5 6 μs
(1)
IDD(HSI48) HSI48 oscillator power consumption - - 350 400 μA
1. Specified by design. Not tested in production.
2. Evaluated by characterization. Not tested in production.
3. ∆fHSI = ACCHSI48_REL + ∆VDD.
4. These values are obtained with one of the following formula: (Freq(3.6 V) - Freq(3.0 V)) / Freq(3.0 V) or
(Freq(3.6 V) - Freq(1.58 V)) / Freq(1.58 V).
5. Jitter measurements are performed without clock source activated in parallel.

Figure 33. HSI48 frequency versus temperature

MSv69123V1

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Secure high-speed internal (SHSI) RC oscillator

Table 84. SHSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fSHSI SHSI frequency - - 48 - MHz

tSU(SHSI) SHSI oscillator startup time - - 2.5 6 μs
IDD(SHSI) SHSI oscillator power consumption - - 350 400 μA
1. Specified by design. Not tested in production.

Low-speed internal (LSI) RC oscillator

Table 85. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 0 31.4 - 32.6

fLSI LSI frequency VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 1 0.245 - 0.255 kHz
1.58 V≤ VDD ≤ 3.6 V, TJ = –40 to 125 °C 30.4(1) - 33.6(1)
DuCy(LSI) LSI duty cycle LSIPREDIV = 1 - 50 - %
tSU(LSI) (2) LSI oscillator startup time - - 230 260
μs
(2)
tSTAB(LSI) LSI oscillator stabilization time 5% of final frequency - 230 260

LSI oscillator power LSIPREDIV = 0 - 140 255

IDD(LSI)(2) nA
consumption LSIPREDIV = 1 - 130 240
1. Evaluated by characterization. Not tested in production.
2. Specified by design. Not tested in production.

5.3.9 PLL characteristics

The parameters given in the table below are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 33.

Table 86. PLL characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock - 4 - 16 MHz

fPLL_IN PLL input clock
- 10 - 90 %
duty cycle
Voltage scaling range 1 1 - 160(2)
PLL P, Q, R
fPLL_OUT Voltage scaling range 2 1 - 110
output clock
Voltage scaling range 3 1 - 55 MHz
Voltage scaling range 1, 2 128 - 544
fVCO_OUT PLL VCO output Voltage scaling range 3 128 - 330
Duty cycle with division 1 40 - 60 %

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Table 86. PLL characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Integer mode - 25 50
tLOCK(3)(4) PLL lock time μs
Fractional mode - 40 65

RMS cycle-to- Integer mode, VCO = 544 MHz - 20 -

cycle jitter Fractional mode, VCO = 544 MHz - 70 -
Integer mode, VCO = 544 MHz - 35 -
Jitter RMS period jitter ±ps
Fractional mode, VCO = 544 MHz - 45 -
Long-term Integer mode, VCO = 544 MHz - 160 -
jitter(5),
fPLL_IN = 8 MHz Fractional mode, VCO = 544 MHz - 170 -

VCO freq = 160 MHz,

Range 1 - 370 -
1 clock output
VCO freq = 160 MHz,
Range 1 - 390 -
3 clock outputs
PLL power Range 1 - 460 -
consumption on VCO freq = 200 MHz,
IDD(PLL) Range 2 - 435 -
VDD 1 clock output
with LDO Range 3 - 410 -
VCO freq = 336 MHz,
Range 1 - 710 -
1 clock output
VCO freq = 544 MHz,
Range 1 - 1100 -
1 clock output
μA
VCO freq = 160 MHz,
Range 1, IVCORE(6) = 19.4 mA - 260 -
1 clock output
VCO freq = 160 MHz,
Range 1, IVCORE(6) = 19.4 mA - 270 -
3 clock outputs
PLL power Range 1, IVCORE(6) = 19.4 mA - 320 -
consumption on VCO freq = 200 MHz,
IDD(PLL) Range 2, IVCORE(6) = 11.7 mA - 300 -
VDD 1 clock output
with SMPS Range 3, IVCORE(6) = 5.74 mA - 290 -
VCO freq = 336 MHz,
Range 1, IVCORE(6) = 19.4 mA - 470 -
1 clock output
VCO freq = 544 MHz,
Range 1, IVCORE(6) = 19.4 mA - 730 -
1 clock output
1. Specified by design and not tested in production, unless otherwise specified.
2. PLL1 output Q and PLL2 output Q can be up to 200 MHz only when selected as OCTOSPI clock.
3. Evaluated by characterization. Not tested in production.
4. Lock time is the duration until PLLxRDY flag (2% of final frequency).
5. Measured on 5000 cycles.
6. SMPS efficiency based on CoreMark RUN current on VCORE at max frequency of each voltage range.

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5.3.10 Flash memory characteristics

Table 87. Flash memory characteristics(1)

Symbol Parameter Conditions Typ Max(2) Unit

Normal mode 118 118

tprog 128-bit programming time µs
Burst mode 48 48
fAHB = 160 MHz, normal mode 60.2 -
tprog_page One 8-Kbyte page programming time
fAHB = 160 MHz, burst mode 24.5 -
fAHB = 160 MHz, normal mode 7710 -
tprog_bank One 1-Mbyte bank programming time
fAHB = 160 MHz, burst mode 3140 -
ms
10 k endurance cycles 1.5 2.4
tERASE One 8-Kbyte page erase time
100 k endurance cycles 1.7 3.4
Mass erase time (one bank) 195 308
tME 10 k endurance cycles
Mass erase time (two banks) 390 616
Write mode 2.1 -
Average consumption from VDD
Erase mode 1.3 -
IDD(3) mA
Write mode 2.6 -
Maximum current (peak)
Erase mode 3.0 -
1. Specified by design. Not tested in production.
2. Evaluated by characterization after cycling. Not tested in production.
3. Evaluated by characterization. Not tested in production.

Table 88. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

Whole bank 10
NEND Endurance TA = –40 to 125 °C kcycles
Limited to 256 Kbytes per bank 100
TA = 85 °C after 1 kcycle(2) 30
TA = 105 °C after 1 kcycle (2)
15
TA = 125 °C after 1 kcycle(2) 10
Whole bank
TA = 55 °C after 10 kcycles (2)
30
tRET Data retention TA = 85 °C after 10 kcycles(2) 15 Years
(2)
TA = 105 °C after 10 kcycles 10
TA = 55 °C after 100 kcycles(2) 30
Limited to 256 Kbytes per bank TA = 85 °C after 100 kcycles(2) 15
TA = 105 °C after 100 kcycles(2) 10
1. Evaluated by characterization. Not tested in production.
2. Cycling performed over the whole temperature range.

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5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling two LEDs through the
I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The
failure is indicated by the LEDs as follows:
• Electrostatic discharge (ESD) (positive and negative): applied to all device pins until a
functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB (fast transient voltage burst) (positive and negative): applied to VDD and VSS pins
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in the table below. They are based on the EMS levels and classes
defined in application note EMC design guide for STM8, STM32 and Legacy MCUs
(AN1709).

Table 89. EMS characteristics

Level/
Symbol Parameter Conditions
Class

Voltage limits to be applied on any I/O pin to VDD = 3.3 V, TA = +25 °C, fHCLK = 160 MHz,
VFESD 3B
induce a functional disturbance BGA169 conforming to IEC 61000-4-2
Fast transient voltage burst limits to be
VDD = 3.3 V, TA = +25 °C, fHCLK = 160 MHz,
VEFTB applied through 100 pF on VDD and VSS pins 5A
BGA169 conforming to IEC 61000-4-4
to induce a functional disturbance

Designing hardened software to avoid noise problems

The EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. Note that good EMC performance is
highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for the application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for
1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened

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to prevent unrecoverable errors occurring. See application note Software techniques for
improving microcontrollers EMC performance (AN1015) for more details.

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard that specifies the test board and the pin loading.

Table 90. EMI characteristics for fHSE = 8 MHz and fHCLK = 160 MHz
Monitored frequency
Symbol Parameter Conditions Value Unit
band

0.1 MHz to 30 MHz 5

30 MHz to 130 MHz 6
Peak(1) VDD = 3.6 V, TA = 25 °C, dBμV
SEMI BGA169 package compliant 130 MHz to 1 GHz 6
with IEC 61967-2
1 GHz to 2 GHz 7
Level(2) 0.1 MHz to 2 GHz 2 -
1. Refer to the EMI radiated test section of the application note EMC design guide for STM8, STM32 and Legacy MCUs
(AN1709).
2. Refer to the EMI level classification section of the application note EMC design guide for STM8, STM32 and Legacy MCUs
(AN1709).

5.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, latch-up) using specific measurement methods, the
device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.

Table 91. ESD absolute maximum ratings(1)

Max
Symbol Ratings Conditions Packages Class Unit
value

Electrostatic discharge TA = 25 °C, conforming to

VESD(HBM) All 2 2000
voltage (human body model) ANSI/ESDA/JEDEC JS-001
LQFP100
C1 250
LQFP144
UFQFPN48 V
Electrostatic discharge TA = 25 °C, conforming to LQFP48 C2A 500
VESD(CDM)
voltage (charge device model) ANSI/ESDA/JEDEC JS-002 LQFP64
WLCSP90
UFBGA132 C2B 750
UFBGA169
1. Evaluated by characterization. Not tested in production.

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Static latch-up
The following complementary static tests are required on three parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78E IC latch-up standard.

Table 92. Electrical sensitivities(1)

Symbol Parameter Conditions Class

LU Static latch-up class TJ = 130 °C conforming to JESD78E 2

1. Evaluated by characterization. Not tested in production.

5.3.13 I/O current injection characteristics

As a general rule, the current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) must be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller if
abnormal injection accidentally happens, some susceptibility tests are performed on a
sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating-input mode. While this current is injected
into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter, such as an ADC error above a certain
limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on
adjacent pins (out of the -5 µA/+0 µA range), or other functional failure (for example reset
occurrence or oscillator frequency deviation).
The characterization results are given in the table below. The negative induced leakage
current is caused by the negative injection. The positive induced leakage current is caused
by the positive injection.

Table 93. I/O current injection susceptibility(1)(2)

Functional susceptibility
Symbol Description Unit
Negative injection Positive injection

Injected current on OPAMP1_VINM,

OPAMP2_VINM, PA4, PA5, PB0, PE7, PB15, 0 0
IINJ PC11, and PD0 pins mA

Injected current on all other pins 5 N/A

1. Evaluated by characterization. Not tested in production.
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

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5.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the conditions summarized in Table 33. All I/Os are designed as
CMOS- and TTL-compliant.
Note: For information on GPIO configuration, refer to the application note ‘STM32 GPIO
configuration for hardware settings and low-power consumption’ (AN4899).

Table 94. I/O static characteristics(1)

Sym

Unit
Parameter Conditions Min Typ Max
-bol
1.08 V ≤ VDDIOx ≤ 3.6 V - - 0.3 VDDIOx
I/O input
VIL(2) low-level All I/Os except FT_c - - 0.38 VDDIOx(3)
voltage
FT_c I/Os - - 0.3 VDDIOx
1.08 V ≤ VDDIOx ≤ 3.6 V 0.7 VDDIOx - - V
I/O input
VIH 0.5 VDDIOx
high-level All I/Os except FT_c - -
(2) + 0.2(3)
voltage
FT_c I/Os 0.7 VDDIOx - -
Vhys Input
(3) TT_xx, FT_xx I/Os - 250 - mV
hysteresis

VIN ≤ Max (VDDXXX)(5) - - 150

all I/Os except FT_u, Max (VDDXXX) < VIN
- - 2000
FT_c, FT_d, FT_t, ≤ Max (VDDXXX) + 1 V(6)
TT_xx
Max (VDDXXX) + 1 V < VIN
- - 500
≤ 5.5 V(6)
VIN ≤ Max (VDDXXX)(5) - - 200
Max (VDDXXX) < VIN
- 2500
FT_u I/Os ≤ Max (VDDXXX) + 1 V(6)
Max (VDDXXX) + 1 V < VIN
Input - - 500
Ilkg ≤ 5.5 V(6)
(3)(4) leakage nA
current VIN ≤ Max (VDDXXX) - - 1500
FT_c I/Os
Max (VDDXXX) < VIN ≤ 5 V(6) - - 2000
VIN ≤ Max (VDDXXX) - - 1500
FT_d I/Os
Max (VDDXXX) < VIN ≤ 5.5 V(6) - - 5000
VIN ≤ Max (VDDXXX) 300
Max (VDDXXX) < VIN
3000
FT_t I/Os ≤ Max (VDDXXX) + 1 V(6)
Max (VDDXXX) + 1 V < VIN
600
≤ 5.5 V(6)

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Table 94. I/O static characteristics(1) (continued)

Sym

Unit
Parameter Conditions Min Typ Max
-bol
TT_xx I/Os except
Input OPAMPx_VINM VIN ≤ Max (VDDXXX) - - 500
Ilkg (x = 1, 2)
(3)(4) leakage nA
current OPAMPx_VINM (x = 1, 2) dedicated input leakage
- - (7)
current
Weak
pull-up
RPU - 30 40 50
equivalent
resistor(8)
kΩ
Weak
pull-down
RPD - 30 40 50
equivalent
resistor(8)
I/O pin
CIO - - 5 - pF
capacitance
1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
2. Refer to Figure 34: I/O input characteristics (all I/Os except BOOT0 and FT_c).
3. Specified by design. Not tested in production.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA+ [number of I/Os where VIN is applied on the pad] ₓ Ilkg max.
5. Max (VDDXXX) is the maximum value of all the I/O supplies. The I/O supplies depend on the I/O structure options, as
described in Table 26: Legend/abbreviations used in the pinout table.
6. To sustain a voltage higher than Min (VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal pull-up and pull-down resistors must
be disabled.
7. Refer to Ibias in the OPAMP characteristics table for the values of the OPAMP dedicated input leakage current.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS.
This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

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All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in the figure below.

Figure 34. I/O input characteristics (all I/Os except BOOT0 and FT_c)

MSv69136V1

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Output driving current

The GPIOs (except PC13, PC14, PC15) can sink or source up to ±8 mA, and sink or source
up to ± 20 mA (with a relaxed VOL/VOH). PC13, PC14, PC15 are limited to ±3 mA shared
between the three I/Os.
In the user application, the number of I/O pins tat can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2: Absolute maximum ratings:
• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 31: Current characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS
(see Table 31: Current characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 33. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified).

Table 95. Output voltage characteristics(1)(2)(3)

Symbol Parameter Conditions Min Max Unit

VOL Output low-level voltage CMOS port(4), |IIO| = 8 mA, - 0.4

VOH Output high-level voltage 2.7 V ≤ VDDIOx ≤ 3.6 V VDDIOx - 0.4 -
VOL(5) Output low-level voltage TTL port(4),|IIO| = 8 mA, - 0.4
VOH(5) Output high-level voltage 2.7 V ≤ VDDIOx ≤ 3.6 V 2.4 -
VOL(5) Output low-level voltage All I/Os, |IIO| = 20 mA, - 1.3
VOH(5) Output high-level voltage 2.7 V ≤ VDDIOx ≤ 3.6 V VDDIOx - 1.3 -
VOL(5) Output low-level voltage |IIO| = 4 mA, - 0.4
VOH(5) Output high-level voltage 1.58 V ≤ VDDIOx ≤ 3.6 V VDDIOx - 0.4 - V
VOL(5) Output low-level voltage |IIO| = 1 mA, - 0.4
VOH(5) Output high-level voltage 1.08 V ≤ VDDIOx <3.6 V VDDIOx - 0.4 -
|IIO| = 20 mA,
- 0.4
2.7 V ≤ VDDIOx ≤ 3.6 V
Output low-level voltage for |IIO| = 10 mA,
VOLFM+(5) - 0.4
a FT_f I/O pin in FM+ mode 1.58 V ≤ VDDIOx ≤ 3.6 V
|IIO| = 2 mA,
- 0.4
1.08 V ≤ VDDIOx < 3.6 V
1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
2. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 31:
Current characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
3. FT_t I/O characteristics are degraded in VBAT mode (refer to Table 96).
4. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
5. Specified by design. Not tested in production.

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Table 96. Output voltage characteristics for FT_t I/Os in VBAT mode
Symbol Parameter Conditions Min Max Unit

VOL Output low-level voltage |IIO| = 0.5 mA, 2.7 V ≤ VBAT ≤ 3.6 V, - 0.4
VOH Output high-level voltage VDD off VDDIOx - 0.4 -
V
VOL Output low-level voltage |IIO| = 0.25 mA, 1.58 V ≤ VBAT ≤ 3.6 V, - 0.4
VOH Output high-level voltage VDD off VDDIOx - 0.4 -

Output AC characteristics
The definition and values of output AC characteristics are given in Figure 35: Output AC
characteristics definition and in the table below respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 33.

Table 97. Output AC characteristics, HSLV OFF (all I/Os except FT_c)(1)(2)(3)(4)
Speed Symbol Parameter Conditions Min Max Unit

CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 12.5

CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5

Maximum frequency CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 1

Fmax MHz
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 12.5
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 1
00
CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 17
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33

Output rise and fall time CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 85
tr/tf ns
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 12.5
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 25
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 50

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Table 97. Output AC characteristics, HSLV OFF (all I/Os except FT_c)(1)(2)(3)(4) (continued)
Speed Symbol Parameter Conditions Min Max Unit

CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 55

CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 12.5

Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 2.5

Fmax MHz
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 55
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 12.5
CL = 10 pF, 1.08 V ≤ VDDIOx ≤<1.58 V - 2.5
01
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 5.8
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 10

Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 18
tr/tf ns
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 4.2
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 7.5
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 12
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 100(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33(5)

Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5

Fmax MHz
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 133(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 40(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
10
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 3.3(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 6.0(5)

Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 13.3
tr/tf ns
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 2(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.1(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 9.2

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Table 97. Output AC characteristics, HSLV OFF (all I/Os except FT_c)(1)(2)(3)(4) (continued)
Speed Symbol Parameter Conditions Min Max Unit
(5)
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 100
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33(5)
Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
All I/Os except FT_c, FT_v,
and TT_v CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 133(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 40(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
Fmax MHz
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 140(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 40(5)

Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5

11
FT_v and TT_v I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 166(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 50(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 3.3(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 6.0(5)
Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 13.3
tr/tf All I/Os except FT_c, FT_v, ns
and TT_v CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V 2.0(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V 4.1(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V 9.2
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 2.5(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5.0(5)

11 Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 11
tr/tf ns
(cont’d) FT_v and TT_v I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 1.66(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 3.1(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 7
Fmax Maximum frequency CL = 550 pF, 1.08 V ≤ VDDIOx < 3.6 V - 1 MHz
CL = 100 pF, 1.58 V ≤ VDDIOx < 3.6 V - 50
Fm+ CL = 100 pF, 1.08 V ≤ VDDIOx < 1.58 V - 80
tf Output fall time(6) ns
CL = 550 pF, 1.58 V ≤ VDDIOx < 3.6 V - 100
CL = 550 pF, 1.08 V ≤ VDDIOx < 1.58 V - 220
1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO
port configuration register.
3. Specified by design. Not tested in production.
4. FT_t I/O characteristics are degraded in VBAT mode (refer to Table 100).
5. Compensation system enabled.
6. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.

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Table 98. Output AC characteristics, HSLV ON (all I/Os except FT_c)(1)(2)(3)(4)

Speed Symbol Parameter Conditions Min Max Unit

CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 10

CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4
Fmax Maximum frequency MHz
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 15
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4
00
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 18
CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 32
tr/tf Output rise and fall time ns
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 12
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 21
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 50
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10
Fmax Maximum frequency MHz
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 67
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10
01
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5.3
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10.6
tr/tf Output rise and fall time ns
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 3.1
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5.6
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 75(5)
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
Fmax Maximum frequency MHz
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 100(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
10
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.4(5)
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 9.6
tr/tf Output rise and fall time ns
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 2.2(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4.7
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 75(5)
Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
All I/Os except FT_c, FT_v,
and TT_v CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 100(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
11 Fmax MHz
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 110(5)

Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 25

FT_v and TT_v I/Os CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 150(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 25

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Table 98. Output AC characteristics, HSLV ON (all I/Os except FT_c)(1)(2)(3)(4) (continued)
Speed Symbol Parameter Conditions Min Max Unit
(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.4
Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 9.6
All I/Os except FT_c, FT_v,
and TT_v CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V 2.2(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V 4.7
11 tr/tf ns
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 3.0(5)

Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 6.6
FT_v and TT_v I/Os CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V 1.6(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 3.4
1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of
GPIO port configuration register.
3. Specified by design. Not tested in production.
4. FT_t I/O characteristics are degraded in VBAT mode (refer to Table 100).
5. Compensation system enabled.

Table 99. Output AC characteristics for FT_c I/Os(1)(2)

Speed Symbol Parameter Conditions Min Max Unit

All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 10

Fmax Maximum frequency MHz
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5
00
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 33
tr/tf Output rise and fall time ns
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 66
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 25
Fmax Maximum frequency MHz
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 10
01
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 13
tr/tf Output rise and fall time ns
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 40
Fmax Maximum frequency MHz
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 20
1x
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 8
tr/tf Output rise and fall time ns
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 17
1. Specified by design. Not tested in production.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of
GPIO port configuration register.

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Table 100. Output AC characteristics for FT_t I/Os in VBAT mode(1)

Symbol Parameter Conditions Min Max Unit

CL = 50 pF, 2.7 V ≤ VBAT ≤ 3.6 V, VDD off - 0.5

Fmax Maximum frequency MHz
CL = 50 pF, 1.58 V ≤ VBAT < 2.7 V, VDD off - 0.25
CL = 50 pF, 2.7 V ≤ VBAT ≤ 3.6 V, VDD off - 400
tr/tf Output rise and fall time ns
CL = 50 pF, 1.58 V ≤ VBAT < 2.7 V, VDD off - 900
1. Specified by design. Not tested in production.

Figure 35. Output AC characteristics definition

90% 10%

50% 50%

10% 90%

t r(IO)out t f(IO)out

Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.

5.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized
in Table 33.

Table 101. NRST pin characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) NRST input low-level voltage - - - 0.3 x VDDIOx

V
VIH(NRST) NRST input high-level voltage - 0.7 x VDDIOx - -
NRST Schmitt trigger voltage
Vhys(NRST) - - 200 - mV
hysteresis
RPU Weak pull-up equivalent resistor(2) VIN = VSS 30 40 50 kΩ
tF(NRST) NRST input filtered pulse - - - 50
1.71 V ≤ VDD ≤ 3.6 V 330 - - ns
tNF(NRST) NRST input not-filtered pulse
1.58 V ≤ VDD ≤ 3.6 V 1000 - -
1. Specified by design. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).

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Figure 36. Recommended NRST pin protection

External
reset circuit(1) VDD

RPU
NRST(2) Internal reset
Filter

0.1 μF

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in the above table.
Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.

5.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 102. EXTI input characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit

PLEC Pulse length to event controller - 20 - - ns

1. Specified by design. Not tested in production.

5.3.17 Analog switches booster

Table 103. Analog switches booster characteristics(1)

Symbol Parameter Min Typ Max Unit

VDD Supply voltage 1.6 1.8 3.6 V

tSU(BOOST) Booster startup time - - 50 µs
IDD(BOOST) Booster consumption - - 125 µA
1. Specified by design. Not tested in production.

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5.3.18 14-bit analog-to-digital converter (ADC1) characteristics

Unless otherwise specified, the parameters given in the table below are values derived from
tests performed under ambient temperature, fHCLK frequency and VDDA supply voltage
conditions summarized in Table 33.
Note: It is recommended to perform a calibration after each power-up.

Table 104. 14-bit ADC1 characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog power supply for

VDDA - 1.62 - 3.6
ADC ON

Positive reference VDDA ≥ 2 V 2 - VDDA

VREF+ V
voltage VDDA < 2 V VDDA
Negative reference
VREF- - VSSA
voltage
ADC clock frequency 1.62 V ≤ VDDA ≤ 3.6 V 5(3) - 55 MHz
fADC
ADC clock ratio - 45 - 55 %
Resolution = 14 bits 0.23 - 2.5
Resolution = 12 bits 0.25 - 2.75
fs Sampling rate Msps
Resolution = 10 bits 0.28 - 3.05
Resolution = 8 bits 0.31 - 3.44
tTRIG External trigger period Resolution = 14 bits 26 - - 1/fADC
Conversion voltage
VAIN(4) - 0 - VREF+ V
range
Common mode input
VCIMV - VREF+/2 - 10% VREF+/2 VREF+/2 + 10% V
voltage
Resolution = 14 bits
- - 1000
Tj = 130 °C
Resolution = 12 bits
- - 1000
External input Tj = 130 °C
RAIN(5) Ω
impedance Resolution = 10 bits
- - 4700
Tj = 130 °C
Resolution = 8 bits
- - 22000
Tj = 130 °C
Internal sample and
CADC - - 5 - pF
hold capacitor
tADCVREG_
ADC LDO startup time - - - 17 µs
STUP

tSTAB ADC power-up time LDO already started (3 × 1/fADC) + 1 conversion Cycle
Offset and linearity
tCAL - 25502 1/fADC
calibration time
tOFF_CAL Offset calibration time - 683

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Table 104. 14-bit ADC1 characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Trigger conversion PRESC = 0 3

latency for regular and
PRESC = 1 7
tLATR injected channels,
without aborting the
PRESC = 2 13
conversion
Trigger conversion PRESC = 0 4
latency Injected 1/fADC
tLATRINJ PRESC = 1 9
channels aborting a
regular conversion PRESC = 2 17
ts Sampling time - 5 - 814
Total conversion time
tCONV (including sampling Resolution = N bits ts + N + 3
time)
fs = 2.5 Msps,
- 970 -
resolution = 14 bits
fs = 1 Msps,
- 550 -
resolution = 14 bits
fs = 10 ksps,
- 130 -
ADC consumption on resolution = 14 bits
IDDA_D(ADC) µA
VDDA Differential mode fs = 2.5 Msps,
- 940 -
resolution = 12 bits
fs = 2.5 Msps,
- 840 -
resolution = 10 bits
fs = 2.5 Msps,
- 730 -
resolution = 8bits
fs = 2.5 Msps,
- 140 -
resolution = 14 bits
fs = 1 Msps,
- 80 -
resolution = 14 bits
fs = 10 ksps,
- 13 -
ADC consumption on resolution = 14 bits
IDDV_D(ADC) µA
VREF+ Differential mode f = 2.5 Msps,
s - 140 -
resolution = 12 bits
fs = 2.5 Msps,
- 140 -
resolution = 10 bits
fs = 2.5 Msps,
- 120 -
resolution = 8bits

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Table 104. 14-bit ADC1 characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

fs = 2.5 Msps,
- 980 -
resolution = 14 bits
fs = 1 Msps,
- 550 -
resolution = 14 bits
fs = 10 ksps,
ADC consumption on - 130 -
resolution = 14 bits
IDDA_s(ADC) VDDA Singe-ended µA
mode fs = 2.5 Msps,
- 900 -
resolution = 12 bits
fs = 2.5 Msps,
- 840 -
resolution = 10 bits
fs = 2.5 Msps,
- 770 -
resolution = 8bits
fs = 2.5 Msps,
- 160 -
resolution = 14 bits
fs = 1 Msps,
- 90 -
resolution = 14 bits
fs = 10 ksps,
ADC consumption on - 15 -
resolution = 14 bits
IDDV_s(ADC) VREF+ Single-ended µA
mode fs = 2.5 Msps,
- 150 -
resolution = 12 bits
fs = 2.5 Msps,
- 150 -
resolution = 10 bits
fs = 2.5 Msps,
- 150 -
resolution = 8bits
1. Specified by design. Not tested in production.
2. The voltage booster on the ADC switches must be used when VDDA < 2.4 V (embedded I/O switches).
3. Degraded differential linearity error below 10 MHz.
4. Depending on the package, VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA.
5. The tolerance is 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.

The maximum value of RAIN can be found in the table below.

Table 105. Maximum RAIN for 14-bit ADC1(1)(2) (3)

Resolution RAIN max (Ω) Sampling time [ns] Sampling cycle at 5 MHz Sampling cycle at 55 MHz

47 142
14 bits
(2 LSB 68 145 5 12
tolerance)
100 170

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Table 105. Maximum RAIN for 14-bit ADC1(1)(2) (3) (continued)

Resolution RAIN max (Ω) Sampling time [ns] Sampling cycle at 5 MHz Sampling cycle at 55 MHz

47 135
68 135
100 140
12 bits 150 145 5 12
220 150
330 155
470 180
47 128
68 130
100 132
150 134 5 12
220 140
10 bits 330 146
470 160
680 176
12
1000 200
5
1500 240
20
2200 320
47 123
68 124
100 125
150 128
220 130
12
330 137
5
470 140
8 bits 680 157
1000 178
1500 204
2200 250
20
3300 313
4700 400
36
6800 546 5
10000 830 68
1. Specified by design. Not tested in production.
2. BOOSTEN and ANASWVDD configured properly according to VDD and VDDA values.
3. Values without external capacitor.

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Table 106. 14-bit ADC1 accuracy(1)(2)

Symbol Parameter Conditions(3) Min Typ Max Unit

Single ended - ±25 -

ET Total unadjusted error
Differential - ±28 -
Single ended - ±2 ±5(4)
EO Offset error
Differential - ±2 ±10(4)
Single ended -
EG Gain error ±15 -
Differential -
LSB
Single ended -
fADC ≥ 10 MHz -0.9/+1.5 -0.9/+2.5
Differential -
ED Differential linearity error
Single ended -
fADC < 10 MHz -0.9/+1.5 -1/+3
Differential -
Single ended -
EL Integral linearity error ±2 ±5
Differential -
Single ended 11 12 -
ENOB Effective number of bits bits
Differential 11.8 12.8 -

Signal-to-noise and Single ended 68 74 -

SINAD
distortion ratio Differential 73 78 -
Single ended 68 74 -
SNR Signal-to-noise ratio dB
Differential 73 78 -
Single ended - -84 -80
THD Total harmonic distortion
Differential - -95 -89
1. Evaluated by characterization for BGA packages. Not tested in production. The values for LQFP packages may differ.
2. ADC DC accuracy values are measured after the internal calibration.
3. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in SYSCFG_CFGR1 when
VDDA < 2.4 V). The booster is disabled when VDDA ≥ 2.4 V. Resolution = 14 bits, no oversampling.
4. This parameter may degrade in case of digital activity on adjacent I/Os.

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Figure 37. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA

MSv19880V6

Figure 38. Typical connection diagram when using the ADC

with FT/TT pins featuring analog switch function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter

Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to the ADCx characteristic table for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance
(refer to Table 94: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades the
conversion accuracy. To remedy this, fADC must be reduced.
3. Refer to Table 94: I/O static characteristics for the values of Ilkg.
4. Refer to Section 5.1.6: Power supply scheme.

General PCB design guidelines

The power-supply decoupling must be performed as shown in the corresponding
power-supply scheme. The 100 nF capacitor must be ceramic (good quality) and must be
placed as close as possible to the chip.

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5.3.19 12-bit analog-to-digital converter (ADC4) characteristics

Unless otherwise specified, the parameters given in the table below are values derived from
tests performed under ambient temperature, fHCLK frequency and VDDA supply voltage
conditions summarized in Table 33.
Note: It is recommended to perform a calibration after each power-up.

Table 107. 12-bit ADC4 characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog power supply for ADC

VDDA - 1.62 - 3.6
ON
V
VREF+ Positive reference voltage - 1 - VDDA
VREF- Negative reference voltage - VSSA
ADC clock frequency 1.62 V ≤ VDDA ≤ 3.6 V 0.14 - 55 MHz
fADC
ADC clock duty cycle - 45 - 55 %
Resolution = 12 bits 0.01 - 2.75
Resolution = 10 bits 0.012 - 3.05
fs Sampling rate Msps
Resolution = 8 bits 0.014 - 3.43
Resolution = 6 bits 0.0175 - 3.92
tTRIG External trigger period Resolution = 12 bits 16 - - 1/fADC
(3)
VAIN Conversion voltage range - 0 - VREF+ V
Resolution = 12 bits - - 2.2

External input impedance Resolution = 10 bits - - 6.8

RAIN(4) kΩ
Tj = 130 °C Resolution = 8 bits - - 33.0
Resolution = 6 bits - - 47.0
Internal sample and hold
CADC - - 5 - pF
capacitor
tADCVREG_
ADC LDO startup ready flag time - - - 25 µs
STUP

tSTAB ADC power-up time LDO already started (3 × 1/fADC) + 1 conversion Cycle
tOFF_CAL Offset calibration time - 82
WAIT = 0, AUTOFF = 0,
4
DPD = 0, fADC = HCLK
WAIT = 0, AUTOFF = 0,
tLATR Trigger conversion latency 4 1/fADC
DPD = 0, fADC = HCLK/2
WAIT = 0, AUTOFF = 0,
3.75
DPD = 0, fADC = HCLK/4
ts Sampling time - 1.5 - 814.5

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Table 107. 12-bit ADC4 characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Resolution = N bits,
ts + N + 0.5
VREFPROTEN = 0
Resolution = N bits,
Total conversion time (including VREFPROTEN = 1 ts + N + 0.5 - ts + N + 1.5
tCONV 1/fADC
sampling time) VREFSECSMP = 0
Resolution = N bits,
VREFPROTEN = 1 ts + N + 0.5 - ts + N + 2.5
VREFSECSMP = 1
fs = 2.5 Msps - 360 -
fs = 1 Msps - 180 -
fs = 10 ksps - 10 -
IDDA(ADC) ADC consumption on VDDA
AUTOFF = 1, DPD = 0,
- 9 -
no conversion
AUTOFF = 1, DPD = 1,
- 0.1 -
no conversion
µA
fs = 2.5 Msps - 18 -
fs = 1 Msps - 10.2 -
fs = 10 ksps - 0.12 -
IDDV(ADC) ADC consumption on VREF+
AUTOFF = 1, DPD = 0,
- 0.01 -
no conversion
AUTOFF = 1, DPD = 1,
- 0.01 -
no conversion
1. Specified by design. Not tested in production.
2. The voltage booster on the ADC switches must be used when VDDA < 2.4 V (embedded I/O switches).
3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA.
4. The tolerance is 2 LSBs.

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The maximum value of RAIN can be found in the table below.

Table 108. Maximum RAIN for 12-bit ADC4(1)(2)(3)

Resolution RAIN max (Ω) Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz

47 276
68 288
12.5 19.5
100 306
150 336
220 377
330 442 19.5
39.5
470 526
680 650
1000 840 39.5
12 bits 79.5
1500 1134
2200 1643 79.5
3300 2395
4700 3342
6800 4754 814.5
10000 6840 814.5
15000 9967
22000 14068
33000 19933 N/A
47 86
68 90 3.5
100 95
7.5
150 108
220 116
330 136 7.5
470 161
10 bits 12.5
680 212
1000 276 12.5 19.5
1500 376 39.5
19.5
2200 516
3300 735 79.5
39.5
4700 1012
6800 1423 79.5 814.5

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Table 108. Maximum RAIN for 12-bit ADC4(1)(2)(3) (continued)

Resolution RAIN max (Ω) Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz

10000 2040
15000 2978
10 bits
22000 4356 814.5 814.5
(cont’d)
33000 6443
47000 8925
47 45
68 46
100 48 3.5
150 53 3.5
220 59
330 69
470 81
7.5
680 101
1000 130 7.5
8 bits 1500 177 12.5
2200 242
12.5 19.5
3300 345
4700 475 19.5
39.5
6800 670
39.5
10000 963
79.5
15000 1417
79.5
22000 2040
33000 2995 814.5
814.5
47000 4158
47 32
68 32
100 33
6 bits 1.5 3.5
150 35
220 37
330 41

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Table 108. Maximum RAIN for 12-bit ADC4(1)(2)(3) (continued)

Resolution RAIN max (Ω) Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz

470 49
3.5
680 61 3.5
1000 79
7.5
1500 106
2200 146 7.5
12.5
3300 207
6 bits (cont’d)
4700 286 12.5 19.5
6800 404 19.5
39.5
10000 584 39.5
22000 1250 79.5
79.5
33000 1853
814.5
47000 2607 814.5
1. Specified by design. Not tested in production.
2. BOOSTEN and ANASWVDD configured properly according to VDD and VDDA values.
3. Values without external capacitor.

Table 109. 12-bit ADC4 accuracy(1)(2) (3)

Symbol Parameter Conditions Min Typ Max Unit

ET Total unadjusted error - - ±3 ±7.5

EO Offset error - - ±2 ±5.5
EG Gain error - - ±2 ±6.5 LSB
ED Differential linearity error - - -0.9/+1 -0.9/+1.5
EL Integral linearity error - - ±2 ±3.5
ENOB Effective number of bits - 9.9 10.9 - bits
SINAD Signal-to-noise and distortion ratio - 61.4 67.4 -
SNR Signal-to-noise ratio - 61.6 67.5 - dB
THD Total harmonic distortion - - -74 -70
1. Evaluated by characterization for BGA packages. Not tested in production. The values for LQFP packages may differ.
2. ADC DC accuracy values are measured after the internal calibration.
3. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in SYSCFG_CFGR1 when
VDDA < 2.4 V). This switch is disabled when VDDA ≥ 2.4 V. Resolution = 12 bits, no oversampling.

See Figure 37: ADC accuracy characteristics, Figure 38: Typical connection diagram when
using the ADC with FT/TT pins featuring analog switch function and General PCB design
guidelines.

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5.3.20 Temperature sensor characteristics

Table 110. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - - 1.3 °C

(1)
Avg_Slope Average slope 2 2.5 3.0 mV/°C
V30(2) Voltage at 30°C (±1 °C) 700 752 800
∆(Vcontinuous - Difference of voltage between continuous and mV
- - –10/+4
Vsampling)(3) sampling modes(4)
tSTART
(3) Sensor buffer startup time - 1 10
(TS_BUF)
µs
tS_temp (3) ADC sampling time when reading the temperature 13 - -

Temperature sensor consumption from VDD, when

IDD(TS)(3) - 14 20 µA
selected by ADC
1. Evaluated by characterization. Not tested in production.
2. Measured at VREF+ = VDDA = 3.0 V ±10 mV. The V30 A/D conversion result is stored in the TS_CAL1 byte. Refer to
Table 16: Temperature sensor calibration values.
3. Specified by design. Not tested in production.
4. The temperature sensor is in continuous mode when the regulator is in range 1, 2 or 3. The temperature sensor is in
sampling mode when the regulator is in range 4, or when the device is in Stop 1 or Stop 2 mode.

5.3.21 VCORE monitoring characteristics

Table 111. VCORE monitoring characteristics(1)

Symbol Parameter Min Typ Max Unit

ADC sampling time when reading the VCORE

tS_VCORE 1 - - µs
voltage
1. Specified by design. Not tested in production.

5.3.22 VBAT monitoring characteristics

Table 112. VBAT monitoring characteristics(1)

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 4 × 25.6 - kΩ

Q Ratio on VBAT measurement - 4 - -
(2)
Er Error on Q -5 - 5 %
tS_VBAT(2) ADC sampling time when reading the VBAT 5 - - µs
1. 1.58 V ≤ VBAT ≤ 3.6 V
2. Specified by design. Not tested in production.

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Table 113. VBAT charging characteristics

Symbol Parameter Conditions Min Typ Max Unit

VBRS = 0 - 5 -
RBC Battery charging resistor kΩ
VBRS = 1 - 1.5 -

5.3.23 Digital-to-analog converter characteristics

Table 114. DAC characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage for

VDDA - 1.6 - 3.6
DAC ON

VREF+ Positive reference voltage - 1.6 - VDDA V

VREF- Negative reference voltage - - VSSA -

connected to VSSA 5 - -
DAC output
RL Resistive load connected to
buffer ON 25 - -
VDDA
RO Output impedance DAC output buffer OFF 10 13 16
Output impedance sample VDDA = 2.7 V - - 1.5 kΩ
RBON and hold mode, output
buffer ON VDDA = 2.0 V - - 2.5

Output impedance sample VDDA = 2.7 V - - 16.5

RBOFF and hold mode, output
buffer OFF VDDA = 2.0 V - - 17.5

CL DAC output buffer OFF - - 50 pF

Capacitive load
CSH Sample and hold mode - 0.1 1 µF

Voltage on DAC_OUT DAC output buffer ON 0.2 - VDDA - 0.2

VDAC_OUT V
output DAC output buffer OFF 0 - VREF+
±0.5 LSB - 2.05 3.05
Settling time (full scale: for Normal mode
a 12-bit code transition ±1 LSB - 1.90 3
DAC output
between the lowest and the buffer ON ±2 LSB - 1.85 2.85
highest input codes when CL ≤ 50 pF,
tSETTLING ±4 LSB - 1.80 2.8 µs
DAC_OUT reaches the RL ≥ 5 kΩ
final value of ±0.5 LSB, ±8 LSB - 1.75 2.65
±1 LSB, ±2 LSB, ±4 LSB,
or ±8 LSB) Normal mode DAC output
- 1.7 3
buffer OFF, ±1 LSB, CL = 10 pF
Normal mode DAC output buffer
Wakeup time from off state ON - 4.2 7.5
tWAKEUP (setting the ENx bit in the CL ≤ 50 pF, RL = 5 kΩ
(2) µs
DAC control register) until
the final value ±1 LSB Normal mode DAC output
- 2 5
buffer OFF, CL ≤ 10 pF

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Table 114. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Normal mode DAC output buffer

DC VDDA supply rejection
PSRR ON - -80 -28 dB
ratio
CL ≤ 50 pF, RL = 5 kΩ
DAC output buffer
- 0.7 1.9
DAC_OUT ON, CSH = 100 nF
Sampling time in sample pin ms
DAC output buffer
and hold mode, connected OFF, CSH = - 10.5 15
CSH = 100 nF
100 nF
(code transition between
tSAMP
the lowest input code and DAC_OUT
the highest input code pin not
when DACOUT reaches connected DAC output buffer
- 2 8 µs
the final value ±1 LSB) (internal OFF
connection
only)

(3)
Ileak Output leakage current - - - nA

Internal sample and hold

CIint - 7 9.2 11 pF
capacitor
tTRIM Middle code offset trim time DAC output buffer ON 50 - - µs

Middle code offset for VREF+ = 3.6 V - 1520 -

Voffset µV
1 trim code step VREF+ = 1.6 V - 680 -
No load, middle
- 330 510
DAC output code (0x800)
buffer ON No load, worst
- 470 680
code (0xF1C)

DAC consumption No load,

IDDA(DAC) DAC output µA
from VDDA middle/worst code - - 0.3
buffer OFF
(0x800)
330 × TON 680 × TON
Sample and hold mode, /(TON + /(TON +
-
CSH = 100 nF TOFF) TOFF)
(4) (4)

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Table 114. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

No load, middle
- 170 240
DAC output code (0x800)
buffer ON No load, worst
- 300 400
code (0x0E4)
No load,
DAC output
middle/worst code - 145 180
buffer OFF
(0x800)
DAC consumption
IDDV(DAC) µA
from VREF+ 170 × TON 400 × TON
Sample and hold mode, buffer /(TON + /(TON +
-
ON, CSH = 100 nF (worst code) TOFF) TOFF)
(4) (4)

145 × TON 180 × TON

Sample and hold mode, buffer /(TON + /(TON +
-
OFF, CSH = 100 nF (worst code) TOFF) TOFF)
(4) (4)

1. Specified by design. Not tested in production.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
3. Refer to Table 94: I/O static characteristics.
4. TON is the refresh phase duration. TOFF is the hold phase duration (see the product reference manual for more details).

Figure 39. 12-bit buffered/non-buffered DAC

Buffered/non-buffered DAC

Buffer(1)

RLOAD

12-bit DAC_OUTx
digital-to-analog
converter
CLOAD

(1) The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads
directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in
the DAC_CR register. MSv47959V2

Table 115. DAC accuracy(1)

Symbol Parameter Conditions Min Typ Max Unit

Differential DAC output buffer ON - - ±2

DNL LSB
non-linearity(2) DAC output buffer OFF - - ±2
- Monotonicity 10 bits guaranteed -

Integral DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ - - ±4

INL LSB
non-linearity(3) DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±4

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Table 115. DAC accuracy(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Offset error at code

Offset DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±8
0x800(3)
Offset error at code
Offset1 DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±5
0x001(4) LSB
Offset error at code VREF+ = 3.6 V - - ±5
DAC output buffer ON,
OffsetCal 0x800(3)
CL ≤ 50 pF, RL ≥ 5 kΩ VREF+ = 1.6 V - - ±5
after calibration
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ - - ±0.5
Gain Gain error(5) %
DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±0.5
DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±10
TUE Total unadjusted error DAC output buffer ON, C ≤ 50 pF, R ≥ 5 kΩ, LSB
L L - - ±14
after calibration
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ,
- 70.6 -
Signal-to-noise 1 kHz, BW = 500 kHz
SNR
ratio(6) DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz,
- 72 -
BW = 500 kHz
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - -79 - dB
Total harmonic
THD
distortion(6) DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - -81 -

Signal-to-noise and DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.1 -
SINAD
distortion ratio(6) DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - 71.5 -

Effective number DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.3 -
ENOB bits
of bits DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - 11.6 -
1. Specified by design. Not tested in production.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at code i and the value measured at code i on a line drawn between code 0 and
last code 4095.
4. Difference between the value measured at code (0x001) and the ideal value.
5. Difference between the ideal transfer-function slope and the measured slope computed from code 0x000 and 0xFFF when
the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is -0.5 dBFS with Fsampling = 1 MHz.

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5.3.24 Voltage reference buffer characteristics

Table 116. VREFBUF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VRS = 000 1.8 -

VRS = 001 2.1 -
Normal mode 3.6
VRS = 010 2.4 -

Analog supply VRS = 011 2.8 -

VDDA
voltage VRS = 000 - 1.8

Degraded VRS = 001 - 2.1

1.62
mode(2) VRS = 010 - 2.4
VRS = 011 - 2.8
VRS = 000 1.496 1.5 1.504
Normal mode at
VRS = 001 1.795 1.8 1.805 V
VDDA = 3 V,
TJ = 30 °C, VRS = 010 2.042 2.048 2.054
Iload = 10 µA
VRS = 011 2.493 2.5 2.507

VREFBUF Min (VDDA - 0.15

Voltage reference VRS = 000 - 1.504
_OUT
;1.496)
(3) buffer output
Min (VDDA - 0.15
VRS = 001 - 1.805
Degraded ;1.795)
mode(2) Min (VDDA - 0.15
VRS = 010 - 2.054
;2.042)
Min (VDDA - 0.15
VRS = 011 - 2.507
;2.493)
TRIM Trim step - 0.1 0.175 0.25 %
CL Load capacitor(4) - 0.5 1.10 1.50 µF
CL equivalent serial
esr - - - 2 Ω
resistor
Iload Static load current - - - 4 mA
RPD Pull-down resistance - - - 400 Ω
VDDAmin ≤ VDDA ≤ 3.6 V,
Iline_reg Line regulation Normal mode, ±0.016 ±0.033 ±0.053 %
500 µA ≤ Iload ≤ 4 mA
Normal mode, ppm/
Iload_reg Load regulation(5) - 50 400
500 μA ≤ Iload ≤ 4 mA mA
Temperature Tcoeff_vrefint ppm/
TCoeff –40 °C < TJ < +130 °C - -
coefficient + 50 °C

Power supply DC - 65 -
PSRR dB
rejection 100 kHz - 30 -

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Table 116. VREFBUF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

CL = 0.5 µF - 110 200

tSTART Startup time CL = 1.1 µF - 240 350 µs
CL = 1.5 µF - 320 500
Control of DC
current drive on
IINRUSH VREFBUF_ - - 8 11 mA
OUT during startup
phase (6)
Iload = 0 µA - 14 18
IDDA VREFBUF
(VREFBUF consumption from Iload = 500 µA - 16 20 µA
) VDDA
Iload = 4 mA - 42 50
1. Specified by design and not tested in production, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not accurately maintain the output voltage (VDDA - drop voltage).
3. Evaluated by characterization. Not tested in production.
4. The capacitive load must include a 100 nF capacitor in order to cut off the high-frequency noise.
5. The load regulation value only takes into account the die and package resistance. The parasitic resistance on PCB
degrades this value.
6. To correctly control the VREFBUF inrush current during startup phase and scaling change, the VDDA voltage must be in the
range of [1.8 V-3.6 V], [2.1 V-3.6 V], [2.4 V-3.6 V] and [2.8 V-3.6 V] for VRS = 000, 001, 010 and 011 respectively.

Figure 40. VREFBUF_OUT versus temperature (VRS = 000)

MSv69705V1

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Figure 41. VREFBUF_OUT versus temperature (VRS = 001)

MSv69706V1

Figure 42. VREFBUF_OUT versus temperature (VRS = 010)

MSv69707V1

Figure 43. VREFBUF_OUT versus temperature (VRS = 011)

MSv69708V1

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5.3.25 Comparator characteristics

Table 117. COMP characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage for

VDDA - 1.58 - 3.6
COMP ON
Comparator input voltage V
VIN - 0 - VDDA
range
VREFINT(3) Scaler input voltage - (3)

VSC Scaler offset voltage - - ±5 ±10 mV

(4)
Scaler static consumption Scaler bridge disabled - 0.20 0.25
IDDA(SCALER) µA
from VDDA Scaler bridge enabled(5) - 0.7 1
tSTART_SCALER Scaler startup time - - 130 220
High-speed mode - - 5
Comparator startup time to µs
tSTART reach propagation delay Medium mode - - 25
specification
Ultra-low-power mode - - 80
High-speed mode - 40 100 ns
Propagation delay for
tD(6) 200 mV step with 100 mV Medium mode - 0.5 1
overdrive µs
Ultra-low-power mode - 2 7
Voffset Comparator offset error Full common mode range - ±5 ±20
No hysteresis - 0 -
Low hysteresis - 15 - mV
Vhys Comparator hysteresis
Medium hysteresis - 30 -
High hysteresis - 45 -
Comparator input bias (7)
Ibias - nA
current
High-speed mode, static - 48 90
High-speed mode, with 50 kHz,
- 50 -
±100 mV overdrive square signal
Medium mode, static - 3 6
Comparator consumption
IDDA(COMP) Medium mode, with 50 kHz, ±100 mV µA
from VDDA - 3.75 -
overdrive square signal
Ultra-low-power mode, static - 0.3 1
Ultra-low-power mode, with 50 kHz,
- 0.65
±100 mV overdrive square signal
1. Specified by design and not tested in production, unless otherwise specified.
2. The input capacitance is negligible compared to the I/O capacitance.
3. Refer to Table 36: Embedded internal voltage reference.
4. No VREFINT division, includes only buffer consumption.
5. VREFINT division, includes resistor bridge and buffer consumption.

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6. Evaluated by characterization. Not tested in production.

7. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 94: I/O static characteristics.

5.3.26 Operational amplifiers characteristics

Table 118. OPAMP characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage

VDDA - 1.60 - 3.6
range for OPAMP ON
V
Common mode input
CMIR - 0 - VDDA
range
TJ = 30 °C, no load on output,
- - ±3
Normal mode
TJ= 30 °C, no load on output,
- - ±3
Low-power mode
VIOFFSET Input offset voltage mV
All voltages and temperature,
- - ±7
Normal mode
All voltages and temperature,
- - ±11.5
Low-power mode

Input offset voltage drift Normal mode - ±7 -

∆VIOFFSET μV/°C
over temperature Low-power mode - ±15 -
Offset trim step at low
TRIMOFFSETP
common input voltage - - 1.05 1.25
TRIMLPOFFSETP
(0.1 × VDDA)
mV
Offset trim step at high
TRIMOFFSETN
common input voltage - - 1.05 1.25
TRIMLPOFFSETN
(0.9 × VDDA)
Normal mode - - 500
ILOAD Drive current
Low-power mode - - 100
μA
Normal mode - - 450
ILOAD_PGA Drive current in PGA mode
Low-power mode - - 50

Resistive load (connected Normal mode 3.9 - -

RLOAD kΩ
to VSSA or VDDA) Low-power mode 20 - -
CLOAD Capacitive load - - - 50 pF

Common mode rejection Normal mode - 79 -

CMRR dB
ratio Low-power mode - 69 -
CLOAD ≤ 50 pF,
Normal
RLOAD ≥ 3.9 kΩ(3), 35 75 -
mode
Power supply rejection DC
PSRR dB
ratio C ≤ 50 pF,
Low-power LOAD
RLOAD ≥ 20 kΩ(3), 32 69 -
mode
DC

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Table 118. OPAMP characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Normal mode 0.4 2 3.1

GBW Gain bandwidth product MHz
Low-power mode 0.23 0.5 0.76
Normal
Standard speed 0.5 1 3.2
mode
mode
Low-power (OPAHSM = 0)
0.14 0.25 0.75
Slew rate (from 10% and mode
(3)
SR V/µs
90% of output voltage) Normal
1.4 3.2 5.6
mode High speed mode
Low-power (OPAHSM = 1)
0.38 0.82 1.5
mode
Normal mode 72 105 -
AO Open loop gain dB
Low-power mode 77 106 -
Normal mode 54 67 -
φm Phase margin °
Low-power mode 54 65 -
Normal mode - 9 -
GM Gain margin dB
Low-power mode - 17 -
Normal VDDA
ILOAD max or - -
mode - 100
VOHSAT(3) High saturation voltage RLOAD min,
Low-power Input at V VDDA
DDA - -
mode - 50
mV
Normal
ILOAD max or - - 100
mode
VOLSAT(3) Low saturation voltage RLOAD min,
Low-power Input at 0 V
- - 50
mode
CLOAD ≤ 50 pF,
Normal
RLOAD ≥ 3.9 kΩ, - 4 10
mode
Wakeup time from follower config.
tWAKEUP µs
OFF state C ≤ 50 pF,
Low-power LOAD
RLOAD ≥ 20kΩ, - 20 40
mode
follower config.
General purpose input (all (4)
- -
packages except UFBGA)
TJ ≤ 75 °C - - 7
Ibias OPAMP input bias current Dedicated nA
input TJ ≤ 85 °C - - 9
(UFBGA TJ ≤ 105 °C - - 18
only)
TJ ≤ 125 °C - - 25

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Table 118. OPAMP characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

PGA_GAIN[1:0] = 00 - 2 -
PGA_GAIN[1:0] = 01 - 4 -
PGA gain(3) Non-inverting gain value %
PGA_GAIN[1:0] = 10 - 8 -
PGA_GAIN[1:0] = 11 - 16 -
PGA gain = 2 - 80/80 -
R2/R1 internal resistance PGA gain = 4 - 120/40 - kΩ/
Rnetwork values in non-inverting
PGA gain = 8 - 140/20 - kΩ
PGA mode(5)
PGA gain = 16 - 150/10 -
Resistance variation
Delta R - -18 - 18
(R1 or R2) %
PGA gain error PGA gain error - -1 - 1
PGA gain = 2 - GBW/2 -

PGA bandwidth for PGA gain = 4 - GBW/4 -

PGA BW MHz
different non inverting gain PGA gain = 8 - GBW/8 -
PGA gain = 16 - GBW/16 -
At 1 kHz,
Normal
output loaded with - 220 -
mode
3.9 kΩ
At 1 kHz,
Low-power
output loaded with - 350 - nV
en Voltage noise density mode
20 kΩ /√Hz
Normal At 10 kHz, output
- 190 -
mode loaded with 3.9 kΩ
Low-power at 10 kHz, output
- 210 -
mode loaded with 20 kΩ
Normal
no load, quiescent - 130 190
mode
mode,
Low-power standard speed
- 40 58
OPAMP consumption from mode
IDDA(OPAMP) µA
VDDA Normal
no load, quiescent - 138 205
mode
mode,
Low-power high-speed mode
- 42 60
mode
1. Specified by design and not tested in production, unless otherwise specified.
2. OPA_RANGE must be set to 1 in OPAMP1_CSR.
3. Evaluated by characterization. Not tested in production.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 94: I/O static characteristics.
5. R2 is the internal resistance between the OPAMP output and the OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.

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Figure 44. OPAMP voltage noise density, normal mode, RLOAD = 3.9 kΩ

Figure 45. OPAMP voltage noise density, low-power mode, RLOAD = 20 kΩ

5.3.27 Temperature and Backup domain supply thresholds monitoring

The temperature and Backup domain supply monitoring characteristics are provided in the
technical note STM32U585xx MCUs for PCI products (TN1333). A NDA is required.

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5.3.28 ADF/MDF characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fAHB frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.

Table 119. ADF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Input clock frequency via

fCCKI ADF_CCK[1:0] pin, in SLAVE - - 25
SPI mode
Output clock frequency in
fCCKO - - 25
MASTER SPI mode 1.71 ≤ VDD ≤ 3.6 V MHz
Output clock frequency in
fCCKOLF - - 5
LF_MASTER SPI mode
Input symbol rate in
fSYMB - - 20
Manchester mode
tHCCKI ADF_CCK[1:0] input clock 2×
In SLAVE SPI mode - -
tLCCKI high and low time Tadf_proc_ck(2)
tHCCKO ADF_CCK[1:0] output clock 2×
In MASTER SPI mode - -
tLCCKO high and low time Tadf_proc_ck
tHCCKOLF ADF_CCK[1:0] output clock
In LF_MASTER SPI mode Tadf_proc_ck - -
tLCCKOLF high and low time
Data setup time with respect In SLAVE SPI mode:
tSUCCKI 4.5 - - ns
to ADF_CCK[1:0] input ADF_CCK[1:0] configured in
Data hold time with respect to input, measured on rising and
tHDCCKI falling edge 1 - -
ADF_CCK[1:0] input
Data setup time with respect In MASTER SPI mode:
tSUCCKO 5.5 - -
to ADF_CCK[1:0] output ADF_CCK[1:0] configured in
Data hold time with respect to output, measured on rising and
tHDCCKO falling edge 0 - -
ADF_CCK[1:0] output
Data setup time with respect
In LF_MASTER SPI mode:
tSUCCKOLF 19.5 - -
to ADF_CCK[1:0] output ADF_CCK[1:0] configured in
ns
Data hold time with respect to output, measured on rising and
tHDCCKOLF falling edge 0 - -
ADF_CCK[1:0] output
1. Evaluated by characterization. Not tested in production.
2. Tadf_proc_ck is the period of the ADF processing clock.

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Figure 46. ADF timing diagram

fCCKI, fCCKO, fCCKOLF
tSUCCKI tHDCCKI tSUCCKI tHDCCKI
tSUCCKO tHDCCKO tSUCCKO tHDCCKO tLCCKI, tLCCKO, tHCCKI, tHCCKO,
tSUCCKOLF tHDCCKOLF tSUCCKOLF tHDCCKOLF tLCCKOLF tHCCKOLF

ADF_CCK (I/O)

ADF_SDIx (I)
MSv69124V1

Table 120. MDF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Input clock frequency via

fCKI MDF_CKIx pin, in - - 25
SLAVE SPI mode
Input clock frequency via
fCCKI MDF_CCK[1:0] pin, in - - 25
SLAVE SPI mode
1.71 ≤ VDD ≤ 3.6 V MHz
Output clock frequency in
fCCKO - - 25
MASTER SPI mode
Output clock frequency in
fCCKOLF - - 5
LF_MASTER SPI mode
Input symbol rate in
fSYMB - - 20
Manchester mode
MDF_CKIx input clock high 2×
tHCKI tLCKI In SLAVE SPI mode - -
and low time Tmdf_proc_ck(2)
tHCCKI MDF_CCK[1:0] input clock 2×
In SLAVE SPI mode - -
tLCCKI high and low time Tmdf_proc_ck
ns
tHCCKO MDF_CCK[1:0] output clock 2×
In MASTER SPI mode - -
tLCCKO high and low time Tmdf_proc_ck
tHCCKOLF MDF_CCK[1:0] output clock
In LF_MASTER SPI mode Tmdf_proc_ck - -
tLCCKOLF high and low time

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Table 120. MDF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Data setup time with respect

tSUCKI 1.5 - -
to MDF_CKIx input In SLAVE SPI mode, measured
Data hold time with respect on rising and falling edge
tHDCKI 0 - -
to MDF_CKIx input
Data setup time with respect In SLAVE SPI mode:
tSUCCKI 1.5 - -
to MDF_CCK[1:0] input MDF_CCK[1:0] configured in
Data hold time with respect input, measured on rising and
tHDCCKI falling edge 0.5 - -
to MDF_CCK[1:0] input
ns
Data setup time with respect In MASTER SPI mode:
tSUCCKO 3.5 - -
to MDF_CCK[1:0] output MDF_CCK[1:0] configured in
Data hold time with respect output, measured on rising and
tHDCCKO falling edge 1.5 - -
to MDF_CCK[1:0] output
Data setup time with respect In LF_MASTER SPI mode,
tSUCCKOLF 19.5 - -
to MDF_CCK[1:0] output MDF_CCK[1:0] configured in
Data hold time with respect output, measured on rising and
tHDCCKOLF falling edge 0 - -
to MDF_CCK[1:0] output
1. Evaluated by characterization. Not tested in production.
2. Tmdf_proc_ck is the period of the MDF processing clock.

Figure 47. MDF timing diagram

tSUCKI tHDCKI tSUCKI tHDCKI
fCKI, fCCKI, FCCKO, fCCKOLF
tSUCCKI tHDCCKI tSUCCKI tHDCCKI
tSUCCKO tHDCCKO tSUCCKO tHDCCKO tLCKI, tLCCKI, tHCKI, tHCCKI,
tSUCCKOLF tHDCCKOLF tSUCCKOLF tHDCCKOLF tLCCKO tHCCKO

MDF_CKIx (I)
MDF_CCK (I/O)

MDF_SDIx (I)
MSv69125V1

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5.3.29 DCMI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 33, with the following configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1

Table 121. DCMI characteristics(1)

Symbol Parameter Min Max Unit

- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel clock input - 64 MHz
DPIXEL Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 2 -
th(DATA) Data hold time 1 -
tsu(HSYNC) ns
DCMI_HSYNC and DCMI_VSYNC input setup times 2 -
tsu(VSYNC)
th(HSYNC)
DCMI_HSYNC and DCMI_VSYNC input hold times 1 -
th(VSYNC)
1. Evaluated by characterization. Not tested in production.

Figure 48. DCMI timing diagram

1/DCMI_PIXCLK

DCMI_PIXCLK

tsu(HSYNC) th(HSYNC)

DCMI_HSYNC

tsu(VSYNC) th(HSYNC)

DCMI_VSYNC
tsu(DATA) th(DATA)

DATA[0:13]

MS32414V2

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5.3.30 PSSI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 33, with the following configuration:
• PSSI_PDCK polarity: falling
• PSSI_RDY and PSSI_DE polarity: low
• Bus width: 16 lines
• Data width: 32 bits
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1

Table 122. PSSI transmit characteristics(1)

Symbol Parameter Conditions Min Max Unit

- Frequency ratio DCMI_PDCK/fHCLK - - 0.4 -

2.7 V ≤ VDD ≤ 3.6 V - 64(2)
PSSI_PDCK PSSI clock input MHz
1.71 V ≤ VDD ≤ 3.6 V - 47(2)
DPIXEL PSSI clock input duty cycle - 30 70 %
2.7 V ≤ VDD ≤ 3.6 V - 14
tOV(DATA) Data output valid time
1.71 V ≤ VDD ≤ 3.6 V - 21
tOH(DATA) Data output hold time 7 -
tOV(DE) DE output valid time 1.71 V ≤ VDD ≤ 3.6 V - 12.5 ns
tOH(DE) DE output hold time 6 -
tSU(RDY) RDY input setup time 0 -
1.71 V ≤ VDD ≤ 3.6 V
tH(RDY) RDY input hold time 0 -
1. Evaluated by characterization. Not tested in production.
2. This maximal frequency does not consider receiver setup and hold timings.

Table 123. PSSI receive characteristics(1)

Symbol Parameter Conditions Min Max Unit

- Frequency ratio DCMI_PDCK/fHCLK - - 0.4 -

PSSI_PDCK PSSI clock input 1.71 V ≤ VDD ≤ 3.6 V - 64 MHz
DPIXEL PSSI clock input duty cycle - 30 70 %

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Table 123. PSSI receive characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

tSU(DATA) Data input setup time 2 -

tH(DATA) Data input hold time 1.5 -
tSU(DE) DE input setup time 0.5 -
1.71 V ≤ VDD ≤ 3.6 V ns
tH(DE) DE input hold time 2 -
tOV(RDY) RDY output valid time - 12
tOH(RDY) RDY output hold time 6 -
1. Evaluated by characterization. Not tested in production.

Figure 49. PSSI receive timing diagram

tc(PDCK)

tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK

CKPOL=0
(input)

CKPOL=1

ts(DATA)
th(DATA)
PSSI D[15:0]
Invalid data IN Valid data IN Invalid data IN
(input)
ts(DE)
th(DE)
DEPOL=0
PSSI_DE
(input)

DEPOL=1

tv(RDY) tho(RDY)
PSSI_RDY

RDYPOL=0
(output)

RDYPOL=1

MSv63436V1

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Figure 50. PSSI transmit timing diagram

tc(PDCK)

tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK

CKPOL=0
(input)

CKPOL=1

tv(DATA) tho(DATA)
PSSI D[15:0]
Invalid data OUT Valid data OUT Invalid data OUT
(output)

tv(DE) tho(DE)
DEPOL=0
PSSI_DE
(output)

DEPOL=1

ts(RDY) th(RDY)
PSSI_RDY

RDYPOL=0
(input)

RDYPOL=1

MSv63437V1

5.3.31 Timer characteristics

The parameters given in the following tables are specified by design, not tested in
production.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 124. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 160 MHz 6.25 - ns

Timer external clock frequency on - 0 fTIMxCLK/2

fEXT MHz
CH1 to CH4 fTIMxCLK = 160 MHz 0 80
TIMx (except TIM2/3/4/5) - 16
ResTIM Timer resolution bit
TIM2/3/4/5 - 32
- 1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period
fTIMxCLK = 160 MHz 0.007 409.6 µs

Maximum possible count with - - 65536 × 65536 tTIMxCLK

tMAX_COUNT
32-bit counter fTIMxCLK = 160 MHz - 26.843 s
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

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Table 125. IWDG min/max timeout period at 32 kHz (LSI)(1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF Unit

/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock, so that there is always a full
RC period of uncertainty.

Table 126. WWDG min/max timeout value at 160 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit

1 0 0.025 1.638
2 1 0.051 3.276
4 2 0.102 6.553
8 3 0.204 13.107
ms
16 4 0.409 26.214
32 5 0.819 52.428
46 6 1.177 75.366
128 7 3.276 209.715

5.3.32 FSMC characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
characteristics.

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Asynchronous waveforms and timings

Figure 51 to Figure 54 represent asynchronous waveforms and Table 127 to Table 134
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
• AddressSetupTime (ADDSET) = 0x1
• AddressHoldTime (ADDHLD) = 0x1
• ByteLaneSetup (NBLSET) = 0x1
• DataSetupTime (DATAST) = 0x1 (except for asynchronous NWAIT mode,
DataSetupTime = 0x5)
• DataHoldTime (DATAHLD) = 0x1 (0x0 for write operation)
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all timing tables, the THCLK is the HCLK clock period.

Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

tw(NE)

FMC_NE

tv(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

tv(A_NE) t h(A_NOE)

FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)

FMC_NBL[1:0]

t h(Data_NE)

t su(Data_NOE) th(Data_NOE)

t su(Data_NE)

FMC_D[15:0] Data

t v(NADV_NE)

tw(NADV)

FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32753V1

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Table 127. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3 × tHCLK - 1 3 × tHCLK + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 5
tw(NOE) FMC_NOE low time 2 × tHCLK - 1 2 × tHCLK + 1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time THCLK -
tv(A_NE) FMC_NEx low to FMC_A valid - 1.5
th(A_NOE) Address hold time after FMC_NOE high 2 × tHCLK - 1 -
ns
tsu(Data_NE) Data to FMC_NEx high setup time tHCLK + 15 -
tsu(Data_NOE) Data to FMC_NOEx high setup time 15 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 1.5
tw(NADV) FMC_NADV low time - THCLK + 1
1. Evaluated by characterization. Not tested in production.

Table 128. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8 × tHCLK - 1 8 × tHCLK + 1

tw(NOE) FMC_NWE low time 7 × tHCLK - 1 7 × tHCLK + 1
tw(NWAIT) FMC_NWAIT(2) low time tHCLK - ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 × tHCLK + 9.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 × tHCLK + 10 -
1. Evaluated by characterization. Not tested in production.
2. NWAIT pulse is equal to one HCLK cycle.

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Figure 52. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)

FMC_NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)

FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)

FMC_D[15:0] Data
t v(NADV_NE)

tw(NADV)
FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32754V1

Table 129. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3 × tHCLK - 1 3 × tHCLK + 1

tv(NWE_NE) FMC_NEx low to FMC_NWE low tHCLK - 1 tHCLK + 1
tw(NWE) FMC_NWE low time tHCLK - 0.5 tHCLK + 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time tHCLK -
tv(A_NE) FMC_NEx low to FMC_A valid - 1
th(A_NWE) Address hold time after FMC_NWE high tHCLK - 0.5 -
ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high tHCLK - 0.5 -
tv(Data_NE) FMC_NEx low to Data valid - tHCLK + 2
th(Data_NWE) Data hold time after FMC_NWE high tHCLK -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 2
tw(NADV) FMC_NADV low time - tHCLK + 1
1. Evaluated by characterization. Not tested in production.

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Table 130. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8 × tHCLK - 1 8 × tHCLK + 1

tw(NWE) FMC_NWE low time 6 × tHCLK - 1 6 × tHCLK + 1
ns
(2)
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 × tHCLK + 13 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 × tHCLK + 12 -
1. Evaluated by characterization. Not tested in production.
2. NWAIT pulse is equal to one HCLK cycle.

Figure 53. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)

FMC_ NE
tv(NOE_NE) t h(NE_NOE)

FMC_NOE

t w(NOE)

FMC_NWE

tv(A_NE) th(A_NOE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)
tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32755V1

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Table 131. Asynchronous multiplexed PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3 × tHCLK - 1 3 × tHCLK + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 5
tw(NOE) FMC_NOE low time 2 × tHCLK - 0.5 2 × tHCLK + 0.5
th(NE_NOE) FMC_NOE high to FMC_NE high hold time tHCLK -
tv(A_NE) FMC_NEx low to FMC_A valid - 1.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1.5 ns
tw(NADV) FMC_NADV low time tHCLK - 0.5 tHCLK + 1
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) tHCLK - 4 -
th(A_NOE) Address hold time after FMC_NOE high tHCLK - 1 -
tsu(Data_NE) Data to FMC_NEx high setup time tHCLK + 15 -
tsu(Data_NOE) Data to FMC_NOE high setup time 15 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
ns
th(Data_NOE) Data hold time after FMC_NOE high 0 -
1. Evaluated by characterization. Not tested in production.

Table 132. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8 × tHCLK - 1 8 × tHCLK + 1

tw(NOE) FMC_NOE low time 7 × tHCLK - 1 7 × tHCLK + 1
ns
tsu(NWAIT_NE) FMC_NWAIT(2) valid before FMC_NEx high 4 × tHCLK + 9.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 3 × tHCLK + 10 -
1. Evaluated by characterization. Not tested in production.
2. NWAIT pulse is equal to one HCLK cycle.

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Figure 54. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)

FMC_ NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NWE)

FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)

tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32756V1

Table 133. Asynchronous multiplexed PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3 × tHCLK - 1 3 × tHCLK + 1

tv(NWE_NE) FMC_NEx low to FMC_NWE low tHCLK - 1 tHCLK
tw(NWE) FMC_NWE low time 2 × tHCLK - 0.5 2 × tHCLK + 1
th(NE_NWE) FMC_NWE high to FMC_NE high hold time tHCLK -
tv(A_NE) FMC_NEx low to FMC_A valid - 1
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 2
tw(NADV) FMC_NADV low time tHCLK - 0.5 tHCLK + 1 ns
th(AD_NADV) FMC_AD(adress) valid hold time after FMC_NADV high) tHCLK - 4.5 -
th(A_NWE) Address hold time after FMC_NWE high tHCLK - 0.5 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high tHCLK - 0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) FMC_NADV high to Data valid - tHCLK + 2
th(Data_NWE) Data hold time after FMC_NWE high tHCLK -
1. Evaluated by characterization. Not tested in production.

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Table 134. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8 × tHCLK - 1 8 × tHCLK + 1

tw(NWE) FMC_NWE low time 6 × tHCLK - 1 6 × tHCLK + 1
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 × tHCLK + 13 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 × tHCLK + 12 -
1. Evaluated by characterization. Not tested in production.

Synchronous waveforms and timings

Figure 55 to Figure 58 represent synchronous waveforms and Table 135 to Table 138
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period.
• Maximum FMC_CLK = 80 MHz for 2.7 V ≤ VDD ≤ 3.6 V, with CL = 15pF and
with CL = 20 pF
• Maximum FMC_CLK = 80 MHz for 1.71 V ≤ VDD ≤ 1.9 V with CL = 15pF and
with CL = 20 pF

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Figure 55. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)

FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32757V1

Table 135. Synchronous multiplexed NOR/PSRAM read timings(1)(2)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2 × tHCLK - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 1
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x = 0..2) tHCLK - 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16..25) - 2.5 ns
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16..25) tHCLK - 0.5 -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tHCLK + 1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -

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Table 135. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued)

Symbol Parameter Min Max Unit

tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3 -

th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 4 -
ns
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 1 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -
1. Evaluated by characterization. Not tested in production.
2. Clock ratio R = (HCLK period /FMC_CLK period).

Figure 56. Synchronous multiplexed PSRAM write timings

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06Y9

Table 136. Synchronous multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period, 2.7 V ≤ VDD ≤ 3.6 V 2 × tHCLK - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 2
ns
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0..2) tHCLK + 1.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2

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Table 136. Synchronous multiplexed PSRAM write timings(1) (continued)

Symbol Parameter Min Max Unit

td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -

td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16..25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16..25) tHCLK -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2.5
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high tHCLK + 1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2
ns
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high tHCLK + 0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -
1. Evaluated by characterization. Not tested in production.

Figure 57. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK)

FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)

FMC_D[15:0] D1 D2

tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

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Table 137. Synchronous non-multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period tHCLK - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 1
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0…2) tHCLK - 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 0…25) - 2.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 0…25) tHCLK - 0.5 - ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tHCLK + 1 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 3 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 4 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 1 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -
1. Evaluated by characterization. Not tested in production.

Figure 58. Synchronous non-multiplexed PSRAM write timings

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WG &/./1$'9/ WG &/./1$'9+

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WK &/.+1:$,79

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06Y9

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Table 138. Synchronous non-multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2 × tHCLK - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 3
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0..2) tHCLK + 1.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16..25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16..25) tHCLK -
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2.5
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high tHCLK + 1 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high tHCLK + 0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -
1. Evaluated by characterization. Not tested in production.

NAND controller waveforms and timings

Figure 59 to Figure 62 represent synchronous waveforms, and Table 139/Table 140 provide
the corresponding timings. The results shown in these tables are obtained with the following
FMC configuration:
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
In all timing tables, the THCLK is the HCLK clock period.

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Figure 59. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)

FMC_NWE

td(NCE-NOE) th(NOE-ALE)

FMC_NOE (NRE)

tsu(D-NOE) th(NOE-D)

FMC_D[15:0]
MSv38003V1

Figure 60. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE) th(NWE-ALE)

FMC_NWE

FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)

FMC_D[15:0]
MSv38004V1

Figure 61. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)
FMC_NOE

tsu(D-NOE) th(NOE-D)

FMC_D[15:0]
MSv38005V1

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Figure 62. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE) tw(NWE) th(NOE-ALE)

FMC_NWE

FMC_NOE

td(D-NWE)

tv(NWE-D) th(NWE-D)
FMC_D[15:0]

MSv38006V1

Table 139. Switching characteristics for NAND Flash read cycles(1)

Symbol Parameter Min Max Unit

tw(N0E) FMC_NOE low width 4 × tHCLK - 0.5 4 × tHCLK + 0.5

tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 10 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3 × tHCLK + 0.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4 × tHCLK - 1 -
1. Evaluated by characterization. Not tested in production.

Table 140. Switching characteristics for NAND Flash write cycles(1)

Symbol Parameter Min Max Unit

tw(NWE) FMC_NWE low width 4 × tHCLK - 0.5 4 × tHCLK + 0.5

tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2 × tHCLK + 1 -
ns
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5 × tHCLK - 5 -
td(ALE_NWE) FMC_ALE valid before FMC_NWE low - 3 × tHCLK + 0.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2 × tHCLK - 0.5 -
1. Evaluated by characterization. Not tested in production.

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5.3.33 OCTOSPI characteristics

Unless otherwise specified, the parameters given in Table 141 toTable 143 are derived from
tests performed under the ambient temperature, fAHB frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Delay block enabled for DTR (with DQS)/HyperBus
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1 unless otherwise specified
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.

Table 141. OCTOSPI characteristics in SDR mode(1)(2)(3)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V ≤ VDD ≤ 3.6 V

Voltage range 1 - - 93
CL = 15 pF
2.7 V ≤ VDD ≤ 3.6 V
OCTOSPI clock
f(CLK) Voltage range1 - - 100 MHz
frequency
CL = 15 pF
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 4 - - 24
CL = 15 pF
tw(CLKH) OCTOSPI clock high t(CLK)/2 - 0.5 - t(CLK)/2
PRESCALER[7:0] = n
and low time
tw(CLKL) (even division) (n = 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2

(n/2) × t(CLK) (n/2) × t(CLK)

tw(CLKH) OCTOSPI clock high -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1)
and low time
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
t (odd division) -
w(CLKL) /(n+1) - 0.5 /(n+1)
Voltage range 1 2.75 - -
ts(IN) Data input setup time ns
Voltage range 4 3 - -
Voltage range 1 0.5 - -
th(IN) Data input hold time
Voltage range 4 1 - -
Voltage range 1 - 0.5 1
tv(OUT) Data output valid time
Voltage range 4 - 1.5 2.5
Voltage range 1 0.5 - -
th(OUT) Data output hold time
Voltage range 4 -0.25 - -
1. Evaluated by characterization. Not tested in production.
2. Measured values in this table apply to Octo- and Quad-SPI data modes.
3. Delay block bypassed.

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Table 142. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3)

Sym
Parameter Conditions Min Typ Max Unit
bol

1.71 V ≤ VDD ≤ 3.6 V Voltage

- - 93(4)
range 1, CL = 15 pF
OCTOSPI clock 2.7 V ≤ VDD ≤ 3.6 V
f(CLK) - - 100(4) MHz
frequency Voltage range1, CL = 15 pF
1.71 V ≤ VDD ≤ 3.6 V
- - 24(4)
Voltage range 4, CL = 15 pF
tw(CLKH) OCTOSPI clock t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
PRESCALER[7:0] = n
high and low time
tw(CLKL) (even division) (n = 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5

(n/2) × t(CLK) (n/2) × t(CLK)

tw(CLKH) OCTOSPI clock -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1) + 0.5
high and low time
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
t (odd division) -
w(CLKL) /(n+1) - 0.5 /(n+1) + 0.5

tsr(IN) Data input setup Voltage range 1 3.25 - -

tsf(IN) time Voltage range 4 3.75 - -

thr(IN) Data input hold Voltage range 1 1 - -

ns
thf(IN) time Voltage range 4 1.5 - -

Data output valid Voltage range 1 - 6 9.25

tvr(OUT) time, DHQC = 0 Voltage range 4 - 13.25 19.75
tvf(OUT)
Data output valid Voltage range 1 t(CLK)/4
- t(CLK)/4 + 1.5
time, DHQC = 1 All prescaler values (except 0) + 0.75

Data output hold Voltage range 1 4 - -

thr(OUT) time DHQC = 0 Voltage range 4 8 - -
thf(OUT)
Data output hold Voltage range 1
t(CLK)/4 - 0.5 - -
time DHQC = 1 All prescaler values (except 0)
1. Evaluated by characterization. Not tested in production.
2. Measured values in this table apply to Octo- and Quad-SPI data modes.
3. Delay block bypassed.
4. Activating DHQC is mandatory to reach this frequency.

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Table 143. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V ≤ VDD ≤ 3.6 V

Voltage range 1 - - 93(3)(4)
CL = 15 pF
2.7 V ≤ VDD ≤ 3.6 V
OCTOSPI clock
f(CLK) Voltage range1 - - 100(3)(4) MHz
frequency
CL = 15 pF
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 4 - - 24(4)
CL = 15 pF
tw(CLKH) OCTOSPI clock t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
PRESCALER[7:0] = n
high and low time
tw(CLKL) (n = 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
(even division)
(n/2) × t(CLK) (n/2) × t(CLK)
tw(CLKH) OCTOSPI clock -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1) + 0.5
high and low time ns
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
tw(CLKL) (odd division) -
/(n+1) - 0.5 /(n+1) + 0.5
tv(CLK) Clock valid time - - - t(CLK) + 2
th(CLK) Clock hold time - t(CLK)/2 - 0.5 - -
CLK, NCLK
VODr(CLK)
(5) crossing level on VDD = 1.8 V 975 - 1120
CLK rising edge
mV
CLK, NCLK
VODf(CLK)
(5) crossing level on VDD = 1.8 V 845 - 990
CLK falling edge
Chip select high
tw(CS) - 3 × t(CLK) - -
time
Data input valid
tv(DQ) - 0 - -
time
Data strobe input
tv(DS) 0 - -
valid time
Data strobe input
th(DS) - 0 - -
hold time ns
Data strobe output
tv(RWDS) - - - 3 × t(CLK)
valid time

tsr(DQ) Data input setup Voltage range 1 -0.5 - t(CLK)/2 - 1.5(6)

tsf(DQ) time Voltage range 4 -0.25 - t(CLK)/2 - 1.75(6)

thr(DQ) Data input hold Voltage range 1 1.5 - -

thf(DQ) time Voltage range 4 1.75 - -

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Table 143. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Data output valid Voltage range 1 - 6 9.5

time DHQC = 0 Voltage range 4 - 13 19.5
tvr(OUT)
tvf(OUT) Voltage range 1
Data output valid
All prescaler values - t(CLK)/4 + 0.5 t(CLK)/4 + 1.25
time DHQC = 1
(except 0)
ns
thr(OUT) Data output hold Voltage range 1 4 - -
thf(OUT) time DHQC = 0 Voltage range 4 7.75 - -
Voltage range 1
Data output hold
thr(OUT) All prescaler values t(CLK)/4 - 0.5 - -
time DHQC = 1
(except 0)
1. Evaluated by characterization. Not tested in production.
2. Delay block activated.
3. Maximum frequency values are given for a RWDS to DQ skew of maximum ±1.0 ns.
4. Activating DHQC is mandatory to reach this frequency.
5. Crossing results are in line with specification, except for PA3/PB5 CLK that exceed slightly the specification.
6. Data input maximum setup time does not take into account the data level switching duration.

Figure 63. OCTOSPI timing diagram - SDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V3

Figure 64. OCTOSPI timing diagram - DDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output D0 D1 D2 D3 D4 D5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input D0 D1 D2 D3 D4 D5

MSv36879V4

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Figure 65. OCTOSPI HyperBus clock

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)
tf(NCLK) t(NCLK) tw(NCLKL) tw(NCLKH) tr(NCLK)

NCLK

VOD(CLK)
CLK
MSv47732V3

Figure 66. OCTOSPI HyperBus read

tw(CS)

NCS

tv(CLK) t ACC= Initial access th(CLK)

CLK, NCLK

tv(RWDS) tv(DS) th(DS)

RWDS

tv(OUT) th(OUT) Latency count tv(DQ) ts(DQ) th(DQ)

47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

DQ[7:0] A B A B

Command address
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS. MSv47733V3

Figure 67. OCTOSPI HyperBus read with double latency

NCS

tRWR=Read/write recovery Additional latency tACC = Access

CLK, NCLK

tCKDS
RWDS High = 2x latency count
Low = 1x latency count
RWDS and data
are edge aligned
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1
A B A B

Command address Memory drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS. MSv49351V3

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Figure 68. OCTOSPI HyperBus write

tw(CS)

NCS

Read write recovery Access latency

tv(CLK) th(CLK)

CLK, NCLK

tv(RWDS) High = 2x latency count tv(OUT) th(OUT)

Low = 1x latency count
RWDS

Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)

Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B

Command address Host drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS.
MSv47734V3

5.3.34 SD/SDIO/e•MMC card host interfaces (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 144 and Table 145 are derived
from tests performed under the ambient temperature, fAHB frequency and VDD supply
voltage conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
characteristics.

Table 144. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V)(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 100(3) MHz

tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP = 52 MHz 8.5 9.5 -

CMD, D inputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes

tISU Input setup time HS - 3.5 - -

tIH Input hold time HS - 1.5 - - ns
tIDW(5) Input valid window (variable window) - 4.5 - -

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Table 144. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V)(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

CMD, D outputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes

tOV Output valid time HS - - 5.5 6

ns
tOH Output hold time HS - 4 - -

CMD, D inputs (referenced to CK) in SD default mode

tISU Input setup time SD - 3.5 - -

ns
tIH Input hold time SD - 1.5 - -

CMD, D outputs (referenced to CK) in SD default mode

tOV Output valid default time SD - - 0.5 2

ns
tOH Output hold default time SD - 0 - -
1. Evaluated by characterization. Not tested in production.
2. For SDMMC2 in SD/e.MMC DDR mode, the clock OSPEEDRy[1:0] is set to 01 while data OSPEEDRy[1:0] remains at 10.
3. With capacitive load CL = 20 pF.
4. For SD 1.8 V support, an external voltage converter is needed.
5. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Table 145. e•MMC characteristics (VDD = 1.71 V to 1.9 V)(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

All modes
- - 84
fPP Clock frequency in data transfer mode except DDR MHz
DDR mode - - 40(3)
tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP = 52 MHz 8.5 9.5 -

CMD, D inputs (referenced to CK) in e•MMC mode

tISU Input setup time HS - 2.5 - -

tIH Input hold time HS - 2 - - ns
tIDW(4) Input valid window (variable window) - 4 - -

CMD, D outputs (referenced to CK) in e•MMC mode

tOV Output valid time HS - - 10.5 13/15(5)

ns
tOH Output hold time HS - 7 - -
1. Evaluated by characterization. Not tested in production.
2. With capacitive load CL = 20 pF.
3. For DDR mode, the maximum frequency is 40 MHz and HSLV must be OFF.
4. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.
5. tOV = 13 ns for SDMMC1 and tOV = 15 ns for SDMMC2.

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Figure 69. SD high-speed mode

tC(CK)
tW(CKH) tW(CKL)

CK
tOH
tOV

D, CMD output
tIH
tISU

D, CMD input
MSv69709V1

Figure 70. SD default mode

CK
tOV tOH

D, CMD output MSv69710V1

Figure 71. SDMMC DDR mode

D input Valid data Valid data

tISU tIH tISU tIH

tW(CKH)

CK

tW(CKL)
tOV tOV
tOH tOH

D output Valid data Valid data

MSv69158V1

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5.3.35 Delay block characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
conditions summarized in Table 33.

Table 146. Delay block characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

tinit Initial delay - 900 1300 2100

ps
t∆ Unit delay - 34 41 51
1. Evaluated by characterization. Not tested in production.

5.3.36 I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bitrate up to 100 Kbit/s
• Fast-mode (Fm): with a bitrate up to 400 Kbit/s
• Fast-mode Plus (Fm+): with a bitrate up to 1 Mbit/s
The I2C timings requirements are specified by design, not tested in production, when the
I2C peripheral is properly configured (refer to the product reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low-level output-current maximum requirement. Refer to Section 5.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics.

Table 147. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 115(3) ns
1. Specified by design. Not tested in production.
2. Spikes with widths below tAF min are filtered.
3. Spikes with width above tAF max are not filtered.

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5.3.37 USART characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).

Table 148. USART characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode, 1.71 V ≤ VDD ≤ 3.6 V - - 20

USART clock Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V - - 53

fCK MHz
frequency Slave transmitter, 1.71 V ≤ VDD ≤ 3.6 V - - 28.5
Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V - - 32
tsu(NSS) NSS setup time Slave mode Tker(2) + 2 - -
th(NSS) NSS hold time Slave mode 2 - -
tw(CKH) CK high and
Master mode 1/fCK / 2 - 1 1/fCK / 2 1/fCK / 2 + 1
tw(CKL) low time

Data input Master mode 14 - -

tsu(RX)
setup time Slave mode 1 - -
th(RX) Data input hold Master mode 4 - - ns
th(RX) time Slave mode 1 - -
Slave mode, 2.7 V ≤ VDD ≤ 3.6 V - 11 17.5
tv(TX) Data output
Slave mode, 1.71 V ≤ VDD ≤ 3.6 V - 11 15.5
valid time
tv(TX) Master mode - 2.5 6.5
th(TX) Data output Slave mode 8.5 - -
th(TX) hold time Master mode 2 - -
1. Evaluated by characterization. Not tested in production.
2. Tker is the usart_ker_ck_pres clock period.

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Figure 72. USART timing diagram in master mode

1/fCK
CK output CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CK output

CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(CKH)
tsu(RX) tw(CKL)
RX
INPUT MSB IN BIT6 IN LSB IN
th(RX)
TX
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX)
MSv65386V4

Figure 73. USART timing diagram in slave mode

NSS
input
1/fCK th(NSS)
tsu(NSS) tw(CKH)

CPHA = 0
CK input

CPOL = 0
CPHA = 0
CPOL = 1

tw(CKL) tv(TX) th(TX)

TX output First bit OUT Next bits OUT Last bit OUT

th(RX)
tsu(RX)

RX input First bit IN Next bits IN Last bit IN

MSv65387V4

5.3.38 SPI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 33.
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).

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Table 149. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode, 2.7 V ≤ VDD ≤ 3.6 V, 80

- -
voltage range 1 or 50(2)
Master mode, 1.71 V ≤ VDD < 2.7 V 75
- -
voltage range 1 or 50(2)
Master mode, 1.08 V ≤ VDD ≤ 1.32 V(3) - - 15
Master transmitter mode, 80
- -
2.7 V ≤ VDD ≤ 3.6 V, voltage range 1 or 50(2)
Master transmitter mode, 75
fSCK - -
SPI clock frequency 1.71 V ≤ VDD ≤ 2.7 V, voltage range 1 or 50(2) MHz
1/tc(SCK)
Slave receiver mode,
- - 100
1.71 V ≤ VDD ≤ 3.6 V, voltage range 1
Slave mode transmitter/full duplex(4), 41.5
- -
1.71 V ≤ VDD < 2.7 V, voltage range 1 or 25.5(5)
Slave mode transmitter/full duplex(4), 38.5
- -
2.7 V ≤ VDD ≤ 3.6 V, voltage range 1 or 24(5)
1.71 V ≤ VDD ≤ 3.6 V, voltage range 4 - - 12.5
1.08 V ≤ VDD ≤ 1.32 V(3) - - 15
tsu(NSS) NSS setup time Slave mode 4 - -
th(NSS) NSS hold time Slave mode 3 - -
tw(SCKH)
SCK high and low time Master mode tSCK(6)/2 - 1 tSCK/2 tSCK/2 + 1
tw(SCKL)
tsu(MI) Master mode 4.5 - -
Data input setup time
tsu(SI) Slave mode 2.5 - -
ns
th(MI) Master mode 3 - -
Data input hold time
th(SI) Slave mode 1 - -
Data output access
ta(SO) Slave mode 9 - 34
time
Data output disable
tdis(SO) Slave mode 9 - 16
time

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Table 149. SPI characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Slave mode, 2.7 V ≤ VDD ≤ 3.6 V, 13

- 10
voltage range 1 or 20.5(5)
Slave mode, 1.71 V ≤ VDD < 2.7 V, 12
- 10
voltage range 1 or 19.5(5)
tv(SO)
Slave mode, 1.71 V ≤ VDD ≤ 3.6 V, 19.5
Data output valid time - 17
voltage range 4 or 27(5)
22.5 ns
Slave mode, 1.08 V ≤ VDD ≤ 1.32 V(3) - 21
or 30(5)
2 or 9.5(7)
tv(MO) Master mode - 1.5
or 12.5(8)
Slave mode, 1.71 V ≤ VDD ≤ 3.6 V 7 - -
th(SO)
Data output hold time Slave mode, 1.08 V ≤ VDD ≤ 1.32 V(3) 18 - -
th(MO) Master mode 0 - -
1. Evaluated by characterization. Not tested in production.
2. When using PA5, PA9, PC10, PB3, PB13.
3. The SPI is mapped on port G I/Os, that is supplied by VDDIO2 specified down to 1.08V. The SPI is tested at this value.
4. The maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) that has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
5. When using PA11, PB4, PB14.
6. tSCK = tspi_ker_ck × baudrate prescaler.
7. When using PA12.
8. When using PB15.

Figure 74. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

th(SI)
tsu(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

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Figure 75. SPI timing diagram - slave mode and CPHA = 1

NSS input

tc(SCK)

tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V1

1. Measurement points are done at 0.3 VDD and 0.7 VDD levels.

Figure 76. SPI timing diagram - master mode

High

NSS input

tc(SCK)
SCK Output

CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1

tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN

th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)

ai14136d

1. Measurement points are done at 0.3 VDD and 0.7 VDD levels.

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5.3.39 SAI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized inTable 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK, SD, FS).

Table 150. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

SAI main clock

fMCK - - 50
output
Master transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 26
Master transmitter, 1.71 V ≤ VDD ≤ 3.6 V - 18
MHz
SAI clock Master receiver, 1.71 V ≤ VDD ≤ 3.6 V - 21.5
fSCK
frequency(2) Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 30
Slave transmitter, 1.71 V ≤ VDD ≤ 3.6 V - 20.5
Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V - 50
Master mode, 2.7 V ≤ VDD ≤ 3.6 V - 16
tv(FS) FS valid time
Master mode 1.71 V ≤ VDD ≤ 3.6 V - 23
th(FS) FS hold time Master mode 7 -
tsu(FS) FS setup time Slave mode 2.5 -
th(FS) FS hold time Slave mode 1 -
tsu(SD_A_MR) Data input setup Master receiver 4 -
t time Slave receiver 3 - ns
su(SD_B_SR)

th(SD_A_MR) Data input hold Master receiver 1 -

t time Slave receiver 1 -
h(SD_B_SR)

Data output valid Slave transmitter (after enable edge), 2.7 V ≤ VDD ≤ 3.6 V - 16.5
tv(SD_B_ST)
time Slave transmitter (after enable edge), 1.71 V ≤ VDD ≤ 3.6 V - 24
Data output hold
th(SD_B_ST) Slave transmitter (after enable edge) 8 -
time

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Table 150. SAI characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

Master transmitter (after enable edge), 2.7 V ≤ VDD ≤ 3.6 V - 19

Data output valid
tv(SD_A_MT) Master transmitter (after enable edge),
time - 27.5
1.71 V ≤ VDD ≤ 3.6 V ns
Data output hold
th(SD_A_MT) Master transmitter (after enable edge) 8 -
time
1. Evaluated by characterization. Not tested in production.
2. APB clock frequency that must be at least twice SAI clock frequency.

Figure 77. SAI master timing diagram

1/fSCK

SAI_SCK_X
th(FS)

SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)

SAI_SD_X Slot n
(receive)
MS32771V1

Figure 78. SAI slave timing digram

1/fSCK

SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)

SAI_SD_X Slot n
(receive)
MS32772V1

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5.3.40 OTG_FS characteristics

Table 151. OTG_FS characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDDUSB USB transceiver operating supply voltage - 3.0(1) - 3.6 V

RPUI Embedded USB_DP pullup value during idle - 900 - 1575
RPUR Embedded USB_DP pullup value during reception - 1425 - 3090 Ω
ZDRV Output driver impedance(2) High and low driver 28 36 44
1. USB functionality is ensured down to 2.7 V, but some USB electrical characteristics are degraded in 2.7 to 3.0 V range.
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-). The matching impedance is
already included in the embedded driver.

5.3.41 UCPD characteristics

UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0
specifications.

Table 152. UCPD characteristics

Symbol Parameter Conditions Min Typ Max Unit

Sink mode only 3.0 3.3 3.6

VDD UCPD operating supply voltage V
Sink and source mode 3.135 3.3 3.465

5.3.42 JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests
performed under the ambient temperature, fHCLKx frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
characteristics.

Table 153. JTAG characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

2.7 V ≤ VDD ≤ 3.6 V - - 38

FTCK TCK clock frequency MHz
1.71 V ≤ VDD ≤ 3.6 V - - 26
tisu(TMS) TMS input setup time - 1 - -
tih(TMS) TMS input hold time - 3 - -
ns
tisu(TDI) TDI input setup time - 2 - -
tih(TDI) TDI input hold time - 1 - -

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Table 153. JTAG characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

2.7 V ≤ VDD ≤ 3.6 V - 9 13

tov(TDO) TDO output valid time
1.71 V ≤ VDD ≤ 3.6 V - 9 19 ns
toh(TDO) TDO output hold time - 7 - -
1. Evaluated by characterization. Not tested in production.

Table 154. SWD characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

2.7 V ≤ VDD ≤ 3.6 V - - 66.5

FSWCLK SWCLK clock frequency MHz
1.71 V ≤ VDD ≤ 3.6 V - - 43
tisu(SWDIO) SWDIO input setup time - 1 - -
tih(SWDIO) SWDIO input hold time - 2.5 - -
2.7 V ≤ VDD ≤ 3.6 V - 10.5 15 ns
tov(SWDIO) SWDIO output valid time
1.71 V ≤ VDD ≤ 3.6 V - 10.5 23
toh(SWDIO) SWDIO output hold time - 7.5 - -
1. Evaluated by characterization. Not tested in production.

Figure 79. JTAG timing diagram

tc(TCK)

TCK

tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS

tov(TDO) toh(TDO)

TDO

MSv40458V1

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Figure 80. SWD timing diagram

tc(SWCLK)

SWCLK

tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)

tov(SWDIO) toh(SWDIO)

SWDIO
(transmit)

MSv40459V1

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6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

6.1 UFQFPN48 package information

This UFQFPN is a 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package

Figure 81. UFQFPN48 - Outline

Pin 1 identifier
laser marking area
D

A
E E
T Seating
plane
ddd A1
e b

Detail Y
D
Y

Exposed pad
area D2
1

L
48
C 0.500x45°
pin1 corner R 0.125 typ.

E2 Detail Z

48
Z
A0B9_ME_V3

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.

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Table 155. UFQFPN48 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 82. UFQFPN48 - Recommended footprint

7.30

6.20

48 37

1 36

0.20 5.60

7.30
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80
A0B9_FP_V2

1. Dimensions are expressed in millimeters.

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Device marking for UFQFPN48

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 83. UFQFPN48 marking example (package top view)

STM32U585
Product identification(1)

CIU6

Y WW Date code

Pin 1 identifier
R Revision code

MSv64351V2

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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6.2 LQFP48 package information

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package
Note: See list of notes in the notes section.

Figure 84. LQFP48 - Outline(15)

BOTTOM VIEW

4x N/4 TIPS
aaa C A-B D
 
(2)
R1

H
R2

B
B-
D 1/4

N
O
(6)

TI
C
SE
B GAUGE PLANE
E 1/4

0.25
S
B
bbb H A-B D 4x
L

(13) (L1)
0.05 (N – 4)x e (1) (11)

A A2 C SECTION A-A

(12) ccc C
A1 ddd C A-B D
b
D (4)
(2) (5)
D1
(10) D (3) (9) (11)
N b WITH PLATING

1
2 E 1/4
(3) A 3
(6) B (3)
D 1/4 c c1
E1 E (11) (11)
(2) (4)
(5)
A A b1 BASE METAL
(Section A-A) (11)

SECTION B-B

TOP VIEW

5B_LQFP48_ME_V1

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Table 156. LQFP48 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 9.00 BSC 0.3543 BSC
(2)(5)
D1 7.00 BSC 0.2756 BSC
E(4) 9.00 BSC 0.3543 BSC
E1(2)(5) 7.00 BSC 0.2756 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 48
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
bbb(1)(7) 0.20 0.0079
(1)(7)
ccc 0.08 0.0031
(1)(7)
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 85. LQFP48 - Recommended footprint

0.50
1.20

36 25
37 24 0.30

0.20

9.70 7.30

48 13
1 12

5.80

9.70
5B_LQFP48_FP_V1

1. Dimensions are expressed in millimeters.

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Device marking for LQFP48

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 86. LQFP48 marking example (package top view)

STM32U585
Product identification(1)

CIT6

Y WW Date code

Pin 1 identifier
R Revision code

MSv67814V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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6.3 LQFP64 package information

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 87. LQFP64 - Outline(15)

BOTTOM VIEW

 
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4

0.25
(6)
S
B

E 1/4 L
4x N/4 TIPS

(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A

(13) (N – 4)x e

C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C

D (4)

(5) (2) D1 (9) (11)

(10)
D (3) b WITH PLATING
N (4)

1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)

A A SECTION B-B
(Section A-A)

TOP VIEW 5W_LQFP64_ME_V1

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Table 157. LQFP64 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.

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9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 88. LQFP64 - Recommended footprint

48 33

0.30
49 0.5 32

12.70

10.30

10.30
64 17

1.20
1 16

7.80

12.70
5W_LQFP64_FP_V2

1. Dimensions are expressed in millimeters.

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Device marking for LQFP64

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 89. LQFP64 marking example (package top view)

STM32U585
Product identification(1)

RIT6

Y WW Date code

Pin 1 identifier
R Revision code

MSv64352V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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STM32U585xx Package information

6.4 WLSCP90 package information

WLCSP is a 90 balls, 4.20 x 3.95 mm, 0.4 mm pitch, wafer level chip scale package.

Figure 90. WLCSP90 - Outline

A1 BALL LOCATION bbb Z
DETAIL A A1
e1
F aaa
G (4x)
A1

B4 B2

e2 E

e e
D A2
A
BOTTOM VIEW TOP VIEW SIDE VIEW

A3 A2 BUMP

A1
b eee Z

FRONT VIEW

b (90x) Z
ccc Z X Y
ddd Z
SEATING PLANE
DETAIL A
ROTATED 90
B01C_WLCSP90_ME_V2

1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.

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Table 158. WLCSP90 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 0.59 - - 0.023

A1 - 0.18 - - 0.007 -
A2 - 0.38 - - 0.015 -
(3)
A3 - 0.025 - - 0.001 -
b 0.22 0.25 0.28 0.009 0.010 0.011
D 4.19 4.20 4.21 0.165 0.165 0.166
E 3.93 3.95 3.97 0.155 0.156 0.156
e - 0.40 - - 0.016 -
e1 - 3.40 - - 0.134 -
e2 - 3.12 - - 0.123 -
F(4) - 0.400 - - 0.016 -
G(4) - 0.416 - - 0.016 -
aaa - - 0.10 - - 0.004
bbb - - 0.10 - - 0.004
ccc - - 0.10 - - 0.004
ddd - - 0.05 - - 0.002
eee - - 0.05 - - 0.002
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place

Figure 91. WLCSP90 - Recommended footprint

Dpad

Dsm
B03P_WLCSP36_DIE464_FP_V1

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Table 159. WLCSP90 - Recommended PCB design rules

Dimension Recommended values

Pitch 0.4 mm
Dpad 0,225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm

Device marking for WLCSP90

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 92. WLCSP90 marking example (package top view)

Pin 1 identifier

Product identification(1) U585OI6Q

Date code Y WW R Revision code

MSv67815V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.5 LQFP100 package information

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 93. LQFP100 - Outline(15)

θ2 θ1
(2)
R1

H
R2

B
B-
N
O
(6)

TI
C
SE
D1/4 B GAUGE PLANE

S
E1/4
B θ
4x N/4 TIPS
θ3 L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)

BOTTOM VIEW SECTION A-A

(N-4) x e (13)

C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)

SIDE VIEW

D (4)
(11) c
(2) (5) D1 c1 (11)

D (3)
(10) (4)
N

b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B

D1/4 (6) (2)

A B
(5)

E1 E

SECTION A-A

A A

TOP VIEW 1L_LQFP100_ME_V3

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Table 160. LQFP100 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - 1.50 1.60 - 0.0590 0.0630

(12)
A1 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 16.00 0.6299
(2)(5)
D1 14.00 0.5512
E(4) 16.00 0.6299
E1(2)(5) 14.00 0.5512
e - 0.50 - - 0.0197 -
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
N 100
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 94. LQFP100 - Recommended footprint

75 51

76 50
0.5

0.3

16.7 14.3

100 26

1.2
1 25

12.3

16.7

1L_LQFP100_FP_V1

1. Dimensions are expressed in millimeters.

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Device marking for LQFP100

The following figure gives an example of topside marking orientation versus pin 1 identifier
location. The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 95. LQFP100 marking example (package top view)

STM32U
Product identification(1)
585VIT6

R Revision code

Y WW Date code

Pin 1 identifier

MSv64353V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.6 UFBGA132 package information

This UFBGA is a 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package.

Figure 96. UFBGA132 - Outline

A1 ball identifier

E1 B A
e E
Z

D1 D

12 1
BOTTOM VIEW Øb (132 balls) TOP VIEW
Øeee M C A B
Ø fff M C

A4
ddd C

A2 A3
b A1 A
SEATING
PLANE
UFBGA132_A0G8_ME_V2

1. Drawing is not to scale.

Table 161. UFBGA132 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 6.850 7.000 7.150 0.2697 0.2756 0.2815
D1 - 5.500 - - 0.2165 -
E 6.850 7.000 7.150 0.2697 0.2756 0.2815
E1 - 5.500 - - 0.2165 -

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Table 161. UFBGA132 - Mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

e - 0.500 - - 0.0197 -
Z - 0.750 - - 0.0295 -
ddd - 0.080 - - 0.0031 -
eee - 0.150 - - 0.0059 -
fff - 0.050 - - 0.0020 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 97. UFBGA132 - Recommended footprint

Dpad

Dsm

UFBGA132_A0G8_FP_V1

Table 162. UFBGA132 - Recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values

Pitch 0.5 mm
Dpad 0.280 mm
Dsm 0.370 mm typ. (depends on the soldermask registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Ball diameter 0.280 mm

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Device marking for UFBGA132

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 98. UFBGA132 marking example (package top view)

STM32U
Product identification(1)

585QII6

Date code

Y WW R Revision code

Pin 1 identifier
MSv64354V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.7 LQFP144 package information

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 99. LQFP144 - Outline(15)

BOTTOM VIEW

 
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
(6) B GAUGE PLANE

0.25
D 1/4
S
B
L

E 1/4 (L1)
(1) (11)
4x N/4 TIPS
aaa C A-B D SECTION A-A
bbb H A-B D 4x

(N-4)x e
C
A
0.05 (12) ddd C A-B D
A2 A1 b ccc C

D (4)
D1 (2) (5)
(10) (3) D (9) (11)
N (4)
b WITH PLATING

1
2
3 E 1/4

(11) (11)
c c1
(6)
D 1/4 (2)
(3) A B (3) (5)

E1 E b1 BASE METAL
(11)

SECTION B-B

A A
(Section A-A)

TOP VIEW
1A_LQFP144_ME_V2

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Table 163. LQFP144 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 22.00 BSC 0.8661 BSC
(2)(5)
D1 20.00 BSC 0.7874 BSC
E(4) 22.00 BSC 0.8661 BSC
E1(2)(5) 20.00 BSC 0.7874 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 144
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.

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5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 100. LQFP144 - Recommended footprint

108 73
1.35

109 0.35 72

0.50

19.90 17.85
22.60

144 37

1 36

19.90
22.60
1A_LQFP144_FP

1. Dimensions are expressed in millimeters.

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Device marking for LQFP144

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 101. LQFP144 marking example (package top view)

Product identification(1) STM32U585ZIT6

R Revision code

Y WW Date code

Pin 1 identifier
MSv64355V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.8 UFBGA169 package information

This UFBGA is a 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.

Figure 102. UFBGA169 - Outline

Z Seating plane
A2 A4
ddd Z
A
A3 A1
b
SIDE VIEW A1 ball A1 ball
identifier index area X
E
E1
e F

A
F

D1 D

e
Y
N
13 1

BOTTOM VIEW Øb (169 balls) TOP VIEW

Ø eee M Z X Y
Ø fff M Z
A0YV_ME_V2

1. Drawing is not to scale.

Table 164. UFBGA169 - Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.950 6.000 6.050 0.2343 0.2362 0.2382
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.950 6.000 6.050 0.2343 0.2362 0.2382
e - 0.500 - - 0.0197 -
F 0.450 0.500 0.550 0.0177 0.0197 0.0217

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Table 164. UFBGA169 - Mechanical data (continued)

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

ddd - - 0.100 - - 0.0039

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 103. UFBGA169 - Recommended footprint

Dpad

Dsm MS18965V2

Table 165. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values

Pitch 0.5 mm
Dpad 0.27 mm
0.35 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Solder paste 0.27 mm aperture diameter.

Note: Non-solder mask defined (NSMD) pads are recommended.

4 to 6 mils solder paste screen printing process.

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Device marking for UFBGA169

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 104. UFBGA169 marking example (package top view)

Pin 1 identifier
STM32U
Product identification(1)

585AII6

Date code

Y WW R Revision code

MSv64356V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

6.9 Package thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
where:
• TA max is the maximum ambient temperature in °C.
• ΘJA is the package junction-to-ambient thermal resistance in °C/W.
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max).
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins:
PI/O max = ∑(VOL × IOL) + ∑((VDDIOx - VOH) × IOH)
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the
application.

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Table 166. Package thermal characteristics

Symbol Parameter Package Value Unit

LQFP48 7 x 7 mm 45.8
UFQFPN48 7 x 7 mm 26.9
LQFP64 10 x 10 mm 39.6
WLCSP90 4.2 x 3.95 mm 42.3
ΘJA Thermal resistance junction-ambient
LQFP100 - 14 × 14 m 34.4
UFBGA132 7 x 7 mm 35.2
LQFP144 20 x 20 mm 35.9
UFBGA169 7 x 7 mm 33.7
LQFP48 7 x 7 mm 23.4
UFQFPN48 7 x 7 mm 11.2
LQFP64 10 x 10 mm 22
WLCSP90 4.2 x 3.95 mm 27.5
ΘJB Thermal resistance junction-board °C/W
LQFP100 - 14 × 14 m 20.3
UFBGA132 7 x 7 mm 20.7
LQFP144 20 x 20 mm 24.8
UFBGA169 7 x 7 mm 19.3
LQFP48 7 x 7 mm 10.7
UFQFPN48 7 x 7 mm 8
LQFP64 10 x 10 mm 9.0
WLCSP90 4.2 x 3.95 mm 1.6
ΘJC Thermal resistance junction-top case
LQFP100 - 14 × 14 m 7.4
UFBGA132 7 x 7 mm 8.3
LQFP144 20 x 20 mm 7.6
UFBGA169 7 x 7 mm 8.3

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STM32U585xx Ordering information

7 Ordering information

Example: STM32 U 585 V I T 6 Q TR

Device family

STM32 = Arm based 32-bit microcontroller

Product type

U = ultra-low-power

Device subfamily

585 = STM32U585xx with OTG and AES hardware encryption

Pin count

C = 48 pins
R = 64 pins
O = 90 pins
V = 100 pins
Q = 132 balls
Z = 144 pins
A = 169 balls

Flash memory size

I = 2 Mbytes

Package

T = LQFP
I = UFBGA (7 x 7 mm)
U = UFQFPN
Y = WLCSP

Temperature range

6 = Industrial temperature range, –40 to 85 °C (105 °C junction)

3 = Industrial temperature range, –40 to 125 °C (130 °C junction)

Dedicated pinout

Q = Dedicated pinout supporting SMPS step-down converter

Packing

TR = tape and reel

xxx = programmed parts

For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.

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Important security notice STM32U585xx

8 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

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9 Revision history

Table 167. Document revision history

Date Revision Changes

02-Sep-2021 1 Initial release.

Updated:
– Figure 24 and Figure 25: STM32U585xQ power supply scheme (with SMPS)
– Figure 28: AC timing diagram for high-speed external clock source
– Figure 29: AC timing diagram for low-speed external square clock source
– VDDCoeff values in Table 36: Embedded internal voltage reference
– IDD(RUN) Range 2 values in Table 37 and Table 38
24-Sep-2021 2
– New consumption Table 40, Table 42, Table 45, Table 46, Table 50, Table 52,
Table 54, Table 56, Table 58, Table 60, Table 66, Table 68
– All values in consumption Table 53, Table 55, Table 57, Table 59, Table 65
– All values in Table 71, Table 72, Table 73
– USER TROM COVERAGE removed in Table 80: MSI oscillator characteristics
– Table 84: PLL characteristics
Updated:
– Security and cryptography
– ‘legacy’ replaced by ‘without SMPS’ in Table 2: STM32U585xx features and
peripheral counts
– PSSI in Table 10: Functionalities depending on the working mode
– Table 38 and new Table 39: Current consumption in Run mode on SMPS, code with
data processing running from Flash memory, ICACHE ON (1-way), prefetch ON,
VDD = 3.0 V
19-Nov-2021 3
– Table 45 and new Table 46: Current consumption in Sleep mode on SMPS, Flash
memory in power down, VDD = 3.0 V
– Table 47: SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and
SMPS
– twu(Sleep) max in Table 74: Low-power mode wakeup timings on SMPS
– Footnote 8 on Table 82: MSI oscillator characteristics
– tSU(RX) in Table 147: USART characteristics
– Section 6.5: LQFP100 package information
Updated:
– FMC_A16 and FMC_A17 in Table 26: STM32U585xx pin definitions and Table 28:
Alternate function AF8 to AF15
13-Dec-2021 4 – New tVBAT_BOR_sampling in Table 34: Embedded reset and power control block
characteristics
– CS_PARA in Table 79: LSE oscillator characteristics (fLSE = 32.768 kHz)
– Figure 32: Typical application with a 32.768 kHz crystal
Updated:
– GPIOs and capacitive sensing in Table 2: STM32U585xx features and peripheral
13-Mar-2022 5 counts
– Figure 1: STM32U585xx block diagram
– VBAT in Section 3.9.1: Power supply schemes

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Table 167. Document revision history (continued)

Date Revision Changes

– Backup domain in Figure 2 and Figure 3: STM32U585xx power supply overview

(without SMPS)
– IWDG in Table 10: Functionalities depending on the working mode
– New sentence beg. of Section 3.25: Octo-SPI interface (OCTOSPI)
– Section 3.25.1: OCTOSPI TrustZone security
– Figure 9: UFQFPN48_SMPS pinout
– PB2 I/O structure in Table 27: STM32U585xx pin definitions
– Notes of Table 51: Current consumption in Stop 1 mode on LDO
– Table 52: Current consumption during wakeup from Stop 1 mode on LDO
– Notes of Table 53: Current consumption in Stop 1 mode on SMPS
– Table 54: Current consumption during wakeup from Stop 1 mode on SMPS
– Table SRAM static power consumption in Stop 2 when supplied by LDO moved
– Notes of Table 55: Current consumption in Stop 2 mode on LDO
– Table 57: Current consumption during wakeup from Stop 2 mode on LDO
– Table SRAM static power consumption in Stop 2 when supplied by SMPS moved
– Table 60: Current consumption during wakeup from Stop 2 mode on SMPS
– Notes of Table 58: Current consumption in Stop 2 mode on SMPS
– Table SRAM static power consumption in Stop 3 when supplied by LDO moved
– Table 63: Current consumption during wakeup from Stop 3 mode on LDO
– Table SRAM static power consumption in Stop 3 when supplied by SMPS moved
– Notes of Table 64: Current consumption in Stop 3 mode on SMPS
– Table 66: Current consumption during wakeup from Stop 3 mode on SMPS
13-Mar-2022 5 (cont’d)
– Table 68: Current consumption during wakeup from Standby mode
– Notes of Table 69: Current consumption in Shutdown mode
– Table 70: Current consumption during wakeup from Shutdown mode
– twu(Sleep) and notes of Table 73: Low-power mode wakeup timings on LDO
– Notes Table 75: Regulator mode transition times
– Output driving current
– Notes of Table 95: Output voltage characteristics
– New Table 96: Output voltage characteristics for FT_t I/Os in VBAT mode
– Notes of Table 97: Output AC characteristics, HSLV OFF (all I/Os except FT_c)
– Notes of Table 98: Output AC characteristics, HSLV ON (all I/Os except FT_c)
– Table 100: Output AC characteristics for FT_t I/Os in VBAT mode
– fAHB_CAL removed from Table 104: 14-bit ADC1 characteristics
– Table 114: DAC characteristics
– RLoad and en in Table 118: OPAMP characteristics
– New Figure 44: OPAMP voltage noise density, normal mode, RLOAD = 3.9 kΩ and
Figure 45: OPAMP voltage noise density, low-power mode, RLOAD = 20 kΩ
– tLv(NOE_NE) in Table 131: Asynchronous multiplexed PSRAM/NOR read timings
– Section 6.2: LQFP48 package information
– Section 6.3: LQFP64 package information
– Section 6.5: LQFP100 package information
– Section 6.7: LQFP144 package information
– Disclaimer

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Table 167. Document revision history (continued)

Date Revision Changes

Added:
– Section 8: Important security notice
Updated:
– Up to 22 capacitive sensing channels
– Section 2: Description
– Table 2.: STM32U585xx features and peripheral counts
2-Jun-2022 6 – Section 3.36: Touch sensing controller (TSC)
– TSC_G3_IO1/TSC_G1_IO4 are removed from PC2/PC3 in Table 27.: STM32U585xx
pin definitions and Table 29.: Alternate function AF8 to AF15
– Table 72.: Typical dynamic current consumption of peripherals
– Table 90: EMI characteristics for fHSE = 8 MHz and fHCLK = 160 MHz
– Minimum value added for PSSR in Table 118.: OPAMP characteristics
– Disclaimer

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IMPORTANT NOTICE – READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product
or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2022 STMicroelectronics – All rights reserved

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