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Logic BIST silicon debug and volume diagnosis methodology

Conference Paper in IEEE International Test Conference (TC) · September 2011

DOI: 10.1109/TEST.2011.6139147 · Source: DBLP

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 Logic BIST Silicon Debug and Volume Diagnosis Methodology
M. Enamul Amyeen Andal Jayalakshmi Srikanth Venkataraman Sundar V. Pathy Ewe C. Tan
Intel Corporation, Hillsboro, OR
(enamul.amyeen | andal.jayalakshmi | srikanth.venkataraman| sundar.v.pathy| ewe.cheong.tan)@intel.com

Abstract In a product development, the post-silicon debug and

Post silicon speed-path debug and production volume diagnosis methodologies play a major role. Silicon
diagnosis for yield learning are critical to meet debug methods are used between the first silicon to
product time to market demand. In this paper, we product qualification to root-cause any design flaws
present Logic BIST speed-path debug technique and and the diagnosis methods are used to root-cause any
methodology for achieving higher frequency demand. fab process defects that delays product ramp-up and
We have developed a methodology for Logic BIST high-volume production. Speed path debug identifies
production fail volume diagnosis and presented tester the performance limiting paths that are fixed in future
time and memory overhead tradeoffs and optimization product stepping. Functional patterns are used for
for enabling volume diagnosis. Results are presented speed debug traditionally, but are very expensive and
showing successful isolation of silicon speed-paths on time consuming due to their long test sequences [4].
Intel® SOCs. On the other hand, scan-based tests are easier to
debug due to the limited number of at-speed capture
cycles and can provide the top limiting speed-paths.
1. Introduction
Post silicon debug to root-cause speed-path failures
and production volume diagnosis for yield ramp are
two critical components for meeting product time to In this paper we present flows for Logic BIST post
market demand. Increasing test cost and high silicon debug and production-fail volume diagnosis.
complexity in testing multiple functional blocks are The silicon results demonstrate the effectiveness of
making Logic built in self-test or LBIST test method the proposed methodology in successfully isolating
an attractive alternative to ATPG tests [1,2,3]. speed-paths for LBIST failures on Intel SOCs. We
proposed a novel two pass flow for LBIST on-line
volume diagnosis eliminating conventional interactive
Logic built-in self-test is a means whereby an debug approach. To the best of our knowledge this is
integrated circuit can test its own circuitry. It operates first approach for LBIST on-line volume diagnosis.
by exercising the circuit logic and then detecting if
the logic behaved as intended using on-chip test
generator and test response compactor. LBIST test The rest of the paper is organized as follows: Section
method is being seen as an attractive alternative and 2 presents an overview of the LBIST debug and logic
can be applied to almost any level of configuration diagnosis including LBIST implementation, speed
with a minimal interface and tester support. The other path debug, and the unit-level and production-fail
major benefit is tester memory saving. Since LBIST logic diagnosis flow. Section 3 presents LBIST
generates patterns on the die, it does not have to store speed-path debug methodology. LBIST diagnosis
patterns on tester memory. LBIST generates pseudo- flow for unit-level and production-fail volume
random patterns and usually needs additional test diagnosis are described in section 4. The experimental
points to compensate the inadequate test coverage. results including isolation silicon speed-paths, tester
The additional test points result in higher (typically overhead tradeoffs and optimization for LBIST
more than 90%) fault coverage for LBIST patterns. volume diagnosis are presented in section 5. Section
The LBIST controller and the test points have their 6 concludes the paper.
own overheads in area and power. The typical
hardware overhead for LBIST ranges from 1% to 2%.
Nonetheless, LBIST is becoming an industry standard
due to its attractive advantages over the costs.

Paper 7.3 INTERNATIONAL TEST CONFERENCE 1

978-1-4577-0152-8/11/$26.00 ©2011 IEEE
2. Logic BIST Debug and Diagnosis Overview A standard LBIST diagnosis flow uses a search
method such as a binary search to search for the
Since LBIST uses pseudo-random patterns, we need failing vector and applies this vector to shift out the
special methods for debug and diagnosis of those scan chain responses. This method is time consuming
blocks that have LBIST circuitry. In contrast, the scan due to its adaptive search and not suitable for online
based ATPG debug and diagnosis methods are based fail data collection. For volume production fail
on deterministic test patterns targeted for specific diagnosis, we need a method to capture failures online
faults. In this paper, for debug and diagnosis we (while on the tester) and log the fail information in
convert LBIST pattern into conventional ATPG the tester data-log while keeping the tester overheads
ASCII pattern format. In this section we present an to a minimum. We have developed and implemented
overview of the standard LBIST test flow, the speed- a flow for production fail diagnosis and the details
path debug method and the logic diagnosis flow. along with tester overhead computations are
discussed in section 4 and 5 respectively. Next, we
present the overview of speed-paths debug
2.1 Logic BIST Overview
methodology.
An integrated circuit with LBIST has special test
circuitry embedded in the design for generating the
stimulus and detecting the response. There are many
implementations of LBIST, but almost all use a
Pseudo Random Pattern Generator (PRPG) to 2.2 Speed-path Debug
generate the stimulus for the design, and a Multiple Speed paths limit the performance of a chip causing
Input Shift Register (MISR) to capture the response. chip to fail test at the target frequency. Finding the
The PRPG produces the test pattern data and supplies speed paths enable us to find places where potential
it to internal scan chains and the MISR compacts the design fixes can be applied to improve the
scan chain responses of the circuit which serves as a performance and push the design timing wall.
signature for that cycle of operation. This signature is Identifying speed paths is a crucial step in the post-
unique in the sense that each failure in the device will silicon stage for speed-sensitive products.
likely result in different value. In a standard LBIST
flow, the MISR signatures are accumulated over the At-speed fail data collection plays a critical role in
test cycles (usually large such as 100000) and identifying the speed paths. Transition fault patterns
compared with the golden signature at the end to can be applied to several chips on the tester and at-
know if the unit fails or passes. This is shown in speed fail data can be collected for different design
Figure 1. corners corresponding to different voltages and
temperatures. The frequency range of the at-speed fail
data collection can be determined from the Shmoo
plots as shown in Figure 2. The plot can show the
first failing frequency at which at-speed fail data is
taken and the test engineers usually take additional at-
speed fail data to investigate additional speed paths
that need to be optimized up to the frequency goal of
the design.

Figure 1. Standard LBIST implementation

Paper 7.3 INTERNATIONAL TEST CONFERENCE 2

 Volt

Pass

Fail

Freq

Figure 2. Shmoo Plot

We used Poirot speed path analysis tool [4,6] which

identifies potential speed-path for the top sightings to
address speed-gap and hit frequency goal. Figure 3
Figure 3. Launch-on capture at-speed transition cycles
shows Speed-path analysis for two cycles launch on
capture test. The first functional clock pulse initiate
the transition and send clock pulse to capture the The unit-level diagnosis flow is shown in Figure 4. The
observed values. Finally failures were observed fail data is obtained from testing the fail unit on the tester.
during unloading of scan chain values. Speed-path The fail data is converted to readable failure information
analysis tool does both static and dynamic analysis to for the logic diagnosis tool to analyze. The logic diagnosis
determine the receiving and destination flops. It then tool uses the failure observations from the tester’s datalog
ranks and identifies candidate paths based on path and the failure observations of a fault simulator that is
sensitization using simulation values. built into the tool to analyze and isolate the failure. It
prioritizes the list of candidates for fault locations for
In the next section we provide an overview of the further analysis through physical failure analysis
logic diagnosis flow for engineering and volume techniques.
diagnosis.
In a turnkey high volume diagnosis flow setup, the
2.3. Logic diagnosis datalogs for failing units are analyzed online by the
turnkey diagnosis servers and the results are stored in a
The diagnosis process is utilized to identify and root- database server. These results are later analyzed for
cause the issues of low product yield so that systematic defects to resolve any yield issues.
corrective actions can be taken. The true purpose of
logic diagnosis is to determine the location of the
3. Speed-path Debug Flow
defect though it can also be used to find the logic
nature of the defect [5,6]. There are two applications This section describes our methodology to collect and
for logic diagnosis: First, offline or unit-level analyze LBIST at-speed transition failures. The fail
diagnosis to root cause failures during engineering data is collected by setting up Shmoo for each voltage
debug or diagnosis. Second, online or production-fail and frequency to find the corresponding Fmax limit
volume diagnosis to root cause yield issues. Fmax1, Fmax2, Fmax3, … , Fmax100 and logging
the first failing pattern or trial. Once failing trial is
identified, the scan chain values are shifted out
through Tester Data Out (TDO) pin serially. The
failing scan cells are identified by comparing the
response with the expected scan cell values.

Paper 7.3 INTERNATIONAL TEST CONFERENCE 3

 Figure 4. Unit-level logic diagnosis flow

Diagnosis

Figure 5. Logic BIST diagnosis flow

4.1 Unit-level Diagnosis

We run Speed-path debug analysis with Fmax failures
and report potential speed-paths with the source and In this section, we will review the overall flow and
destination flops. The speed-paths are ordered based the components for unit-level LBIST diagnosis. We
on Fmax value and the common speed-paths across used a methodology which is similar to ATPG
from the highest limiting Fmax to lowest limiting diagnosis that is used to root-cause the hard defects in
Fmax are consolidated. For further analysis of the top the circuit. The overall flow is presented in Figure 5.
N Fmax limiters from the bucketing process, the
speed-path sightings and the information on the
limiting paths are recorded. The sighted speed-paths We used logic diagnosis and it needs a few collaterals
are compared with timing database and paths with for it to do the simulation needed to identify the fault
small timing margin are targeted for fix in the next locations. There are two components that need to be
product stepping. in place: 1. ASCII test patterns 2. Failure file. We
generated the ASCII test patterns using LBIST pattern
database. The LBIST failure data that comes from the
4 Logic BIST Diagnosis tester datalog needs special handling as it is just the
raw scan dump instead of any useful failure
information. We have automated this failure
There are two applications to logic diagnosis. It can
conversion to create a failure file. The custom ASCII
be used for unit-level diagnosis which identifies
patterns which has both failing and passing patterns
issues with packaged units that failed on the tester.
are to be prepared from the pattern files for diagnosis
The other application is for high-volume diagnosis
tool to analyze the actual failures against simulated
where the failures are collected online from the
faults. The results obtained for simulation of injected
failing units for later analysis. This section describes
faults for Intel SOCs are presented in section 5. The
our methodology for these two applications.
components of the LBIST diagnosis flow are
described in detail in the subsections.

Paper 7.3 INTERNATIONAL TEST CONFERENCE 4

4.1.1 Logic BIST ASCII Pattern generation the fail segments (instead of the whole chain), if the
LBIST controller can be configured for that. But this
During the LBIST front-end flow the LBIST database
is product specific as the hardware to reconfigure the
allows us to generate the ASCII patterns which are
chains of interest must be present in the design. The
the equivalent of the LBIST pseudo-random patterns
MISR segment configuration file provides the chain
generated on the die. Since LBIST pattern database
to segment mapping which helps to identify the
has the capability to initialize a PRPG, setup Linear
failing chain from the fail response.
Feedback Shift Register (LFSR) connections and
other constraints and generate random patterns, we
could simulate the LBIST controller and generate the
pseudo random patterns that actually get generated on
the chip. These patterns can be written out in ASCII
format for later use by the logic diagnosis tool.

Since the LBIST test cycles are large (100K) the

LBIST pattern database has to be run for these long
cycles to generate all the 100K patterns. This is time
consuming and occupies large disk space. To
overcome this we developed a flow to generate only
the patterns of interest. First we would need to run a
fault simulation till the end pattern to generate the
LBIST trace which has the PRPG seed for all the
100K patterns. Then we extract the PRPG/MISR
signature from the generated trace file for generating
the pattern of interest.

4.1.2 Custom ASCII Pattern generation

Since LBIST uses a large test cycle and the failing

patterns could be far apart, we need to have an
automated way to create a custom pattern file which
collects patterns from multiple pattern files. The logic
diagnosis tool uses both the passing and failing
patterns and response for its analysis of actual failures Figure 6. Logic BIST volume diagnosis flow
against simulation of injected faults. The LBIST
patterns could be pre-generated and stored for later 4.2 Production-fail volume diagnosis
use or could be generated on demand using the
method described in section 4.1.1. The overall flow for production-fail volume diagnosis
includes three basic components: test content
4.1.3 Fail Datalog conversion generation, fail data collection and automated
analysis. The overall flow is given in Figure 6.
Unlike ATPG diagnosis where the chip response is
compared to golden on the tester and the result is The test content for the diagnosis flow are generated
logged in the tester datalog, responses for LBIST by the LBIST front-end flow which constitutes the
failures are not compared online. The failure triggers Go-NoGo and Fault-Isolation patterns for the pass
the execution of diagnostic patterns which dump out and the fail flow respectively. These are used by the
the failing segment of the scan chains (concatenated test instance which identifies the failing MISRs and
as a daisy chain) as a long list of 0s and 1s. The fail triggers the fail-data collection. The fail-data are
responses are compared offline to determine the analyzed using a similar flow that we used for unit-
failing chain and flop. It is possible to just dump out

Paper 7.3 INTERNATIONAL TEST CONFERENCE 5

level diagnosis. The details of each of these three further data collection effort is done. At the end of the
processes are explained in the following sub-sections. second pass, we have the list of individual failing
trials, now we move on to the third pass, where we
execute each of the failing trial diag pattern
(concatenated chain mode) to log the scan chain data
to a datalog file. The datalog file is then used offline
for further POIROT based failure analysis. The 3
passes are shown here in Figure 7 and Figure 8.

Figure 7. Logic BIST pattern slices

4.2.1 Test Content generation

The test content is generated by the LBIST front-end

flow as Go-NoGo passing and Fault Isolation failing
patterns. The LBIST flow uses 100K patterns and is
sliced into 4 windows 1-100, 101-1000, 1001-10K
and 10001-100k and one Go-NoGo pattern is
generated for each window. During the pass flow, the
MISR signatures of the first 100 trials in each window
are compared with the golden and the failing trials are
stored for use by the fail flow. The cumulative MISR
Figure 8. Shifting out of failing MISR segment chains
of each window is also stored and compared to know
if there are failures outside of the first 100 trials in
One of the optimizations is to combine the First Pass
that window.
and Second Pass into just 4 Patterns and generated the
The Fault Isolation patterns are generated for the first LBIST patterns such that MISR compare happens at
100 trials of each window totaling to 400 trials. The the end of each trial for first hundred trials of each
actual failing trials that fall within these 400 trials are window. This allows the third pass to be 100 diag
run in the second iteration to dump out the scan chain. patterns (with chain concatenation for TDO dump)
The scan chain responses are not compared with per window for a total of 400 patterns. This provides
golden on-the die due to pattern memory restrictions. a better test time optimization at a slightly higher
We have automated this comparison as explained in pattern generation complexity.
the next subsection. 4.2.3 Automated Analysis
4.2.2 Fail data collection The LBIST failures are analyzed using an automated
flow similar to unit-level diagnosis and the details of
A Tester Method class is implemented to handle the the unit-level flow and the individual components
high-volume manufacturing fault isolation data were explained in detail in section 3. The advantage
collection in a consolidated manner. The test method of volume diagnosis over unit-level diagnosis is its
has 3 pass executions of patterns. The first pass is capability to collect fail data during production and
where the single ATE Pattern per trial window (4 analyze failures.
patterns in this example) is executed together in a
single burst and each failing pattern is logged. At the 5. Experimental Results
end of the first pass, we know the windows which
have failing trials in them. This leads to the second We applied Logic BIST debug and diagnosis flow to
pass, where we execute the targeted trial patterns isolate speed-path failures and manufacturing defects
(first 100 per window) in a burst and log all the on Intel® SOCs. The circuit statistics for LBIST
failing patterns, which identify the individual failing blocks are shown in Table 1. Column 2 and 3 show
trials. It is possible that the failing trial is outside the primary inputs count and primary outputs count
targeted trial list within that window; in that case, no respectively. The total gate count is shown in column

Paper 7.3 INTERNATIONAL TEST CONFERENCE 6

4. For the largest block the gate count is 5.9 Million. Table 1. Circuit statistics
The total number of scan chains is shown in column
6 and varies from ~100 to 600. The last column LBIST Latch
shows the total number scan-cells which are evenly Block Count
distributed across the scan chains. Gate # Scan
PIs POs Count Chains
Several diagnostic measures are used to evaluate the BlockG 478 443 5946335 661 216471
match between the simulation failures and the observed
BlockI 806 655 4164887 640 147714
failures and ranking the candidate faults. The diagnostic
measures are illustrated in figure 9. The term intersection BlockC 547 439 2696123 128 120570
is used to describe a match between fault and the BlockD 727 451 4492995 128 84579
observed behavior [6,7,8]. On some test cycles the stuck-
Block0 3205 3779 2795196 192 84540
at fault will cause simulation failures even though
Block1 4384 4638 4086324 360 17057
Block2 2858 1949 4131242 288 134173
Non-prediction Misprediction
Intersection Block3 792 576 2482149 192 84409

0.85V to 1.0V for 100,000 LBIST patterns. A binary

search was then performed to identify failing LBIST
scan operation cycle or trial. For all three units,
Candidate
failures were observed beyond 10,000 trials. The
Observed
number of failing destination flops given in the last
Figure 9. Diagnostic measures for ranking candidates column was obtained by shifting out the scan chain
values and comparing with the expected response.
there are no observed failures on those simulation cycles.
These additional simulation failures are termed as Table 2: LBIST Speed Failures
mispredictions [9,10,11], and they are caused by non-
excitation of the silicon defect on those simulation cycles. Unit Clock Voltage Failing No of
If we observe a complete match between simulation and ID Period trial Failing
observation failures for a test cycle, then it is referred as flops
cycle-intersection. S1 10ns 0.85V 10,769 14
The fault candidates are classified into different groups to 1.0V
based on the intersection, cycle-intersection and S2 10ns 0.85V 57,770 7
misprediction count. Faults with identical behavior, i.e., to 1.0V
same intersection, cycle-intersection, and misprediction S3 10ns 0.84V 57,770 7
counts belong to same candidate fault class.

5.1 Silicon Speed-path Debug results Units S2 and S3 produced identical failing flops
signatures at failing trial 57,770. The failing trail and
In this section, we will present results of silicon failing flop information is passed to speed-path
speed-paths debug using LBIST content. Out of all diagnosis tool [4]. The speed-path diagnosis identified
LBIST failing units, 25% of the units failed at the failing speed-paths corresponding to each failing flop.
specified Vmin voltage and passed at a higher voltage. The common segments among the failing paths were
After characterization 3 units were selected for further then ranked based on the number of occurrences. A
debug. common segment path will rank higher if it appears in
higher number of candidate paths. On all three units,
Table 2 shows the LBIST failure characteristics on the top ranked path segments were resided within or
three units with respect to clock period, voltage, first at the boundary of a specific full adder cell instance.
failing trial, and number of failing flops. On unit S1, Next, we mapped the failing locations in layout and
failures were observed at 10ns, within a voltage range identified the failing regions of interest.
Paper 7.3 INTERNATIONAL TEST CONFERENCE 7
In order to confirm and root-cause the speed failures from TRE probing. The probing at the input and out
laser probing LADA [12] tool was used. The units of adder identified the failing cycle. The failing
were thinned for the back of the chip for LADA condition on the carry-out signal is showing missing
scanning. The LADA probing patterns were created pulse. Circuit simulation later confirmed the weaker
only with the single failing trials. The failing pattern signal strength at one of the adder inputs causing the
or trial was then applied repeated while scanning laser failure. The driver strength and added cell design was
at the layout location identified from diagnosis. When changed to rectify the problem on future stepping of
unit shift from a failing condition to passing condition the product.
it is referred as a hit and identified as a dot. Figure 10
(a) shows the LADA hit at the failing adder cell at the
driver and receiver node of the adder cell. The adder
Clk
cell location is highlighted by a bounding rectangle.
Figure 10(b) shows the LADA hit with layout image
overlay.

CO
(pass)

CO
(fail)

Figure 12. TRE probing waveform at the adder cell

(a) (b) 5.2 Simulation Results for Unit-Level Diagnosis

Figure 10(a) Image of LADA hit at the adder cell location (b) We have setup the unit-level LBIST diagnosis flow
LADA hit image with layout overlay successfully on LBIST blocks. We generated the
ASCII patterns, did simulation validation for all the
LBISTed blocks.
Voltage

Voltage

We used fault simulation tool for logic validation and

all blocks have passed the simultion. We used Poirot
for simulation validation with injected faults and
Clock Period Clock Period obtained a good resolution for all LBIST blocks. The
results are tabulated below in Table 3. The diagnosis
(a) (b) results for 3 random faults are shown here. The
“Defect Type” shows the type of defect. It could be
Figure 11 (a) Failing and (b) passing Shmoo with LADA either stuck-at-0 (SA0) or stuck-at-1(SA1). The
scanning. “Number of failures” represents the total failing
patterns for this defect. This is obtained from the
Figure 10 shows the failing and passing Shmoo plot failure information file. The run time of the logic
while LADA scanning. The passing Shmoo is diagnosis tool was 5.61 secs on an average for the
observed while parking LADA on the region of faults shown here.
interest identified from diagnosis.
5.3 Tester overhead tradeoffs
LADA hit confirmed the failing area identified from
speed-path debug. In order to identify the failing We will analyze overhead for test time and tester
condition, time-resolved emission system TRE memory for enabling LBIST volume diagnosis. The
[13,14] probing was used. Figure 12 shows output overheads are computed based on design data and we

Paper 7.3 INTERNATIONAL TEST CONFERENCE 8

have detailed the observations below. There are two the shift clock period, Mbits be the number of MISR
types of patterns: 1. Go-NoGo and 2. Fault-Isolation. bits, Ntr be the number of trials, NMISR be the number
Table 3 Logic BIST simulation results MISR compares, and Ttest be the tester clock period.
For vanilla or baseline single MISR signature pass-
LBIST Diagnosis results
fail test, total execution time is comprised of time for
Block Fault Defec Number Run shifting the scan chain values over all trails and time
# t type of time for single shifting of final MISR signature. MISR bits
failures (secs) are shifted out through the TDO pin at tester clock
BlockG 1 SA1 438 4.28 frequency. In order to shift MISR bits, additional
2 SA0 27 7.49 overhead register bits, denoted as Obits are also need to
be shifted. The total execution time for baseline or
3 SA1 705 4.31
vanilla single MISR signature pass fail test is
BlockI 1 SA0 86 8.05
computed as:
2 SA1 83 3.10
3 SA0 23 6.39 Tbase  Ntr  Lscan  Tshift  (Mbits  Obits)  Ttest
BlockC 1 SA0 78 4.59
2 SA0 269 3.31
The shift clock frequency for our design is four times
faster than the tester clock frequency. For our design,
3 SA1 2997 10.05
Ntr value of 100,000 trials, shift clock period of 10
BlockD 1 SA0 127 7.46 nano second, tester clock period of 40 nano sec are
2 SA1 131 10.22 used. The number of MISR bits, Mbits varies and can
3 SA0 1161 8.36 range from 100 to 600. Similarly shifting overhead
Block0 1 SA1 135 1.44 register bits, Obits varies from 450 to 2000.
2 SA1 654 4.17
For Go-NoGo patterns assuming 400 MISR compares
3 SA1 639 3.51 represented as Ncmp, total execution time for Go-NoGo
Block1 1 SA0 1599 7.22 pattern on passing unit is calculated as:
2 SA1 139 2.15
Tgonogo_ pass  Ntr Lscan Tshift  (Mbits  Obits) Ttest  Ncmp
3 SA1 2854 6.02
Block2 1 SA1 218 8.16 The Tgonogo execution time for passing unit varies and
2 SA0 54 3.37 for our designs, can be 1 to 15% higher than Tbase. For
a failing unit, the failing MISR signatures need to be
3 SA0 546 6.38
corrected before continuing the execution of
Block3 1 SA1 1520 4.17
remaining trials. The execution time for a failing unit
2 SA1 113 3.30 will depend on the number of failing trials and the
3 SA1 895 7.02 number of MISR bits that gets corrupted. Let Nfailtr be
the number of failing trials. Typically 5% to 20% of
The Go-NoGo patterns are used to identify the failing total trials fail on a failing unit. Once failing MISR
MISRs and the Fault-Isolation patterns are used to signature is compared with the good MISR signature
concatenate the scan chains into a single chain and stored in the tester capture memory, corrupted MISR
shift out the responses through test data observation bits are identified. Let Rcap (0.005 millisecond) be the
or TDO pin. The test time computations for these two time to correct each MISR corrupted bit. For logic
patterns are given below. fails, typically single scan chain segment fails and
corresponding MISR segment bits get corrupted. Let,
Test Time: Based on current estimates, there will be Nseg be the number of chain segment, and Mbits/Nseg
some additional costs for both passing and failing represents the number of MISR bits corresponding to
units for Go-NoGo pattern relative to the vanilla a single chain segment. The execution time for
LBIST pattern which execute a single MISR signature Go-NoGo patterns on a failing unit can be computed
pass-fail test. Next, we will define terms to compute as follows:
test time. Let, Lscan be the length of scan chain, Tshift be Mbits
Tgonogo_ fail  Tgonogo_ pass  Nfailtr   Rcap
Nseg
Paper 7.3 INTERNATIONAL TEST CONFERENCE 9
 On a failing unit, the corrupted MISR signature bits Acknowledgement
need to be restored for Go-NoGo passing pattern. The authors would like to thank Carlston Lim for
Assuming 10% of the MISR compared trials fails and enabling speed-path diagnosis flow, Ajithkumar
single MISR segment bits are corrupted, the overhead Kalangara for implementing LBIST test class, Chin
for Go-NoGo patterns varies between 2% to 20% on a Wah Lim for the silicon failure debug, Inn Chin
failing unit. For fault-isolation pattern, execution Wong from SOC product engineering team for
time is comprised of shifting of scan chain values enabling volume diagnosis deployment.
through TDO, fault-isolation pattern overhead (Opat),
and datalogging time of observed values from the References
capture memory. Let Lseg be the length of a single
[1] Kenneth M. Butler, “ATPG versus Logic BIST - Now and in
chain segments obtained from concatenating the chain the Future”, International Test Conference, 2001
corresponds to a single chain. The execution time for [2] Greg Crowell, Ron Press, "Using Scan Based Techniques for
Fault isolation pattern is computed as: Fault Isolation in Logic Devices", Microelectronics Failure
Analysis, 132–138, Oct 2004
TFI  Lseg Ttest  Lseg  Rcap  Opat [3] W.-T. Cheng, M. Sharma, T. Rinderknecht, Liyang, C. Hill,
“Signature Based Diagnosis for Logic BIST”, IEEE International
The fail unit test time to be 5-10x Tbase (mostly Test Conference, Oct. 21–26, 2007
dominated by serial scan unload time). The overall
[4] R. McLaughlin, S. Venkataraman and C. Lim, “Automated
test time increase will be dependent on Tbase relative to Debug of Speed Path Failures Using Functional Tests” 91 – 96;
test time for all tests and their time, and also the VLSI Test Symposium, pp 91-96, 2009
fraction of good to bad units (failing LBIST). The [5] M. Abramovici, M. A. Breuer, and A. D. Friedman, “Digital
exact increase will depend on the particular System Testing and Testable Design”, AT&T Bell Laboratories
configuration of the block. Initially this test time and W. H. Freeman and Company, 1990.
increase will not be too much of a concern since there [6] S. Venkataraman, S. Drummonds, “Poirot: Applications of a
will be small amount of material or units to test. But Logic Fault Diagnosis Tool”, IEEE Design & Test of Computers,
over time with product ramp, we may have to dial Jan.-Feb. 2001 pp. 19-31.
down the sample of fail units to reduce the overall test [7] B. Chess, D. B. Lavo, F. J. Ferguson, and T. Larrabee,
time. “Diagnosis of Realistic Bridging Faults with Single Stuck-at
Information,” IEEE/ACM International Conference on CAD, pp.
Tester Memory: For Go-NoGo patterns, good MISR 185-192, Nov. 95.
signatures for the compared failing trials are stored.
[8] D. B. Lavo, T. Larrabee, and B. Chess, “Beyond Byzantine
For our LBIST blocks, the maximum number of trials
Generals: Unexpected Behavior and Bridging Faults Diagnosis,”
for MISR compare is limited by the available tester IEEE International Test Conference, pp. 611-619, Oct. 96.
memory. With current tester capacity, for the largest
[9] D. Josephon, S. Poehlman, and V. Govan,, “Debug
failing block we can accommodate 500 MISR Methodology for the McKinley Processor”, International Test
compares within the capture memory limit. For fault Conference, 2001, pp. 451-460.
isolation pattern, expected values of scan chain
[10] Dahlgren, P.; Dickinson, P.; Parulkar, I., “Latch divergency
captures are not stored to save tester memory and in microprocessor failure analysis”, International Test
failing scan cells are determined in off-line by Conference, 2003, pp.755 – 763.
comparing observed values with the expected chain [11] P. Maxwell, I. Hartanto, L. Bentz, “Comparing Functional
values. and Structural Test”, International Test Conference, 2000, pp.
400-407.
7. Conclusions
[12] J. A. Roelette, T. Eiles, “Critical timing analysis in
We presented Logic BIST debug and volume
microprocessors using near-IR laser assisted devices alteration,”
diagnosis methodology for isolating speed-path IEEE International Test Conference, pp. 264-273, Oct. 2003.
failures and manufacturing defects. Silicon results are
[13] J. C. Tsang, J. A. Kash, D. P. Vallett, “Picosecond imaging
presented isolating speed-paths using at-speed scan circuit analysis”, IBM Journal of Research and Development,
test content on Intel SOCs. A novel volume diagnosis 44(4), 2000, pp. 583-604
methodology for LBIST diagnosis is developed and
[14] J. C. Tsang, J. A. Kash, and D.P. Vallett, "Time-
presented eliminating conventional interactive failure
resolved optical characterization of electrical activity in
diagnosis approach. integrated circuits,", IEEE International Test Conference, pp.
1440-1459

Paper 7.3 INTERNATIONAL TEST CONFERENCE 10

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