Pipelining | Practice Problems t& Computer Organization and Architecture ‘Spread the love ing_in Computer Architecture- Before you go through this article, make sure that you have gone through the previous article on Instruction Pee Sr) Peon) peeeciis ed Dead healthier livesIn instruction pipelining, * A form of parallelism called as instruction level parallelism is implemented. + Multiple instructions execute simultaneously. + Speed up, Efficiency and Throughput serve as performance measures of pipelined execution. Also Read- Performance Criteria Of Fae} eee ee errs CAE ee ea od PRACTICE PROBLEMS BASED ON PIPELINING IN COMPUTER ARCHITECTURE- Problem-01: Consider a pipeline having 4 phases with duration 60, 50, 90 and 80 ns. Given latch delay is 10 ns Caloulate- 1, Pipeline cycle time 2. Non-pipeline execution time 3. Speed up ratio 4, Pipeline time for 1000 tasks 5, Sequential time for 1000 tasks 6, Throughput Soluear ACCESS * Four stage pipeline is used + Delay of stages = 60, 50, 90 and 80 ns * Latch delay or delay due to each register = 10 ns Part-01: Pipeline Cycle Time- Cycle time = Maximum delay due to any stage + Delay due to its register= Max { 60, 50, 90, 80} + 10 ns = 90 ns +10ns = 100 ns Non-pipeline execution time for one instruction = 60 ns + 50 ns +90 ns + 80 nscea ere) Peet) cece eid Cea) healthier lives = 280 ns Part-03: Speed Up Ratio: Speed up = Non-pipeline execution time / Pipeline execution time = 280 ns / Cycle time = 280 ns / 100 ns =28 ipeline Time For 1000 Tasks- Pipeline time for 1000 tasks = Time taken for ‘st task + Time taken for remaining 999 tasksCotes Poe Gees HelloFresh™ More time for what! = 1x4 clock cycles + 999 x 1 clock cycle = 4 x cycle time + 999 x cycle time = 4x 100 ns +999 x 100 ns = 400 ns + 99900 ns = 100300 ns Part-05: Sequential Time For 1000 Tasks- Non-pipeline time for 1000 tasks = 1000 x Time taken for one task = 1000 x 280 ns = 280000 ns Part-06: Throughput- Throughput for pipelined execution = Number of instructions executed per unit time = 1000 tasks / 100300 nsProblem-02: A four stage pipeline has the stage delays as 150, 120, 160 and 140 ns respectively. Registers are used between the stages and have a delay of 5 ns each. Assuming constant clocking rate, the total time taken to process 1000 data items on the pipeline will be- 1. 120.4 microseconds 2. 160.5 microseconds 3. 165.5 microseconds 4, 590.0 microseconds Solution- Given- Four stage pipeline is used Delay of stages = 150, 120, 160 and 140 ns Delay due to each register = 5 ns 1000 data items or instructions are processedCycle Time- Cycle time = Maximum delay due to any stage + Delay due to its register = Max { 150, 120, 160, 140} + 5ns = 160ns+5ns = 165 ns Pipeline Time To Process 1000 Data Items- Pipeline time to process 1000 data items = Time taken for 1st data item + Time taken for remaining 999 data items = 1x4 clock cycles + 999 x 1 clock cycle = 4x cycle time + 999 x cycle time = 4x 165 ns +999 x 165 ns = 660 ns + 164835 nscea ere) Peet) cece eid Cea) healthier lives = 165495 ns = 165.5 ps Thus, Option (C) is correct. Problem-03: Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of 4. The same processor is upgraded to a pipelined processor with five stages but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the pipeline, The speed up achieved in this pipelined processor is- 1.3.2 2.3.0 3.22 4.2.0 Solu Cycle Time in Non-Pipelined Processor-Frequency of the clock = 2.5 gigahertz Cycle time = 1 frequency = 11 (2.5 gigahertz) = 11 (2.5 x 10° hertz) =04ns Non-Pipeline Execution Time- Non-pipeline execution time to process 1 instruction= Number of clock cycles taken to execute one instruction = 4 clock cycles, =4x0.4ns =1.6ns Cycle Time in Pipelined Processor- Frequency of the clock = 2 gigahertz Cycle time =1/ frequency =1/(2 gigahertz) =1/ (2x 10° hertz)Save over 45% on fet ea Ey Discount on first year. rue =0.5ns Pipeline Execution Time- Pee Sr) Peon) peeeciis ead Dead healthier lives Since there are no stalls in the pipeline, so ideally one instruction is executed per clock cycle. So, Pipeline execution time = 1 clock cycle =05ns Speed Up-‘Speed up = Non-pipeline execution time / Pipeline execution time =1.6ns/0.5 ns =32 Thus, Option (A) is correct. Problem-04: The stage delays in a 4 stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is %. Solu Ex lion Time in 4 Stage Pipeline-Cycle time = Maximum delay due to any stage + Delay due to its register = Max { 800, 500, 400, 300} + 0 = 800 picoseconds Thus, Execution time in 4 stage pipeline = 1 clock cycle = 800 picoseconds. Throughput in 4 Stage Pipeline- Throughput = Number of instructions executed per unit time = 1 instruction / 800 picoseconds Ex lion Time in 2 Stage Pipeline- Cycle time = Maximum delay due to any stage + Delay due to its register = Max { 600, 350} +0 = 600 picoseconds Thus, Execution time in 2 stage pipeline = 1 clock cycle = 600 picoseconds. Throughput in 2 Stage Pipeline- Throughput = Number of instructions executed per unit time = 1 instruction / 600 picosecondsThroughput Increase- Throughput increase = { (Final throughput ~ Initial throughput) / Initial throughput } x 100 = { (1/600 - 1/800) / (1 / 800) } x 100 = { (800 / 600) - 1} x 100 = (1.33 - 1) x 100 = 0.3333 x 100 = 33.33% Problem-05: Anon-pipelined single cycle processor operating at 100 MHz is converted into a synchronous pipelined processor with five stages requiring 2.5 ns, 1.5 ns, 2ns, 1.5 ns and 2.5 ns respectively. The delay of the latches is 0.5 sec. The speed up of the pipeline processor for a large number of instructions is 1.45 2.40 3.3.33 4.3.0 Solution- Cycle Time in Non-Frequency of the clock = 100 MHz Cycle time = 1 frequency =1/ (100 MHz) = 1/ (100 x 10° hertz) = 0.01 us Non-Pipeline Execution Time- Non-pipeline execution time to process 1 instruction = Number of clock cycles taken to execute one instruction = 1 clock cycle = 0.01 us =10ns Cycle Time in Pipelined Processor- Cycle time = Maximum delay due to any stage + Delay due to its register = Max {2.5, 1.5, 2, 1.5, 2.5} +0.5ns =2.5ns+0.5ns =3ns eline Execution Time-Pipeline execution time = 1 clock cycle =3ns Speed Up- Speed up = Non-pipeline execution time / Pipeline execution time =10ns/3ns =3.33 Thus, Option (C) is correct. Problem-06: We have 2 designs D1 and D2 for a synchronous pipeline processor. D1 has 5 stage pipeline with execution time of 3 ns, 2ns, 4 ns, 2 ns and 3 ns. While the design D2 has 8 pipeline stages each with 2 ns ‘execution time, How much time can be saved using design D2 over design D1 for executing 100 instructions? 4.214 ns 2, 202 ns 3. 86 ns 4, 200 ns Solu Cycle Time in Design D1-Cycle time = Maximum delay due to any stage + Delay due to its register = Max (3,2, 4,2,3}+0 =4ns Execution Time For 100 Instructions in De: Execution time for 100 instructions = Time taken for ‘st instruction + Time taken for remaining 99 instructions = 1x5 clock cycles + 99 x 1 clock cycle = 5x cycle time + 99 x cycle time =5x4ns+99x4ns = 20 ns + 396 ns = 416 ns Cycle Time in Design D2- Cycle time = Delay due to a stage + Delay due to its register =2ns+0 =2ns 5 ion Time For 100 ions in Design D2- Execution time for 100 instructions= Time taken for 1st instruction + Time taken for remaining 99 instructions = 1x8 clock cycles + 99 x 1 clock cycle = 8x cycle time + 99 x cycle time =8x2ns+99x2ns = 16ns +198 ns = 214 ns Time saved = Execution time in design D1 — Execution time in design D2 = 416 ns - 214 ns = 202 ns Thus, Option (B) is correct. Problem-07: Consider an instruction pipeline with four stages (S1, S2, S3 and $4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure-Stage $2 Delay 6 ns Stage $3 Delay 11 ns Stage $4 Delay 8 ns Stage $1 Delay 5 ns e Register (Delay 1 ns) ine Register (Delay 1 ns) Pipeline Register (Delay 1 ns) Pipeline Register (Delay 1 ns) What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation? 1.4.0 2.25 344 4.30 Solu Non-Pipeline Execution Time- Non-pipeline execution time for 1 instruction =5ns+6ns+11ns+8ns = 30ns Cycle Time in Pipelined Processor- Cycle time= Maximum delay due to any stage + Delay due to its register = Max {5,6, 11,8) + 1 ns =11ns+1ns =12ns eline Execution Time- Pipeline execution time = 1 clock cycle = 12ns Speed Up- ‘Speed up = Non-pipeline execution time / Pipeline execution time = 30ns/12ns =25 Thus, Option (B) is correct. Problem-08: Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions 1, 12, 13 and 4 in stages $1, S2, S3 and $4 is shown below- st | S283 | 8412 1 3 2 2 13 2 1 1 3 4 1 2 2 2 What is the number of cycles needed to execute the following loop? for to 2) {14; 12; 13; 14; } 1.16 2.23 3.28 4.30 123 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 24 22. 23 sifufufelafafalafaf2}ofia|. 4 "1 e}elsfa}ofalwfu}e2]e2]is Phase-Time Diagram From here, number of clock cycles req sd to execute the loop = 23 clock cycles. Thus, Option (B) is correct.Problem-09: Consider a pipelined processor with the following four stages- IF : Instruction Fetch ID : Instruction Decode and Operand Fetch EX: Execute WB : Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions? ADD R2,R1,RO R2—RO+R1 MULR4,R3,R2_ R4-— R3 +R2 SUBR6,R5,R4 RE RS+R4 17 2.8 3.10 4.14 Solu The phase-time diagram is-Phase-Time Diagram From here, number of clock cycles required to execute the instructions = 8 clock cycles. Thus, Option (B) is correct. Problem-10: Consider the following procedures. Assume that the pipeline registers have zero latency. P1 : 4 stage pipeline with stage latencies 1 ns, 2ns, 2s, 1 ns P2 : 4 stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns P3 : 5 stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 11ns P4.: 5 stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 nsWhich procedure has the highest peak clock frequency? 4.P4 2.P2 3. P3. 4.P4 Itis given that pipeline registers have zero latency. Thus, Cycle time = Maximum delay due to any stage + Delay due to its register = Maximum delay due to any stage For Processor P1 Cycle time = Max {1 ns, 2ns, 2ns, 11ns} =2ns Clock frequency =1/ Cycle time =1/2ns = 0.5 gigahertz For Processor P2:Cycle time = Max {4 ns, 1.5 ns, 15ns, 15 ns} =1.5ns Clock frequency =1/ Cycle time =1/1.5ns = 0.67 gigahertz For Processor P3: Cycle time = Max {0.5 ns, 1 ns, 11s, 0.6 ns, 1s} =1ns Clock frequency =1/ Cycle time =1/1ns = 1 gigahertz For Processor P4: Cycle time = Max {0.5 ns, 0.5 ns, 1ns, 1ns, 1.11} =1.41nsClock frequency =1/ Cycle time = 1/1108 = 0,91 gigahertz Clearly, Process P3 has the highest peak clock frequency. Thus, Option (C) is correct Problem-11: Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies T;, Tz and T such that T, = 3T2/4 = 273. Ifthe longest pipeline stage is split into two pi frequency is _ GHz, ignoring delays in the pipeline registers, Solu Let‘ be the common multiple of each ratio, then- “Tet 2 T2=4t/3 * Ty=t/2 eline Cycle Tim: Pipeline cycle time = Maximum delay due to any stage + Delay due to its register ine stages of equal latency, the new= Max {t, 43, 2} +0 = 41/3 Frequency Of Frequency =1/ Pipeline cycle time = 11 (4t/3) =3/4t Given frequency = 3 GHz. So, 3/4t=3 GHz 4t=1ns 25 ns Stage Latencies Of Pipeline-Stage latenoy of different stages are + Latency of stage-01 = 0.25 ns + Latency of stage-02 = 0.33 ns + Latency of stage-03 = 0.125 ns Splitting The Pipeline- The stage with longest latency i.e. stage-02 is split up into 4 stages. After splitting, the latency of different stages are- + Latenoy of stage-01 = 0.25 ns + Latency of stage-02 = 0.165 ns + Latency of stage-03 = 0.165 ns + Latency of stage-04 = 0.125 ns Splitted Pipeline Cycle Splitted pipeline cycle time = Maximum delay due to any stage + Delay due to its register = Max { 0.25, 0.165, 0.165, 0.125} +0 =0.25 ns Frequency =1/ splitted pipeline cycle time =1/0.25ns =4GHzThus, new frequency = 4 GHz. Get more notes and other study material of Computer Organization and Architecture. Watch video lectures by visiting our YouTube channel LearnVidEun. PE Summary Article Name Pipelining | Practice Problems Description Practice Problems based on Pipelining in Computer Architecture. Pipetining in Computer Architecture is an efficient way of executing instructions. Speed up, Efficiency and Throughput are performance parameters of pipelined architecture. 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