82C206

INTEGRATEDPERIPHERAL CONTROLLER

100%Compatibleto IBM’” PC AT 114 bytes of CMOS RAM memory

Fully compatible to Intel’% 8237 DMA 8 MHz DMA clock with programmable
controller, 8259 Interrupt controller, 8254 internal divider for 4 MHz operation
Timer/Counter, and Motorolarms146818
Real Time Clock Programmable wait states for the DMA
cycle
Offers 7 DMA channels, 13 Interrupt re-
questchannels,2 Timer/Counterchannels, 16 Mbytes DMA addressspace
and a Real Time clock Single chip 84-pin CMOS implementation
Reduced recovery time (120 ns) between

8259 and 8254. Variable wait state option is

providedfor the DMA cycles: programmable
delays are provided for the CPU access to
the internal registers of the chip. The chip
also providesan option to select 8 or 4 MHz
systemclock.

The 82C206, along with the CS8220 PC AT

Compatible CHIPSet. providesa highly inte-
grated high performancesolutionfor a PC AT
compatible implementation.

The 82C206 is implementedusing advanced

CMOS technologyand is packagedin an 84-
pin PLCC.
2
 .

82C206 Pin Description

Pin No. Name Type Function

24-31 XD7-XDO I/0 DATA BUS: The Data Bus lines are 3-state bi-
directional lines connected to the system data bus
(XD bus in a PC/AT design). The outputs are
enabled in the program condition during the I/0
Read to output the contents of the DMA controller
registers (Address register, Status register,the
Temporary register or a Word Count register), the
three Interrupt Controller registers (Interrupt Request
register, In Service register and the Interrupt Mask
register), the Timer/Counters registers (namely the
contents of these counters or states of the counters),
the Real Time Clocks internal registers and page
registers of memory mapper.

During an I/0 write cycle, the outputs are disabled

and the CPU can program the DMA Controller
registers, the Interrupt Controller registers,the
Timer/Counters registers,the DMA Page register
and the Real Time Clock registers and internal
RAM.
.
During DMA cycles, the most significant 8 bits of
the address are output onto the data bus to be
strobed into an external latch by ADSTB8 or
ADSTB16. During memory-to-memory operations,
data from the memory comes into the DMA
Controller on the data bus during read from the
memory. In the write to memory transfer,the data
bus outputs place the data into the new memory
location.

During the interrupt sequence, the interrupt

controllers output the interrupt vector byte on the
data bus.

Data bus XD7-XDO also acts as the multiplexed

address/data bus for the Real Time Clock.

3
 Pin No. Name Type Function
35-43 XA8-XAO I/0 ADDRESS BUS: This is the system address bus
34 XA9 I used to address various registers of the 82C206. It
is tied to the external bus (XA bus) in a PC/AT
compatible design. During a non-DMA cycle, A3-AO
act as inputs and are used by the CPU to address
the registers of the DMA Controller corresponding
to DMA channels O-3 and A4-A1 address the
registers of the DMA Controller corresponding to
DMA channels 5-7. In the active DMA cycle, A7-AO
are outputs and carry address information for DMA
channels O-3. Correspondingly,A8-A1 are address
outputs for 16 bit DMA channels 5-7. During
program condition, A9-AO are used to address
configuration register and the internal registers of
DMA Controller, INT Controller, Timer, RTC and
Memory Mapper.
18 RESET RESET: Reset is active high input which affects the
following registers:

DMA Controllers: Clears the Command, Status,

DMA Request, Temporary register, First/Last flip-
flop; sets the Mask register. Following reset, the
DMA controller is in an idle state.

INTERRUPT Controllers: Clears the edge sense

circuit, the interrupt mask register, all ICW4
functions, IRQO is assigned highest priority, slave
7 address is set to special mask mode is disabled
and status read is set to IRR.
54 XIOR I/0 I/0 READ: I/0 Read-is a bidirectional active low
three-state line. In an idle cycle (non DMA, non-
interrupt), it is an input control signal used by the
CPU to read the 82C206 internal registers. in an
active DMA cycle, it is an output control signal used
by the DMA Controller to access data from a

memory-to-memory transfer. ●

4
 Pin No. Name Type Function
62 DMAMEMW O DMA MEMORY WRITE: DMAMEMW is an active low
three-state output used to write data to the selected
memory location during DMA write or a memory-to-
memory transfer. In a PC/AT compatible design, this
signal is connected to XMEMW.
21 SCLK I CLOCK INPUT: The Clock Input is used to generate
the timing signals which control DMA operations.
This input may be driven from DC to 10 MHz. The
Clock may be stopped in either state for standby
operation. The internal clock used for DMAC is
either the SCLK or SCLKA2depending on the
setting of DMA CLOCK SELECT bit in the
configuration register.
68 IOCHRDY I/0 I/0 CHANNEL READY: In the input mode. a low on
IOCHRDY causes the internal DMA readysignal to
go low asynchronously.When IOCHRDY goes high,
one DMA Clock cycle will elapse before internal
DMA Ready goes up. This signal is used to extend
memory read and write pulses for the DMA
controllers to accommodate slow memories or I/O
devices. IOCHRDY must satisfy set-up and hold
times with respect to DMACLK in order to work
reliably.

In the output mode, this pin is an open drain output

and provides an active low output whenever any
82C206 register is addressed for read or write. This
output will remain low for a programmed number of
DMACLK cycles (as configured by bits 6 and 7 of
82C206 configuration register) and then goes high,
if pulled up by an external register. IOCHRDY
provides a means of introducing a progammed
number of wait-states (as counted by DMACLK
cycles) for I/0 read/write cycles to 82C206. In a
PC/AT architecture based design this pin should be
wire-ored to PC/AT’s IOCHRDY signal.
73 HLDA I HOLD ACKNOWLEDGE: The active high Hold —
Acknowledge from the CPU indicates that it has
relinquished control of the system busses.
—

5
82C206 Pin Inscription (Continued)

Pin No. Name Type Function

44- DREQO- I DMA REQUEST: The DMA Request (DREQ) are
47 DREQ3 individual asynchronouschannel request inputs
60- DREQ5- used by peripheral circuits to obtain DMA service.
58 DREQ7 in Fixed Priority, DREQO has the highest priority
and DREQ7 has the lowest priority. A request is .
generated by activating the DREQ line of a channel.
DACK will acknowledge the recognition of DREQ
signal. Polarity of DREQ is programmable. Reset
initializes these lines to active high. DREQ must be
maintained until the corresponding DACK goes
active. DREQ will not be recognized while the clock
is stopped. Unused DREQ inputs should be pulled
High or Low (inactive) and the corresponding mask
bit set.

DREQO-DREQ3 support 8-bit transfers between 8-

bit I/0 and 8 or 16-bit system memory.
DREQ5-DREQ7 support 16-bit data transfers
between 16-bit peripheral and 16-bit system
memory. DREQ4 is not available as it is used to
cascade DREQO-DREQ3.
67 TC o TERMINAL COUNT: Terminal Count (TC) is an
active high signal. Information concerning the
completion of DMA services is available at the TC
output pin.

A pulse is generated by the DMA Controller when

terminal count (TC) for any channel is reached,
except for channel O in memory-to-memory mode.
During memory-to-memory transfers TC will be
output when the TC for channel 1 occurs.

When a TC pulse occurs, the DMA Controller will

terminate the service, and if auto-initialize is
enabled, the base registerswill be written to the
current registersof that channel. The mask bit and
TC bit in the status word will be set for the
currently active channel unlessthe channel is
programmed for auto-initialize. In that case, the
mask bit remains clear.

6
82C206 Pin Description(Continued)
—
Pin No. Name Type Function
69 HRQ o HOLD REQUEST: The Hold Request (HRQ) output
is used to request control of the system bus. When
a DREQ occurs and the corresponding mask bit is.
clear, or a software DMA request is made, the DMA
Controller issues HRQ. The HLDA signal then
informs the controller when access to the system
busses is permitted. For stand-alone operation
where the DMA Controller always controls the
busses, HRQ may be tied to HLDA. This will result
in one SO state before the transfer.
48- DACKO- 0 DMA ACKNOWLEDGE: DMA Acknowledge is used—
51 DACK3 to notify the individual peripherals when one has
57- DACK5- been granted a DMA cycle. The active polarity of
55 DACK7 these lines is programmable. Reset initializes them
to active low. Because these signals are used
internally for cascading the DMA channels and for
DMA page register selection, these signals must be
programmed to be active low.
66 ADSTB8 o ADDRESS STROBE: This is an active high signal —
used to control latching of the upper address byte
(A8-A15) for 8-bit peripherals. It will drive directly
the.strobe input of external transparent octal
latches. During block operations, ADSTB8 will only
be issued when the upper address byte must be
updated, thus speeding operation through
elimination of S1 states. ADSTB8 is active for DMA
channels O-3.
64 AEN16 o ADDRESS ENABLE for 16-BIT DMA TRANSFERS: —
This signal enables the 8-bit latch containing the
upper 8 address bits (A9-A16) on to system address
bus. It is inactive when external bus master controls
the system bus (MASTER=O). This signal is active
low.
65 ADSTB16 o ADDRESS STROBE for 16-BIT TRANSFERS –
(channels 5-7). This is an active high signal used to
control latching of the upper address byte A9-A16
for 16-bit DMA transfers. Its function is just like
ADSTB8.
63 AEN8 o ADDRESS ENABLE for 8-BIT DMA TRANSFERS: –
This signal is the output enable for the 8-bit latch
containing upper 8 address bits (A8-A15). It enables
A8-A15 system address bus. It is inactive when
external bus master controls the system bus
(MASTER=O).This signal is active low.

7
82C206 Pin Description(Continued)

Pin No. Name Type Function

33 ACK (MSE) I MODULE SELECT ENABLE: When high, it enables
the chip select function on one of the modules
(DMA Controller, INT Controler, TIMER, RTC, DMA
Page register or the Configuration register) for the
programming function, i.e. CPU read or write of the
command, status or other register of various
modules of the 82C206. When low, the 82C206 is
essentially disconnectedfrom the system bus. The
82C206 at this time could be performing an active
DMA or an interrupt cycle. In a PC/AT compatible
design, this pin is tied to ACK signal.
11-5 A23-A17 o DMA PAGE REGISTER ADDRESS: XA16 and
13 XA16 o A17-A23 are 3-state output pins. XA16 is the least
significant bit of the DMA page register and is used
for DMA transfers for 8-bit peripherals only (channel
O-3). XA16 is not used for DMA transfers to 16-bit
peripherals (channel 5-7) as XA9-XA16 is provided
by demultiplexing the data bus. A17-A23 are the
upper 7 bits.of the DMA page register.
76-82 lRQ15-fRQ9 I INTERRUPT REQUESTS: Asynchronous inputs. An
83, 84 IRQ7, IRQ6 I interrupt request is executed by raising an IRQ
1-3 IRQ5-IRQ3 input low to high and holding it high until it is
4 IRQ1 acknowledged (edge triggered mode) or just a high
level on an IRQ input (level triggered mode).
16 INTA I INTERRUPT ACKNOWLEDGE: This pin is used to
enable the interrupt controllers interrupt vector data
on to the data bus by a sequence of interrupt
acknowledge pulses issued by the CPU.
70 INTR o INTERRUPT: This pin goes high whenever a valid
interrupt request is asserted. It is used to interrupt
the CPU, and is usually connected to the CPU’s
interrupt pin.
23 TMRCLK I TIMER CLOCK: Clock input for Counter O, Counter
1 and Counter 2.
22 GATE2 I GATE 2: Gate input for Counter 2. In a PC/AT
compatible design, the Counter 2 is used for tone
generation for speaker. In this design, the GATE 2
input is driven by Bit O of I/0 Port 61H (called
TIM2GATE SPK).
20 OUT1 o OUT 1: Output of Timer 1. In a PC/AT compatible
design, Timer 1 is programmed as a rate generation
to produce 15 Usec period signal used for interrupt
request for refresh cycles. ,

19 OUT 2 0 OUT 2: Output of Timer 2. In a PC/AT compatible

design, OUT 2 is used to drive the speaker.
.

8
 82C206 Pin Description(Continued)

Pin No. Name Type Function

71 As I ADDRESS STROBE: Address strobe is a positive
pulse whose falling edge latches the address from
the XD bus.
72 Oscl I OSCILLATOR INPUT: The time base for the time
functions is connected to this pin. External square
waves of 32.768 KHz may be connected to this
input.
15 PSRSTB I This input is used to establish the condition of the
control registers when power is applied to the
device. In a PC/AT compatible design, this pin
should be tied to the battery back-up circuit.

When PSRSTB and ,TEST are both low, the following

occurs:
(a) Periodic Interrupt Enable (PIE) bit is cleared to
zero.
(b) Alarm Interrupt Enable (AIE) bit is cleared to
zero.
(c) Update ended Interrupt Enable (UIE) bit is
cleared to zero.
(d) Update ended Interrupt Flag (UF) bit is cleared
to zero.
(e) Interrupt Request status Flag (IRQF) is cleared
to zero.
(f) Periodic Interrupt Flag (PF) bit is cleared to
zero.
(9) The part is not accessible.
(h) Alarm interrupt Flag (AF) bit is cleared to zero.
(i) Square Wave output enable list is cleared to
zero.
14 PWRGD I PWRGOOD: The Power Good pin must be high for
bus cycles in which the CPU accessesthe RTC.
When PWRGD is low, all address, data, data strobe
and R/W pins are disconnected from the processor.
17 TEST I TEST: Test is an active high input. It initializes
various internal registersso that the test program
starts in a known state. It should be tied low for
normal operation.
. 32, 75 Vcc — Power Supply
12, 53, 74 Vss — Ground
,

9
 82C206-INTEGRATED to the systemfor such tasks as time keeping
PERIPHERALSCONTROLLER and task switching. Counter 1 may be pro-
The 82C206 is a LSI implementationof the grammedto generatepulsesor squarewaves
standard peripherals required to implement for use by externaldevices.The third channel
an IBM PC/AT system board. This device (Counter 2) is a full function Counter/timer
contains the equivalent of two 8237A DMA which has a gate input for controlling the
Controllers, a 74LS612 Mapper, two 6259A internalcounter.This channelcan be usedas
InterruptControllers,an 8254 Counter/Timer, an interval counter, a timer, or as a gated .

and a MC146818Real Time Clock with RAM. rate/pulse generator.

The 82C206 providesall of the standardperi- A Real Time Clock (RTC) is included in the
pherals required for a system board imple- 82C206 for maintaining the time and date.
mentationexceptthe keyboardinterfacecon- This subsystem also contains 114 bytes of
troller. Figure 1 illustrates the subsystems RAM in addition to the Clock/Calendar.The
containedwithin the 82C206. Clock/Calendar information and RAM are
kept active by connecting the device to an
Two DMA Controllersare providedand con- external batterywhen systempower is turned
nected in such a way as to provide the user off.
with four channelsof DMA (DMA1) for 6-bit
transfersand three channelsof DMA (DMA2) To interconnectand controlall of thesemajor
for 16-bittransfers(the first 16-bitDMA chan- subsystemsa top levelcontrol section is em-
nel is usedfor cascading).Includedas part of ployed which is divided into subsystemsfor
the DMA subsystem is the Page Register purposesof discussion.
(DMAPAGE) devicewhich is used to supple-
ment the DMA and drive the upper address The first section is the Clock and Wait State
lines when required. Control section.This subsystemcontrolsthe
generation of DMA wait statesand the nega-
Sixteen channelsof interruptare providedin tion of IOCHRDY (if programmedto do so)
the 82C206. These channels are partitioned during CPU access of the device. The last
into two cascadedcontrollers(INTC1,1NTC2) subsystemis the Top Level Decode.
with 8 inputs each. Of these 16 channels,
three are connected internallyto variousde- In order to accommodateover200 registersin
vices,allowing 13 user definable channelsof the 82C206and maintainI/0 decodecompati-
interrupt. The three internally connected bility with the IBM PC/AT a multileveldecode
channelsare as follows: scheme is employed. The Top Level Decode
subsystemperformsthe function of genera-
Channel O — Counter/Timer Counter O ting enablesto the varioussubsystems.Con-
Interrupt trol and direction of the XDO-XD7 data bus
Channel 2 — Cascadeto Slave Interrupt buffersare also handled by this subsystem.
Controller (INTC2)
Channel 8 — Real Time Clock Interrupt Each of these subsystemswill now be de-
scribed separately.
The remaining 13 channels may be defined
and utilized as necessaryto meet the users Top Level Decode
specificsystem requirements. The 82C206 Top Level Decode provides 8
separate enables to various subsystemsof
A Counter/Timer (CTC) subsystem is pro- the device. Figure2 containsa truth table for
vided which contains three independent the Top Level Decoder. The enabling of the
counters.All three countersare drivenfrom a 82C206 XDO-XD7output buffers is also con-
clock input pin which is independent from trolled by this section.The output buffersare 4

generated the other clock inputsto the device. Counter enabled wheneveran enable is to
O is connected to interrupt O of INTC1. It is an internal subsystemand the XIOR signalis
intendedto be used as a multi-levelinterrupt asserted.

10
2. Figure 82C206

by The decoder is enabled three signals. Register, and then performing either a read
ACK,
are These three signals XA9and XA8. or write to location 023H.
ACK
be To enable any internal device must
XA9
both
be
must “1’’and and XA8 ’’O”. Configuration Register (023H) (Index O1H)
msb Isb
employed
scheme
decode
82C206
the The in
is designed to comply with the IBM PC/AT b7 b6 b5 b4 b3 b2 b1 bO
requirements and is more fully decoded. If
RW1 RWC)16W116W08W1 8W0 EMR CLK
the user wishes to take advantage of the
areas which are unused by inserting addi-
tional peripherals in the I/0 map, he may do RW1-RWO—When the higher speed CPU’s
so since the subsystemsin the 82C206 will are accessing the 82C206, the cycle can be
not respond to the unused address spaces extended by programming up to four wait
established by the Top Level Decoder. The states into the Configuration Register, This
extra peripherals may be tied directly to the will cause the 82C206 to assert a not ready
XDO-XD7data lines since the 82C206 output condition on IOCHRDY (low) whenever a
buffers are not enabled unless an internal valid decode from the Top Level Decoder is
subsystem is enabled. detected and either XIOR or XIOW is as-
serted. IOCHRDY will remain low for the
Clock and Wait State Control number of wait states programmed into the
The Clock and Wait State Control subsystem Configuration Register bits 6 and 7.
performs four functions, control of the DMA
command width, control of the CPU read or
write cycle length, and selection of the DMA
clock rate. All of these functions are user
selectable by writing to the Configuration
Register located at address 023H.

Writing and reading this register is accom-

plished by first writing a O1H to location
022H to select the 82C206 Configuration
Wait states are in increments of one SCLK
cycle and are not affected by the DMA Clock
Divider. I
I
 internal synchronizer controls the actual
switching of the clock to prevent a short
clock pulsefrom causinga DMA malfunction.

The ConfigurationRegistercontentsare pre- .

loaded by RESET to an initial value of OCO
hex. This value establishesa default which is
IBM PC/AT compatibleand correspondsto: ,
Read/Write cycles 4 wait states
16-bit DMA transfers —1 wait state
8-bit DMA transfers —1 wait state
DMAMEMR delayed 1 DMA clock cycle
later than XIOR
DMA clock is equal to SCLK/2

DMA FUNCTIONAL DESCRIPTION

The equivalentof two 8237A DMA Controllers
is implementedin the 82C206. Eachcontroller
is a four channel DMA device which will
generate the memory addressesand control
Furthercontrolof the cycle length is available signals necessaryto transfer informationbe-
through the use of the IOCHRDY pin on the tween a peripheraldeviceand memorydirect-
82C206. During DMA this pin is used as an ly.This allowshighspeed informationtransfer
input to the wait state generation logic to with little CPU intervention.
extend the cycle if necessary.This input is
driven low (0) by the peripheralto extend the The two DMA Controllers are internallycas-
cycle. The cycle can then be completed by caded to provide four DMA channels for
releasingIOCHRDY and allowing it to return transfers to 8-bit peripherals (DMA1), and
high (l). three channels for transfers to 16-bit peri-
pherals (DMA2). DMA2 Channel O provides
EMR—This bit enables the extended the cascade interconnectionof the two DMA
DMAMEMR function. Normally the assertion devices,therebymaintainingIBM PC/ATcom-
of DMAMEMR is delayed one clock cycle patibility.
laterthan XIOR in the IBM PC/ATimplementa-
tion. This may not be desirable in some sys- DMA cycle lengthcontrolis providedinternal-
allowing tems. A “l” programmed into this bit posi- ly in the 82C206 independentcontrol
tion will start DMAMEMR at the same time as for both 8-bit and 16-bit cycles. This is done
XlOR. through the programmable registers which
can extend command signals or insert wait
CLK—This bit allows the user to insert a states.
divider between the DMA Controller subsys-
tems and the SCLK input pin, or connect the Each DMA Channel has a pair of 16-bit
two directly.When this bit positioncontainsa counters and a reload register for each
“O”,the SCLK input is divided by two and is counter. The 16-bit counters allow the DMA
used to drive both the 8-bit and 16-bit DMA to transfer blocks as large as 65536 words.
subsystems.A “l” in this position bypasses The register associated with each counter
the divider and usesthe SCLK input directly. allows the channel to reinitialize without re-
Wheneverthe state of this bit is changed, an programming.

12
 1
From this point on the description of the length and the number of states in a cycle
DMA subsystempertainsto both DMA1 and will vary depending on how the device is
DMA2”unlessotherwisenoted. programmedand what type of cycle is being
performed.The statesare labeled S0-S4 and
DMA Operation will be explainedin detail.in the section en-
During normal operation of the 82C206, the titled Active Condition.
DMA subsystem will be in either the Idle
,
condition,the Programconditionor the Active Idle Condition
condition. In the Idle conditionthe DMA con- When no device is requesting service the
troller will be executing cycles consistingof DMA is in an Idle condition which maintains
only one state.The idle state SI is thedefault the state machine in the SI state. During this
condition and the DMA will remain in this time the 82C206 will sample the DREQ input
condition unless the device has been initia- pins every clock cycle. The internal select
lizedand one of the DMA requestsis activeor from the top leveldecoderand HLDA are also
. the CPU attempts to access one of the in- sampled at the same time to determineif the
ternal registers. CPU isattemptingto accessthe internalregis-
ters. When either of the above two situations
When a DMA request becomes active the occurs, the DMA will exit the Idle condition.
device entersthe Activeconditionand issues Note that the Program condition has priorit
a hold request to the system. Once in the over the Active condition since a CPU cycle
Activeconditionthe 82C206 will generatethe has already started.
necessarymemory addressesand command
signalsto accomplisha memory-to 1/0, l/O- Program Condition
to-memory,or a memory-to-memorytransfer. The Program condition is entered whenever
Memory-to-l/O and I/O-to-memory transfers HLDA is inactive and an. internal select is
take place in one cycle while memory-to- active. The internalselect is derived from the
memory transfersrequire two cycles. During top leveldecode describedpreviously.During
transfers between memory and 1/0, data is this time address lines XAO-XA3 become in-
presentedon the systembus by either mem- puts if DMAI is selected,or XA1-XA4 become
ory or the requestingdevice and the transfer inputsif DMA2 is selected.Note, when DMA2
is completed in one cycle. Memory-to- is selected XAO is ignored. These address
memory transfershowever,require the DMA inputs are used to select the DMA controller
to store data from the read operation in an registers which are to be read or written.
internal register.The contentsof this register Figure3 liststhe registeraddressassignment.
is then written to memory on the subsequent Due to the large number of internal registers
cycle. in the DMA subsystem,an internal flip-flop is
used to supplement the addressing of the
During transfers between memory and 1/0, count and address registers.This bit is used
two commandsare activatedduring the same to select between the high and low bytes of
cycle. In the caseof a memory-to-l/O transfer, these registers.The flip-flop will toggle each
the 82C206 will assert both DMAMEMR and time a read or write occursto any of the word
XIOW allowing data to be transfereddirectly count or address registers in the DMA. This
to the requestingdevice from memory. Note internal flip-flop will be cleared by hardware
that 82C206 does not latch data from nor RESET or a Master Clear command and may
drive data out on this type of cycle. be set or cleared by the CPU issuing the
appropriate command.
The numberof clock cyclesrequiredto trans-
fer a word of data maybe varied by program- Specialcommandsare supportedby the DMA
* ing the DMA or, optionally extended by the subsystemin the Program condition to con-
peripheraldevice. During an Active cycle the trol the device.These commandsdo not make
DMA will sequencethrough a seriesof states. use of the data bus but are derivedfrom a set
Each state will be one DMA clock cycle in of addresses,the internalselectand XIOW or

13
 *

14
 XIOR. These commands are Master Clear, by channel basis to operate in one of four
Clear Mask Register, Clear Mode Register modes. The four modesare listed below.
Counter,Set and Clear Byte PointerFlip-Flop.
Single WansferMode-This mode directsthe
The 82C206 will enable programming when- DMA to execute only one transfer cycle at a
ever HLDA has been inactive for one DMA time. DREQ must be held active until DACK
clock cycle. It is the responsibility of the becomes active. If DREQ is held active
9 system to ensure that programming and throughoutthe cycle,the 82C206 will deassert
HLDA are mutually exclusive. Erratic opera- HRQ and releasethe bus once the transferis
tion of the 82C206 can occur if a requestfor complete. After HLDA has gone inactivethe
service occurs on an unmasked channel 82C206 will again assert HRQ and execute
which is being programmed. The channel another cycle on the same channel unlessa
should be masked or the DMA disabled to request from a higher priority channel has
preventthe 82C206from attemptingto service been received. In this mode the CPU is en-
a device with a channel which is partially sured of being allowed to execute at least
programmed. one bus cycle betweentransfers.

Active Condition Following each transfer the word count is

The 82C206 DMA subsystementersthe Active decrementedand the addressis incremented
conditionwhenevera softwarerequestoccurs or decremented.When the word count decre-
or a DMA request on an unmasked channel mentsfromOOOOh to FFFFhthe terminalcount
occurs and the device is not in the Program bit in the statusregisteris set and a T/C:pulse
condition.The 82C206 will then begin a DMA is generated. If the autoinitialization option
transfer cycle. has been enabled,the channelwill reinitialize
itself.If Autoinitializeis not selectedthe DMA
In a read cycle for example, after receivinga will set the DMA request bit mask and sus-
DREQ, the 82C206 will issue a HRQ to the pend transferringon that channel.
system. Until a HLDA is returned the DMA
will remain in an idle condition. On the next Block transfer Mode--When Block Transfer
clock cycle the DMA will exit Idle and enter Mode is selected,the 82C206 will begintrans-
state SO. During SO the device will resolve fers in responseto either a DREQ or a soft-
priorityand issueDACKon the highestpriori- ware requestand will continueuntila terminal
ty channel requestingservice.The DMA will count (FFFFh) is reached, at which time T/C
then proceed to state S1 where the multi- is pulsed and the status register terminal
plexed addresses are output and latched. count bit is set. In this mode DREQ need only
State S2 is then entered, at which time the be held active until DACK is asserted.Auto-
82C206 will assert DMAMEMR. The device initializationis optional in this mode also.
then transitions into S3 where the XIOW
command is asserted.The 82C206 DMA will Demand TransferMode-in Demand Transfer
then remainin S3 until the Wait State Counter mode the DMA will begin transfers in re-
has decremented to zero and IOCHRDY is sponse to the assertion of DREQ and will
true. Note that at least one additional S3 will continueuntileitherterminalcount is reached
occur unlessCompressedTiming is selected. or DREQ becomes inactive. This mode is
Once a ready condition is detected,the DMA normally used for peripherals which have
will enter S4 where both commands are re- limited ‘bufferingability. The peripheral can
asserted. In Burst Mode and Demand Mode initiatea transferand continue until its buffer
(discussed below), subsequent cycles will capacity is exhausted. The peripheral may
beginin S2 unlessthe intermediateaddresses then re-establishservice by again asserting
, require updating. In these subsequentcycles DREQ. During idle periodsbetweentransfers
the lower addressesare changed in S2. the CPU is releasedto operateand can moni-
tor the operation by reading intermediate
The DMA can be programmedon a channel valuesfromthe addressand word count ,=regis-

15
 ters. Once DREQ has beenreasserted,higher
priority channels are allowed to intervene.
Reaching terminal count will result in the
generation of a T/C pulse, the setting of the
terminal count bit in the status register and
autoinitialization(if enabled).
Cascade Mode—This mode is used to inter-
connect more than one DMA controller, to
extend the number of DMA channels while
preserving the priority chain. In Cascade
mode the master DMA controller does not
generate address or control signals. The
DREQ and DACK signals of the master are
used to interfacethe HRQ and HLDA signals
.. of the slave DMA devices. Once the master
has received a HLDA from the CPU in re-
sponseto a DREQ causedby the HRQ from a
slave DMA controller,the master DMA con-
trollerwill ignoreall inputsexcept HLDA from
the CPU and DREQ on the active channel.
This prevents conflicts between the DMA
devices.

Figure 4 shows the cascade interconnection Figure4. CascadeMode Interconnect

for two levels of DMA devices. Note that
Channel O of DMA2 is internally connected
for Cascade mode to DMA1. Additional de- ReadTransfer-Read transfersmovedata from
vices can be cascadedto the availablechan- memory to an 1/0 device, by generating the
nels in either DMA1 or DMA2 since cascade memory address and asserting DMAMEMR
is not limitedto two levelsof DMA controllers. and XIOW during the same cycle.

When programming cascaded controllers, Write Transfer—Write transfers move data

begin with the device which is actually gen- from an 1/0 device to memory by generating
erating HRQ to the system(first level device) the memory addressand assertingXIOR and
and then proceedto the secondleveldevices. DMAMEMW.
RESET causesthe DACK outputsto become
active low and are placed in the inactive Memory-to-Memory Transfer—The memory-
state. To allow the internal cascade between to-memory transfer is used to move a block
DMA1 and DMA2 to function correctly, the of memory from one location in memory to
active low stateof DACK shouldnot be modi- another. DMA channelsO and 1 may be pro-
fied. This is becausethe 82C206 has an in- grammed to operate as memory-to-memory
verterbetweenDACKOof DMA2 and HLDA of channels by setting a bit in the Command
DMA1. The first level device’s DMA request Register. Once programmed to perform a
mask bits will preventsecond level cascaded memory-to-memorytransferthe processcan
devices from generating unwanted hold re- be started by generatingeither a softwareor
questsduring the initializationprocess. an external request to channel O. Once the
transfer is initiated, Channel O provides the
DMA Transfers addressfor the sourceblockduring the mem-
Four types of transfermodesare providedin ory read portion of the cycle. Channel 1 gen-
the 82C206 DMA subsystem.These transfer eratesthe addressfor the memorywrite cycle.
types are: During the read cycle, a byte of data is

16
 latched in the internalTemporaryRegisterof DREQ priority
the 82C206. The contentsof this registerare The 82C206 supportstwo schemesfor estab-
then output on the XDO-7 data lines during IishingDREQ priority.The firstis fixed priority
the write portionof the cycle and subsequent- whichassignsprioritybasedon channelposi-
ly written to memory.Channel O may be pro- tion. In this method Channel O is assigned
grammed to maintain the same source ad- the highest priority. Priority assignmentthen
dresson every cycle. This allows the CPU to progressesdownward through the channels
initalizelargeblocksof memorywith the same in order with Channel 3 receivingthe lowest
value. The 82C206 will continue performing priority.
transfer cycles until Channel 1 reaches ter-
minal count. The second type of priority assignment is
rotating priority. In this scheme the ordering
Verifytransfer-The verifytransferisa pseudo- of priority from Channel O to Channel 3 is
transfer which is useful for diagnostics. In maintainedbut the actualassignmentof prior-
.4
this type of transferthe DMA will operateas if ity changes. The channel most recently ser-
it is performing a Read or Write Transfer by viced will be assignedthe lowestpriority’and,
generating HRQ, addresses and DACK but sincethe order of priorityassignmentremains
will do so without assertinga command sig- fixed, the remaining three channels rotate
nal. Since no transfer actually takes place accordingly.The rotating priority assignment
IOCHRDY is ignored during Verify transfer is illustratedin Figure 5.
cycles.
In instanceswhere multiple requestsoccur at
Autoinitializetion the same time the 82C206 will issue a HRQ
Each of the four DMA channel Mode Regis- but will not freeze the priority logic until
ters containsa bit which will cause the chan- HLDA is returned. Once HDLA becomesac-
nel to reinitializeafterreachingterminalcount. tive the priority logic is frozen and DACK is
Duringthis process,referredto as Autoinitaili- asserted on the highest requesting channel.
zation, the Base Address and Base Word Priority will not be re-evaluated until HLDA
Count Registers,whichwere originallywritten has been deactivated.
by the CPU, are reloaded into the Current
Address and Current Word Count Registers
(both the base and current registers are AddressGeneration
loaded during a CPU write cycle). The base Eight intermediate bits of the address are
registers remain unchanged during DMA multiplexedonto the data lines during Active
Activecyclesand can only be changed by the cycles of the DMA. This reducesthe number
CPU. If the channel has been programmedto of pins required by the DMA subsystem.
autoinitialize,the requestmask bit will not be During state S1, the intermediate addresses
set upon reachingterminalcount.This allows are output on data lines XDO-XD7.These ad-
the DMA to continue operation without CPU dressesshouldbe externallylatchedand used
intervention. to drivethe systemaddressbus. Since DMA1
is used to transfer 8-bit data and DMA2 is
During memory-to-memory transfers the used to transfer 16-bit data, a one bit skew
Word Count Registersof both Channel Oand occurs in the intermediate address fields.
Channel 1 must be programmed with the DMA1 will thereforeoutput addressesA8-A15
samestartingvaluefor full autoinitialization.If on the data bus at this time whereas DMA2
Channel O reaches terminal count before will output A9-A16. A separate set of latch
Channel 1, then Channel O will reload the and enable signals are provided for both
startingaddressand word count and continue DMA1 and DMA2 to accommodate the ad-
transferring data from the beginning of the dress skew.
.

source block. Should Channel 1 reach termi-

nal count first, it will reload the current regis- During 8-bit DMA cycles, in which DMA1 is
ters and Channel O will remain uninitialized. active,the 82C206 will output the lower8-bits

17
Channel O

Channel 2 Channel O Channel 1

Channel 3 Channel 1 Channel 2 Lowest

Figure 5. Rotating Priority Scheme

of address on XAO-XA7.The intermediate8-

bits of address will be output on XDO-XD7
Address RegisterFunction
and ADSTB8 will be asserted for one DMA 080h Unused
clock cycle. The falling edge of ADSTB8 is
used to latch the intermediateaddressesA8- 081h 8-bit DMA Channel 2 (DACK2}
A15. An enable signal,AEN8, is used to con- 082h 8-bit DMA Channel 3 (DACK3)
trol the output drivers of the external latch.
083h 8-bit DMA Channel 1 (DACK1)
A16-A23are also generated at this time from
a DMA Page Register in the 82C206. Note 084h Unused
that A16 is output on the XA16 pin of the 085h Unused
device.
086h Unused
16-bit DMA cycles from DMA2 require the 087h 8-bit DMA Channel O (DACKO)
82C206 to output the lower 8-bits of the ad-
088h Unused
dress on XA1-XA8. The intermediateaddres-
ses A9-A16 are output on XDO-XD7.Control 089h 16-bit DMA Channel 2 (DACK6)
for a separate latch is provided by signals 08Ah 16-bit DMA Channel 3 (DACK7)
ADSTB16 and AEN16. The DMA Page Regis-
ter now generates A17-A23. During 16-bit 08Bh 16-bit DMA Channel 1 (DACK5)
DMA transfersXAOand XA16 remain inactive. 08Ch Unused
The DMA Page Register is a set of 16 8-bit 08Dh Unused
registers in the 82C206 which are used to 08Eh Unused
generate the high order addresses during
08Fh Refresh Cycle
DMA cycles. Only 8 of the registersare actu-
ally used but all 16 were includedto maintain
IBM PC/AT compatibility.Each DMA channel Figure 6.
has a register associated with it with the DMA AddressExtensionRegisterMap
exception of Channel O of DMA2 which is
used for internalcascadingto DMA1. Assign- During Demand and Block Transfers, the ,
ment of each of these registersis shown in 82C206 generates multiple sequentialtrans-
Figure 6 along with its Read/Writeaddress. fers. For most of these transfersthe informa-

18
.
tion in the external address latches will re- Register which determines the number of
main the same, eliminating the need to be transfers to perform. The actual number of
relatched. Since the need to update the transfers performed will be one greater than
latches occurs only when a carry or borrow the value programmed into the register.The
from the lower 8-bits of the AddressCounter register is decremented after each transfer
exists,the 82C206 will only update the latch until it goes from zero to FFFFh. When this
contents when necessary.The 82C206 will roll-overoccursthe 82C206 will generateT/C
therefore, only execute S1 cycles when nec- and either suspendoperationon that channel
essary, resulting in an overall through-put and set the appropriate Request Mask Bit or
improvement. Autoinitializeand continue.

CompressedTiming Base AddressRegister

The DMA subsystemin the 82C206 can be Associatedwith each Current AddressRegis-
programmedto transfera word in as few as 3 ter is a BaseAddressRegister.This is a write
DMA clock cycles. The normal DMA cycle only register which is loaded by the CPU
consistsof three states:S2, S3, and S4 (this when writingto the CurrentAddressRegister.
assumes Demand or Block Transfer Mode). The purpose of this register is to store the
Normal transfersrequire4 DMA clock cycles initial value of the Current Address Register
since S3 is executed twice due to the 1 wait for Autoinitialization. The contents of this
stateinsertion.In systemscapableof support- register are loaded into the Current Address
ing higher through-put, the 82C206 can be Registerwheneverterminal count is reached
programmedto omit one S3 and assertboth’ and the AutoinitializeBit is set.
commands in S2. S2 begins the cycle by
generating the address and asserting both
BaseWord Count Register
commands.One S3 cycle is executedand the
cycle terminatesin S4. If CompressedTiming This registerpreservesthe initial value of the
is selected, T/C will be output in S2 and S1 CurrentWord Count Register.It is also a write
cycles will be executed as necessaryto up- only registerwhich is loaded by writingto the
date the addresslatch.Note that Compressed Current Word Count Register.This register is
Timing is not“allowedfor memory-to-memory loaded into the Current Word Count Register
transfers, during Autoinitialization.

Register Description Command Register

Current AddressRegister
This registercontrolsthe overall operationof
Each DMA channel has a 16-bit Current a DMA subsystem.The register can be read
Address Register which holds the address or written by the CPU and is cleared by either
used during transfers. Each channel can be RESET or a Master Clear command.
programmedto increment or decrement this
register whenever a transfer is completed. msb Isb
This register can be read or written by the
CPU in consecutive 8-bit bytes. If Autoini- b7 b6 b5 b4 b3 b2 b1
tialization is selected, this register will be DAK DRQ EW RP CT CD AH M-x
reloaded from the Base Address Register
upon reaching terminal count in the Current
Word Count Register.Channel O can be pre- DAK—DACK active level is determined by
ventedfrom incrementingor decrementingby bit 7. Programming a 1 in this bit position
settingthe AddressHold Bit in the Command makes DACK an active high signal.
Register.
DRQ—DREQ active level is determined by
Current Word Count Register bit 6. Writing a 1 in this bit position causes
Each channel has a Current Word Count DREQ to become active low.

19
EW—ExtendedWrite is enabled by writing a Ml-MO—Mode selection for each channel is
1 to bit 5, causingthe write commandsto be accomplished by bits 6 and 7.
asserted one DMA cycle earlier during a
transfer.The read and write commands both
begin in state S2 when enabled. Ml MO MODE
RP—Writing a 1 to bit 4 causes the 82C206 o 0 Demand Mode
to utilize a rotating priority scheme for 1
o Single Cycle Mode
honoring DMA requests.The default condi-
tion is fixed priority. 1 0 Block Mode
1 1 Cascade Mode
CT—Compressedtiming is enabled by writ-
ing a 1 to bit 3 of this register.The default O
condition causes the DMA to operate with DEC—Determines direction of the address
normal timing. counter. A one in bit 5 decrements the ad-
dress after each transfer.
CD—Bit 2 is the masterdisable for the DMA
controller. Writing a 1 to this location dis- Al—The Autoinitializationfunction is enabled
ables the DMA subsystem(DMA1 or DMA2). by writing a 1 in bit 4 of the Mode Register.
This function is normally used whenever the
CPU needsto reprogramone of the channels TT1-TTO-Bits 2 and 3 control the type of
to prevent DMA cycles from occuring. transfer which is to be performed.

AH—Writing a 1 to bit 1 enables the address

hold feature in Channel O when performing TT1 TTO TYPE
memory-to-memory transfers.
o 0 Verify Transfer
M-M—A 1 in the bit O position enables o 1 Write Transfer
Channel O and Channel 1 to be used for 1 0 Read Transfer
memory-to-memory transfers.
1 1 Ilegal
Mode Register
Each DMA channel has a Mode Register CS1-CSO—Channel Select bits 1 and O
associated with it. All four Mode Registers determine which channel’s Mode Register
reside at the same I/0 address. Bits O and 1 will be written. Read back of a mode register
of the Write Mode Register command de- will result in bits 1 and O both being ones.
termine which channel’sMode Register gets
written. The remaining six bits control the
mode of the selected channel. Each chan- Cs1 Cso CHANNEL
nel’s Mode Registercan be read by sequen-
tially reading the Mode Register location. A o 0 Channel O select
Clear Mode Register Counter command is o 1 Channel 1 select
provided to allow the CPU to restart the
1 0 Channel 2 select
mode read processat a known point. During
mode read operations, bits Oand 1 will both 1 1 Channel 3 select
be 1.
msb Isb Request Register

b7 b6 b5 b4 b3 b2 b1 bO This is a four bit register used to generate

software requests (DMA service can be re-
Ml MO DEC Al TT1 TTO CS1 CSO quested either externally or under software
(Read/Write Register) control). Request Register bits can be setor

20
 —
.

reset independently by the CPU. The Re- This register can be programmed in two
quest Mask has no effect on software ge- ways. Each channel can be independently
nerated requests. All four bits are read in masked by writing to the Write Single Mask
one operation and appear in the lower four Bit location. The data format for this oper-
bits of the byte. Bits 4 through 7 are read as ation is shown below.
ones.All four requestbitsare cleared to zero
by RESET msb Isb
b7 b6 b5 b4 b3 b2 b1 b0
msb Isb
Xxxx X MB MS1 MS0
b7 b6 b5 b4 b3 b2 b1 bO
(Set/Reset Operation) —
Xxxx X RB RS1 RSO
(Write Operation) MB—Bit 2 sets or resets the request mask
bit for the channel selected by MSI and
RB—The request bit is set by writing a 1 to MSO.Writing a 1 in this bit position sets the
bit 2. RS1-RSOselect which bit (channel) is mask, inhibiting external requests.
to be manipulated.
MS1-MSO—Thesetwo bitsselect the specific
RSl-RSO—ChannelSelect Oand 1 determine mask bit which is to be set or reset.
which channel’s Mode Register will be writ-
ten. React back of the mode register will
result in bits O and 1 both being ones. Ms1 Mso CHANNEL
o 0 Channel O select
Rs1 Rso CHANNEL o 1 Channel 1 select
o 0 Channel O select 1 0 Channel 2 select
o 1 Channel 1 select 1 1 Channel 3 select
1 0 Channel 2 select
“1 1 Channel 3 select Alternatively all four mask bits can be pro-
grammed in one operation by writing to the
Write All Mask Bits address. Data format for
Format for the Request Register read opera- this and the Read All Mask Bits function is
tion is shown below. shown below.
msb Isb msb Isb
b7 b6 b5 b4 b3 b2 b1 bO b7 b6 b5 b4 b3 b2 b1 b0
111 1 RC3 RC2 RC1 RCO xxx X MB3 MB2 MB1 MB0
(Read Operation) (Read/Write Operation)
RC3-RCO—Duringa Request Register read, MB3-MBO—Eachbit position in the field rep-
the state of the request bit associated with resentsthe mask bit of a channel. The mask
each channel is returned in bits Othrough 3 bit numbercorrespondsto the channel num-
of the byte. The bit position corresponds to ber associated with the mask bit.
I
the channel number.
All four mask bits are set following a RESET
Request Mask Register or a Master Clear command. Individualchan-
.
The Request mask register is a set of four nel mask bits will be set as a result of termi-
bits which are used to inhibit external DMA nal count being reached, if Autoinitialize is
requests from generating transfer cycles. disabled. The entire register can be cleared,

21
 enabling all four channels, by performing a low byte of the register and allows the CPU
Clear Mask Register operation. to read or write the register bytes in correct
sequence.
Status Register
The statusof all four channels can be deter- Set Byte Pointer Flip-Flop—Setting the Byte
mined by reading the Status Register.infor- Pointer Flip-Flop allows the CPU to adjust
mation is availableto determine if a channel the pointer to the high byte of an addressor
has reached terminal count and whether an word count register.
external service request is pending. Bits O-3
of this registerare cleared by RESET,Master Master Clear—This command has the same
Clear or each time a StatusRead takes place. effect as a hardware RESET.The Command
Bits 4-7 are cleared by RESET Master Clear Register, Status Register, Request Register,
or the pending request being reasserted. Temporary Register,Mode Register Counter
Bits 4-7 are not affected by the state of the and Byte Pointer Flip-Flop are cleared and
Mask Register Bits. The channel number the Request Mask Register is set. immedi-
.
correspondsto the bit position. ately following Master Clear or RESET the
DMA will be in the idle Condition.
msb Isb
Clear Request Mask Register—This com-
b7 b6 b5 b4 b3 b2 b1 b0 mand enables all four DMA channels to ac-
DRQ3DRQ2DRQ1DRQO TC3 TC2 TC1 TCO cept requests by clearing the mask bits in
the register.
(Read Only Register)

Temporary Register Clear Mode Register Counter—In order to

allow access to four Mode Registers while
The Temporary Register is used as a tempo- only using one address,an additional count-
rary holding register for data during er is used. After clearing the counter all four
memory-to-memory transfers. The register Mode Registers may be read by doing suc-
is loaded during the first cycle of a memory- cessive reads to the Read Mode Register
to-memory transfer from XDO-XD7. During address. The order in which the registers
the second cycle of the transfer, the data in will be read is Channel O first, Channel 3
the Temporary Register is output on the last.
XDO-XD7 pins. Data from the last memory-
to-memorytransferwill remain in the register
unless a RESET or Master Clear occurs. INTERRUPT CONTROLLER
FUNCTIONAL DESCRIPTION
Special Commands The programmableinterruptcontrollersin the
Five Special Commands are provided to 82C206 function as a system wide interrupt
make the task of programming the device manager in an iAPX86 system. They accept
easier. These commands are activated as a requestsfrom peripherals,resolvepriorityon
result of a specific address and assertion of pending interruptsand interruptsin service,
either a XIOR or XIOW. Information on the issue an interrupt request to the CPU, and
data lines is ignored by the 82C206 when- providea vectorwhich is usedas an indexby
ever an XIOW activated command is issued, the CPU to determinewhich interruptservice
thus data returned on XIOR activated com- routine to execute.
mands is invalid.
A variety of priority assignment modes are
Clear Byte Pointer Flip-Flop—Thiscommand provided,which can be reconfiguredat any
is normallyexecuted prior to reading or writ- time during system operation, allowing the
.
ing to the address or word count registers. complete interrupt subsystemto be restruc-
This initializes the flip-flop to point to the tured, based on the systemenvironment.

22
Overview Description of the Interrupt Subsystem will
Two interruptcontrollers,INTC1 and INTC2, pertain to both INTC1 and INTC2 unless
are included in the 82C206. Each of the inter- otherwise noted. Wherever registeraddress-
rupt controllers is equivalent to an 8259A es are used,the addressfor the INTG1 regis-
device operating in iAPX86 Mode. The two ter will be listed first and the addressfor the
devicesare interconnectedand must be pro- INTC2 register will follow in parenthesis.
grammed to operate in Cascade Mode (see Example 020H (OAOH)
Figure 7) for proper operation of all 16 inter-
rupt channels.INTC1 is located at addresses Controller Operation
020H-021H and is configured for Master op- Figure 9 is a block diagram of the major
eration (defined below) in Cascade Mode. elements in the interrupt controller. The
INTC2 is a Slave device (defined below) and Interrupt Request Register (lRR) is used to
is located at OAOH-OAIH.The Interrupt Re- store requestsfrom all of the channelswhich
quest output signal from INTC2 (lNT) is in- are requesting service. Interrupt Request
ternally connected to the interrupt request Register bits are labeled using the Channel
input Channel 2 (IR2) of INTC1. The address Name IR7-IRO.The In-Service Register (ISR)
decodingand Cascadeinterconnectionmatch- containsall the channelswhich are currently
es that of the IBM PC/AT being serviced (more than one channel can
be in service at a time). In-Service Register
Two additional interconnectionsare made to bits are labeled 1S7-1S0and correspond to
the interrupt request inputs of the interrupt IR7-IRO. The Interrupt Mask Register (IMR)
controllers. The output of Timer O in the allows the CPU to disable any or all of the
Counter/Timer subsystem is connected to interrupt channels. The Priority Resolver
Channel O (IRO) of INTC1. Interrupt request evaluates inputs from the above three regis-
from the Real Time Clock is connected to ters, issuesan interrupt request, and latches
Channel O (IRO) of INTC2. Figure 8 lists the the corresponding bit into the In-Service
16 interrupt channels and their interrupt re- Register. During interrupt acknowledge cy-
quest source. cles, a master controller outputs a code to
the slave device which is compared in the
Cascade Buffer/Comparator with a three bit
ID code previouslywritten. If a match occurs
imi. -D
in the slave controller, it will ‘generate an
interrupt vector. The contents of the Vector
Register are used to provide the CPU with
an interruptvectorduring Interrupt Acknowl-
edge (INTA) cycles.

Interrupt Sequence
The 82C206 allows the CPU to perform an
indirectjump to a serviceroutine in response
to a request for service from a peripheral
device. The indirect jump is based on a
vector which is provided by the 82C206 on
the second of two CPU generated INTA
cycles (the first INTA cycle is used for re-
solving priority and the second cycle is for
transferring the vector to the CPU. The
events which occur during an interrupt se-
quence are as follows:

l—One or more of the interrupt requests

23
 INTC1 IRO Counter/Timer OutO
INTC1 IR1 IRQ1 Input Pin
tNTCl IR2 INTC2 Cascade Interrupt
INTC1 IR3 IRQ3 Input Pin
INTC1 IR4 IRQ4 input Pin
INTC1 IR5 IRQ5 Input Pin
INTC1 IR6 IRQ6 Input Pin
INTC1 IR7 IRQ7 Input Pin
. INTC2 IRO Real Time Clock IRQ
INTC2 IR1 IRQ9 input Pin
INTC2 IR2 IRQ1O Input Pin
INTC2 IR3 IRQ1l Input Pin
INTC2 IR4 IRQ12 Input Pin
INTC2 IR5 IRQ13 Input Pin
INTC2 IR6 IRQ14 Input Pin
INTC2 IR7 IRQ15 Input Pin

Figure 8. Interrupt Request Source

(IR7-IRO) becomes active, setting the cor- Word 2 (see Initialization Command Words
responding IRR bit(s). section below).

2—The interrupt controller resolves priority 6—At the end of the second INTA cycle, the
based on the state of the IRR, IMR and ISR ISR bit will be cleared if the Automatic End
and asserts the INTR output if appropriate. Of Interrupt mode is selected (see End Of
Interrupt section below). Otherwise, the ISR
3—The CPU accepts the interrupt and re- bit must be cleared by an End Of Interrupt
sponds with an INTA cycle. (EOI) command from the CPU at the end of
the interrupt service routine.
4—During the first INTA cycle, the highest
priority ISR bit is set and the corresponding If no interrupt request is present at the be-
IRR bit is reset. The internal Cascade ad- ginning of the first INTA cycle (i.e., a spu-
dress is generated and the XD7-XDOoutputs rious interrupt) INTC1 will issue an interrupt
remain tri-stated. level 7 vector during the second INTA cycle.

5—The CPU will execute a second INTA End Of Interrupt

cycle, during which the 82C206 will drive an EOI is defined as the condition which causes
8-bit vector onto the data pins XD7-XDO, an ISR bit to be reset. Determination of
which is in turn latched by the CPU. The which ISR bit is to be reset can be done by a
format of this vector is shown in Figure 12. CPU command (specific EOI) or, the Priority
Note that V7-V3 in Figure 12 are program- Resolver can be instructed to clear the
mable by writing to Initialization Control highest priority ISR bit (non-specific EOI),

24
 service routine. An ISR bit that is masked, in
Special Mask Mode by a IMR bit, will not be
cleared by a non-specific EOI command.
The interrupt controller can optionally gen-
erate an Automatic End Of Interrupt (AEC)I)
on the trailing edge of the second INTA
cycle.

Priority Assignment
Assignment of priority is based on an inter-
rupt channel’s position relative to the other
channels in the interrupt controller.After the
initialization sequence, IRO has the highest
priority, IR7 has the lowest, and priority as-
signment is fixed (Fixed Priority Mode).
Priority assignment can be rotated either
manually (Specific Rotation Mode) or auto-
matically (Automatic Rotation Mode) by pro-
gramming operational Command Word 2
(OCW2).

Fixed Priority Mode—This is the default con-

dition which exists unless rotation (either
manual or automatic) is enabled, or the con-
troller is programmed for Polled Mode. In
Fixed Priority Mode, interrupts are fully
nested with priority assigned as shown:

Lowest Highest
priority Status 7 6 5 4 3 2 1 0

Nesting allows interruptsof a higher priority

to generate interrupt requests prior to the
completion of the interrupt in service. When
an interrupt is acknowledged, priority is re-
solved, the highest priority request’s vector
is placed on the bus and the ISR bit for that
channel is set. This bit remains set until an
EOI (automatic or CPU generated) is issued
to that channel. While the ISR bit is set, all
interrupts of equal or lower priority are in-
hibited. Note that a higher priority interrupt
which occurs during an interrupt service
The 82C206 can determine the correct ISR routine, will only be acknowledged if the
bit to reset when operated in modes which CPU has internally re-enabled interrupts.
do not alter the fully nested structure, since
the current highest priority ISR bit is neces- SpecificRotationMode-Specific Rotational-
sarily the last level acknowledged and ser- lows the systemsoftwareto re-assignpriority
viced. In conditions where the fully nested levelsby issuinga command which redefines
structure is not preserved, a specific EOI the highest priority channel.
mustbe generatedat the end of the interrupt

25
 .

Before Rotation Word (ICW1) to address020H (OAOH)with a

Lowest Highest 1 on bit 4 of the data byte. The interrupt
controller interprets this as the start of an
Priority Status 7 6543210 initializationsequenceand doesthe following:
(Specific Rotation command issued with .
Channel 5 specified) l—The InitializationCommandWord Coun-
After Rotation ter is reset to zero.
2—ICW1 is latched into the device
Lowest Highest 3—Fixed Priority Mode is selected
Priority Status 5 4321076 4—IR7 is assignedthe highest priority
5—The Interrupt Mask Register is cleared
Automatic Rotation Mode—In applications 6-The Slave Mode Address is set to 7
where a number of equal priority peripherals 7—Special Mask Mode is disabled
are requestinginterrupts,AutomaticRotation 8—The IRR is selected for Status Read
may be used to equalize the priority assign- operations
ment. In this mode a peripheral, after being
serviced, is assigned the lowest priority. All The next three I/0 writes to address 021H
peripherals connected to the controller will (OAIH) will load ICW2-ICW4. See Figure 11
be serviced at least once in 8 interrupt re- for a flow chart of the initializationsequence.
queststo the CPU from the controller.Auto- The initializationsequencecan be terminated
if matic rotationwill occur, enabled,due to the START
occurrence of EOI (automatic or CPU gen-
erated).

Before Rotation (IR4 is highest priority re-

quest being serviced)

ISR Status Bit 1s71s61s51s4S3 S2 1s11s0

01010000
Lowest Highest
PriorityStatus 76543210

After Rotation (IR4 servicecompleted)

s51S41s31s2 ISR Status Bit 1s7ls6 1s11s0

01000000
Lowest Highest
Priority Status 43210765

ProgrammingThe Interrupt Controller

Two types of commandsare used to control
the 82C206 interruptcontrollers,Initialization
Command Words (ICWS) and Operational
Command Words (OCWS).

InitializationCommand Words
The initializationprocessconsistsof writinga END OF INITIALIZATION
sequence of 4 bytes to each interrupt con- CONTROLLERREADY
troller. The initialization sequence is started
by writing the first Initialization Command Figure11. initializationSequence .

26
 I
. CHIPS
. INTC1. INTC1 will allow INTC2 to generate
its own interrupt vectors if Cascade Mode is
selected and the highest priority IR pending
is from an INTC2 input. INTC1 and INTC2
must be programmed for Cascade Mode for
both devices to operate.

lCW2—Address 021H (OAIH)

msb Isb

(Write Only Register)

I
at any point (all 4 bytes must be written for
the controller to be properly initialized) by V7-V3—Thesebits are the upper 5 bits of the
writing to address 020H (OAOH)with a O in interrupt vector and are programmable by
data bit 4. Note, this will cause OCW2 or the CPU. The lower three bits of the vector
OCW3 to be written. are generated by the Priority Resolverduring
INTA (see “Figure 12). INTC1 and INTC2
ICW1–Address 020H (OAOH) need not be programmed with the same
value in ICW2.

ICW3 Format for INTC1—Address 021H

msb Isb
(Write Only Register)

S1—Bit 4 indicates to the interrupt controller

that an Initialization Sequence is starting
and must be a 1 to write ICW1.
I
LTM—Bit 3 selects level or edge triggered
inputs to the IRR. If a 1 is written to LTM, a
‘high’ level on the IRR input will generate an
interrupt request. The IR must be active until
the first INTA cycle is started to generate the
proper interrupt vector (an IR7 vector will be
generated if the IRR input is reasserted msb Isb
early) and the IR must be removed prior to
EOI to prevent a second interrupt from
occuring.

SM—Bit 1 selects between Single Mode and

Cascade Mode. Single Mode is used when-
ever only one interrupt controller (lNTCl) is
used and is not recommended for this de-
. vice. Cascade Mode allows the two interrupt
controllers to be connected through IR2 of

27
 (Write Only Register)
.
EMI—Bit 4 will Enable Multiple Interrupts
from the same channel in Fixed Priority
Mode. This allows INTC2 to fully nest inter-
rupts, when Cascade Mode with Fixed Pri-
ority Mode are both selected, without being
blocked by INTC1. Correct handling of this
mode requires the CPU to issue a non-
. .
specific EOI command to INTC2 and check
its In-Service Registerfor zero, when exiting
an interrupt service routine. If zero, a non-
specific EOI command should be sent to
INTC1. If non-zero, no command is issued.

AEO1—Auto End Of Interrupt is enabled

when ICW4 is written with a zero in bit 1.
The interrupt controller will perform a non-
specific EOI on the trailing edge of the
second INTA cycle. Note, this function
should not be used in a device with fully
nested interrupts unlessthe device is a cas-
cade Master.

Operational Command Words

Operational Command Words (OCWS) allow
the 82C206 interrupt controllers to be con-
trolled or reconfigured at any time while
operating. Each interrupt has 3 OCWS which
can be programmed to affect the proper
operating configuration and a Status Regis-
ter to monitor controller operation.

Operational Command Word 1 (OCW1) is

located at address 021h (OAlh) and may be
written any time the controller is not in ini-
tialization Mode. Operational Command
Words 2 and 3 (OCW2,0CW3) are located at
address 020H (OAOH). Writing to address
020H (OAOH)with a O in bit 4 will place the
controller in operational mode and load
OCW2 (if data bit 3 = O) or OCW3 (if data bit
3 = 1). #

28

\
 . SMM—lf ESMM and SMM both are written
with a 1 the Special Mask Mode is enabled.
Writing a 1 to ESMM and a O to SMM dis-
ables Special Mask Mode. During Special
Mask Mode, writing a 1 to any bit position
inhibits interruptsand a Oenables interrupts
on the associated channel by causing the
Priority Resolver to ignore the condition of
the ISR.

SI—See S1 above.

2/3-See 2/3 above.

PM—Polled Mode is enabled by writing a 1

to bit 2 of OCW3, causing the 82C206 to
perform the equivalent of an INTA cycle
during the next I/0 read operation to the
controller. The byte read during this cycle
will have bit 7 set if an interrupt is pending.
If bit 7 of the byte is set, the level of the
highest pending request will be encoded on
bits 2-O.The IRR will remain frozen until the
read cycle is completed at which time the
PM bit is reset.

RR—When the RR bit (bit 1) is 1, reading the

Status Port at address020h (OAOh)will cause
the contents of IRR or ISR (determinecl by
RIS) to be placed on XD7-XDO.AssertingPM
forces RR reset.

RIS—This bit selects between the IRR and

the ISR during Status Read operations if RR
=1.

COUNTER/TIMER
FUNCTIONAL DESCRIPTION
The Counter/Timer (CTC) in the 82C206 is
generalpurpose,and can be usedto generate
accurate time delays under software control.
The CTC contains3 16-bitcounters(Counter
O-3) which can be programmed to count in
binary or binary coded decimal (BCD). Each
counter operates independentlyof the other
two and can be programmed for operation as
a timer or a counter.

All three of the countersshown in Figure 13

are controlled from a common set of control
cial Mask Mode state. logic. The Control Logic decodes control in-
—.

29
 Counter Description
Each counter in the CTC contains a Control
Register,a Status Register,a W-bit Counting
Element (CE), a pair of 8-bit Counter Input
Latches(CIL,CIH),and a pair of 8-bit Counter
Output Latches (COL,COH). Each counter
also has a clock input for loading and decre-
menting the CE, a mode defined GATE input
for controlling the counter (only GATE2 is
externally accessible), and an OUT signal
(OUTOis not externallyaccessible).The OUT
signal’sstate and function are controlled by
the Counter Mode and condition of the CE
(see Mode Definitions).

The Control Register stores the mode and

command information used to control the
counter.The Control Registermay be loaded
by writing a byte, containinga pointer to the
desired counter, to the Write Control Word
address (043h). The remaining bits in the
byte contain the mode,the type of command,
formation written to the CTC and provides and count format information.
the controls necessary to load, read, con-
figure and control each counter. Counter O The Status register allows the software to
and Counter 1 can be programmedfor all six monitor counter condition and read back the
modes, but Mode 1 and Mode 5 have limited contentsof the Control Register.
usefulness due to the lack of an external
hardware trigger signal. Counter 2 can be The Counting Element is a Ioadable 16-bit
operated in any of six modes listed below. synchronousdown counter.The CE is loaded
or decremented on the falling edge of
Mode O Interrupt on terminal count TMRCLK. The CE contains the maximum
Mode 1 Hardware retriggerabieone-shot count when a Ois loaded;which is equivalent
Mode 2 Rate generator to 65536 in binaryoperationor 10000in BCD.
Mode 3 Square wave generator The CE does not stop when it reaches 0, In
Mode 4 Software triggered strobe Modes 2 and 3 the CE will be reloadedand in
Mode 5 Hardware retriggerablestrobe all other modesit will wrap aroundto FFFF in
binary operation or 9999 in BCD.
All three countersin the CTC are drivenfrom
a common clock input pin (TMRCLK) which The CE is indirectlyloaded by writing one or
is independentfrom other clock inputsto the two bytes (optional) to the Counter Input
82C206. Counter O’s output (OutO) is con- Latches, which are in turn loaded into the
nected to IRO of INTC1 (see Interrupt Con- CE. This allows the CE to be loaded or re-
troller Functional Description) and may be loaded in one TMRCLK cycle.
used as an interrupt to the system for time
keeping and task switching. Counter 1 may The CE is also read indirectly by reading the
be programmedto generate pulsesor square contentsof the Counter Output Latches.COL
waves for use by external devices.The third and COH are transparent latches which can
counter(Counter2) isa full functionCounter/ be read while transparent or latched (see
Timer.This channelcan be usedas an interval Latch Counter Command).
timer, a counter, or as a gated rate/pulse
generator.

30
 Address Function
040h Counter ORead/Write
041h Counter 1 Read/Write
042h Counter 2 Read/Write
043h Control RegisterWrite Only

Figure 14. Counter/Timer AddressMap

mand (see Read-Back Command). Bits 3-1

become “don’t care” during Latch Counter
Commands.

BCD—Bit O selects binary coded decimal

counting format during Read/Write Counter
Commands. Note, during Read-Back Com-
mand this bit must be O.
(Write Only Register)
Read/Write Counter Command
F3-FO—Bits7-4 determine the command to When writing to a counter, two conventions
be performed. must be observed:

M2-MO—Bits 3-1 determine the counter’s l—Each counters Control Word must be
modeduring Read/WriteCounter Commands written before the initial count is written.
(see Read/Write Counter Command) or se-
lect the counter during a Read-Back Com- 2—Writing the initial count must follow the

31
format specified in the Control Word (least The format of the Read-Back Command is:
significant byte only, most significant byte
only, or least significant byte and then most msb Isb
significant byte). b7 b6 b5 b4 b3 b2 b1 bO
A new initial count can be written into the 11 LC LS C2 Cl CO O
counter at any time after programming with-
out rewritingthe Control Word providingthe LC—Writing a O in bit 5 causes the selected
programmedformat is observed. counter(s) to latch the state of the CE in
COL and COH.
During Read/Write Counter Commands M3-
MOare defined as follows: LS—Writing a O in bit 4 causes the selected
counter(s) to latch the current condition of
it’s Control Register,Null Count and Output
M2 Ml MO Function into the Status Register.The next read of the
o 00 Select Mode O Counter will result in the contents of the
Status Register being read (see Status
0 01 Select Mode 1
Read).
x 10 Select Mode 2
x 11 Select Mode 3 C2-CO—Writinga 1 in bit 3 causes Counter
3 to latch one or both of the registersspeci-
1 10 Select Mode 4 fied by LC and LS. The same is true for bits
1 11 Select Mode 5 2 and 1 except that they enable Counters 1
and O respectively.
Latch Counter Command Each counter’s latches remain latched until
When a Latch Counter Command is issued, either the latch is read or the counter is
the counter’s output latches (COL,COH) reprogrammed.
latch the current state of the CE. COL and
COH remain latched until read by the CPU, If LS = LC = O,status will be returned on the
or the counter is reprogrammed. The output next read from the counter. The next one or
latches then return to a “transparent”con- two reads (depending on whether the coun-
dition. In this condition the latches are en- ter is programmed to transfer one or two
abled and the contents of the CE may be bytes) from the counter result in the count
read directly. being returned.

Latch Counter Commands may be issuedto Status Byte

more than one counter before reading the
first counter to which the command was msb Isb .
issued. Also, multiple Latch Counter Com-
b7 b6 b5 b4 b3 b2 b1 bO
mands issued to the same counter without
reading the counter will cause all but the OUT NC F1 FO M2 Ml MO BCD
first command to be ignored.
OUT—Bit 7 contains the state of the OUT
Read-BackCommand signal of the counter
The Read-BackCommand allows the user to
checkthe count value, Mode, and state of the NC—Bit 6 contains the condition of the Null
OUT signaland Null Count Flag of the selec- Count Flag. This flag is used to indicate that
ted counter(s). the contents of the CE are valid. NC will be
set to a 1 during a write to the Control
Register or the counter. NC is cleared to a O

32
 whenever the counter is loaded from the are loaded. When both CIL and CIH are
counter input registers. written, the CE is ioaded after CiH is written
(see Write Operations). This TMRCL,K pulse
F1-FO—Bits5-4 contain the F1 and FOCom- does not decrement the count, SOIfor an
mand bits which were written to the Com- initial count of N, OUT2 does not go high
mand Register of the counter during initiali- until N+1 TMRCLK pulsesafter initialization.
zation. This information is useful in deter- Writing a new initial count to the counter
mining whether the high byte, the low byte reloads the CE on the next TMRCLK pulse
or both must be transferred during counter
read/write operations. ,
and counting continues from the new count.

If an initial count is written with GATE2 = O,

I
M2-Ml—These bits reflect the mode of the it will still be loaded on the next TMRCLK
counter and are interpreted in the same pulse but counting does not begin until
manner as in Write Command operations. GATE2 = 1. OUT2 therefore, goes high N
TMRCLK pulses after GATE2 = 1.
BCD—Bit O indicates the CE is operating in
BCD format. Mode l—Hardware retriggerable em-shot
Writing the Control Word causes CWT2 to
Counter Operation go high initially. Once initialized the counter
Due to the previously stated restrictions in is armed and a trigger causes OUT2 to go
Counter O and Counter 1, Counter 2 will be low on the next TMRCLK pulse. OUT2 then
used as the example in describing counter remains low until the counter reaches 0. An
operation, but the description of Mode O, 2, initial count of N results in a one-shot pulse
3 and 4 is relevant to ail counters. N TMRCLK cycles long.

The foiiowing terms are defined for describ- Any subsequent triggers while OUT2 is low
ing CTC operation. cause the CE to be reloaded, extending the
length of the pulse, Writing a new count to
TMRCLK pulse—A risingedge followed by a CIL and CIH will not affect the current one-
falling edge of the 82C206 TMRCLK input. shot unless the counter is retriggered.
trigger—The rising edge of the GATE2 input.
Mode 2-Rate generator
counter load—The transfer of the 16-bit Mode 2 functions as a divide-by-N counter,
vaiue in CIL and CIH to the CE.
with OUT2 as the carry. Writing the Control
initialized—A Control Word written and the Word during initialization sets OUT2 high.
Counter Input Latches loaded.
When the initial count is decremented to 1,
Counter 2 operates in one of the following OUT2 goes low on the next TMRCLK pulse.
modes. The following TMRCLK pulse returns OUT2
high, reloads the CE and the process is
I
Mode O—Interrupton terminal count repeated. In Mode 2 the counter continues
counting (if GATE2 = 1) and will generate an
Writing the Control Word causes OUT2 to OUT2 pulse every N TMRCLK cycles. Note
go low and remain low until the CE reaches that a count of 1 is illegal in Mode 2.
O, at which time it goes back high and re-
mains high until a new count or Control GATE2 = O disables counting and forces
Word is written. Counting is enabled when OUT2 high immediately. A trigger reloads
GATE2 = 1. Disabling the count has no effect the the CE on the next TMRCLK pulse. Thus
on OUT2. GATE2 can be used to synchronize the
counter to external events.
The CE is loaded with the first TMRCLK
pulseafter the Control Word and initial count Writing a new count while counting does not

I
33

\ ..
affect current operation unless a trigger is begins decrementing one TMRCLK pulse
received. Otherwise, the new count will be later. OUT2 will go low for one TMRCLK
loaded at the end of the current counting cycle, (N+l) cycles after the initial count is
cycle. written.

Mode 3-Square wave generator If a new initial count is written during a

Mode 3 is similar to Mode 2 in every respect counting sequence, it is loaded into the CE
except for the duty cycle of OUT2. OUT2 is on the next TMRCLK pulse and the se-
set high initially and remains high for the quence continues from the new count. This
first half of the count. When the first half of allows the sequence to be “retriggerable”by
the initial count expires, OUT2 goes low for software.
the remainder of the count.
Mode 5—Hardware triggered strobe
If the counter is loaded with an even count, Writing the Control Word causes OUT2 to
the duty cycle of OUT2 will be 50% (high = go high intially. Counting is started by trig-
low = N/2). For odd count values. OUT2 is ger. The expiration of the initial count causes
high one ‘TMRCLK cycle longer than it is OUT2 to go low for one TMRCLK cycle.
low. Therefore, high = (N+l)/2 and low = GATE2 = O disables counting.
(N-1)/2.
The CE is loaded on the TMRCLK pulse
Mode 4—Software triggered strobe after a trigger. Since loading the CE inhibits
Writing the Control Word causes OUT2 to decrementing, OUT2 will go low for one
go high initially. Expiration of the initial TMRCLK cycle, (N+l) TMRCLK cycles after
count causes OUT2 to go low for one the trigger.
TMRCLK cycle. GATE2 = Odisablescounting
but has no effect on OUT2. Also, a trigger If a new count is loaded during counting,
will not reload the CE. the current counting sequence will not be
affected unless a trigger occurs. A trigger
The counting sequence is started by writing causes the counter to be reloaded from CIL
the initial count. The CE is loaded on the and CIH, making the counter “retriggerable”.
TMRCLK pulse after initialization. The CE

Low Rising High

o DisablesCounting — Enables Counting

Figure 15. Gate Pin Function

34
 GATE2 bytes which normally contain the time, cal-
In Modes O,2, 3 and 4 GATE2 is level sensi- endar, and alarm data, four control and stat-
tive and is sampled on the rising edge of us bytes and 114 general purpose RAM
TMRCLK. In Modes 1, 2, 3 and 5 the GATE2 bytes. All 128 bytes are readable by the
CPU. The CPU may also write to all locations
input is rising-edge sensitive. This rising
edge sets an internal flip-flop whose output except Registers C, D, Bit 7 of Register A
is sampled on the next rising edge of and Bit 7 of the Seconds Byte which is
TMRCLK. The flop-flop resets immediately always O.
after being sampled. Note that in Modes 2
and 3 the GATE2 input is both edge and
level sensitive. Index Function
00 SECONDS
REAL TIME CLOCK
FUNCTIONAL DESCRIPTION 01 SECONDS ALARM
This section of the 82C206 combinesa com- 02 MINUTES
plete time-of-day clock with alarm, one hun- 03 MINUTES ALARM
dred year calendar,a programmableperiodic
interrupt, and 114 bytes of low power static 04 HOURS
RAM. Provisions are made to enable the 05 HOURS ALARM
device to operate in a low power (battery
06 DAY OF WEEK
powered) mode and protect the contents of
both the RAM and clock during system 07 DATE OF MONTH
power-up and power-down. 08 MONTH
Register Access
Reading and writing to the 128 locations in
the Real Time Clock is accomplished by first
placing the Index Address of the location
you wish to access on the data input pins
XDO-XD6 and then strobing the AS input
pin. The address will then be latched into
the Index Address Register on the falling
edge of AS. The Index Address Register is
then used as a pointer to the specific byte in
the Real Time Clock, which
—— may be read or
written to by asserting XIOR or XIOW with
with an address on the XA9-XAO inputs of
071H.

Since AS will most likely be generated by an

1/0 operation which will result in the asser-
tion of XIOW, it is recommended that an
address of 070H be applied to the XA9-XAO
inputs during this time. This will prevent the
modificationof other registersin the 82C206.

Address Map
Figure 16 illustratesthe internal register/RAM
organization of the Real Time Clock portion
of the 82C206. The 128addressablelocations
in the Real Time Clock are divided into 10

35
 .

Before initializationof the internal registers

can be performed, the SET bit in Register B
should be set to a “l” to prevent Real Time
Clock updatesfrom occuring.The CPU then
initializesthe first 10 locationsin BCD format.
The SET bit should then be cleared to allow
updates. Once initializedand enabled, the
Real Time Clock will perform Clock/Calen-
dar updates at a 1 Hz rate.

Index
Register Function EICDRange
Address
o Seconds 00-59
1 Seconds Alarm 00-59
2 Minutes 00-59
3 Minutes Alarm 00-59
Hours 01-12 (AM)
(12 hour mode) 81-92 (PM)
4
Hours 00-23
(24 hour mode)
Hours Alarm 01-12 (AM)
(12 hour mode) 81-92 (PM)
5
Hours Alarm 00-23
(24 hour mode)
6 Day of Week 01-07
7 Day of Month 01-31
8 Month 01-12
9 Year 00-99

Figure 17. Time, Calendar,

Alarm Data Format

Figure 17 shows the format for the ten clock,

calendarand alarm locations.The 24/12 bit in
RegisterB determineswhetherthe hour loca-
tions will be updated using a 1-12 or O-23
format. After initializationthe 24/12 bit cannot
be changed without reinitializingthe hour lo-
cations. In 12 hour format the high order bit
of the hours byte in both the time and alarm
bytes will indicate PM when it is a “l”.

During updates, which occur once per sec-

36
UIP-Update in progress flag is a status bit
used to indicate when an update cycle is
about to take place. A “l” indicates that an
update cycle is taking place or is imminent.
UIP will go active (High) 244us prior to the
start of an update cycle and will remain
activefor an additional 2ms while the update
is taking place. The UIP bit is read only and
is not affected by Reset. Writing a “1” to the
SET bit in Register B will clear the UIP Divider‘Options
status bit.
RS3-RSO—Thesefour bits control the Peri-
DV2-DVO—Thesethree bits are used to con- odic Interrupt rate. The Periodic interrupt is
trol the Divider/Prescaler on the Real Time derived from the Divider/Prescaler in the
Clock. While the 82C206 can operate at fre- Real Time Clock and is separate from the
quencies higher than 32.768 Khz, this is not Alarm Interrupt. Both the alarm and periodic
recommendedfor batterypowered operation interrupts do however, use the same inter-
due to the increased power consumption at rupt channel in the Interrupt Controller. Use
these higher frequencies. of the Periodic Interrupt allows the genera-
tion of interrupts at rates higher than once
per second. Below are the interrupt rates for
which the Real Time Clock can be pro-
grammed.

Rate Selection Time Base

—
4.194304 MHz

37
 .
REGISTER C (OCH)

(Read/Write Register)

SET—Writing a “O”to this bit enables the IRQF—The Interrupt Request Flag bit is set
Update Cycle and allows the Real Time to a “l” when any of the conditions which
Clock to function normal!y. When set to a can cause an interrupt is true and the inter-
“l” the Update Cycle is inhibited and any rupt enable for that condition is true. The
cycle in progress is aborted. The SET bit is condition which causes this bit to be set,
not affected by the RESET input pin. also generates an interrupt. The logic ex-
pression for this flag is:
PIE—The Periodic interrupt Enable Bit con-
trols the generation of interrupts based on
the value programmedinto the RS3-RSObits
of RegisterA. This allows the user to disable
this function without affecting the program-
med rate. Writing a “l” to this bit enables the This bit and all other active bits in this regis-
generation of periodic interrupts. This bit is ter are cleared by reading the register or by
cleared to a “O”by Reset. activating the PSRSTB/ input pin. Writing to
this register has no affect on the contents.
AlE—The generation of alarm interrupts is
enabled by settingthis bit to a”1”. Once this PF—The PeriodicInterruptFlag is setto a “l”
bit is enabled the Real Time Clock will gen- when a transition,which is selected by RS3-
erate an alarm whenever a match occurs RSO,occurs in the divider chain. This bit will
between the programmed alarm and clock become active, independentof the condition
information. If the don’t care condition is of the PIE control bit. The PF bit will then
programmed into one or more of the Alarm generatean interruptand set IRQF if PIE isa
Registers,this will enable the generation of 1.
periodic interruptsat rates of one second or
greater. This bit is cleared by Reset. AF—A “1” appears in the AF bit whenevera
match hasoccuredbetweenthe time registers
24/12—The24/12 control bit is usedto estab- and alarm registersduring an update cycle.
lish the format of both the Hours and Hours This flag is also independent of it’s enable
Alarm bytes. If this bit is a “l”, the Real Time (AIE) and will generate an interrupt if AIE is
Clock will interpret and update the the in- true.
formation in these two bytes using the 24
hour mode. This bit can be read or—– written REGISTER D (ODH)
by the CPU and is not affected by Reset.
msb Isb
DSE—The Real Time Clock can be instruc-
ted to handle daylight savingstime changes
by setting this bit to a “l”. This enables two
exceptions to the normal time keeping se- (Read only register)
quence to occur. On the last Sunday in April
AM. Set- ,
VRT—The Valid RAM and Time Bit indicates
ting this bit to a “O”disables the execution the condition of the contents of the Real
of these two exceptions. PSRSTB has no Time Clock. This bit is cleared to a “O”
affect on this bit. whenever the PS input pin is LOW. This pin .

.“

38
 is normally derived from the power supply cycle is complete. Once the cycle is com-
which supplies Vcc to the device and will plete the UIP bit will be cleared and the
allow the userto determinewhetherthe regis- Update Flag (UF) in Register C will be set.
ters have been initialized since power was Figure 18 illustrates the update cycle. CPU
applied to the device. PSRSTB has no affect access is always allowed to Registers A
on this bit and it can only be set by reading through D during update cycles.
Register D.All unused register bits will be
“O”when read and are not writable. Two methods for reading and writing to the
Real Time Clock are recommended. Both of
Update Cycle these methods will allow the user to avoid
During normal operation the Real Time contention between the CPU and the Real
Clock will perform an update cycle once Time Clock for access to the time and date
every second.The performanceof an update information.
cycle is contingent upon the divider bits
DV2-DVO not being cleared, and the SET bit The first method is to read Register A,
in Register B cleared. The function of the determine the state of the UIP bit and if it is
update cycle is to increment the clock/ “O”,perform the read or write operation. For
calendar registersand compare them to the this method to work successfullythe entire
Alarm Registers. If a match occurs between read or write operation (including any inter-
the two sets of registers, an alarm is issued rupt service routines which might occur)
and an interrupt will be issued if the alarm must not require longer than 244@ to com-
and interrupt control bits are enabled. plete from the beginning of the read of
Register A to the completion of the last read
or write operation to the Clock Calendar
Registers.

The second method of accessing the lower

10 registers is to read Register C once and
disregard the contents. Then subsequently
continue reading this register until the UF
bit is a “l”. This bit will become true im-
mediately after an update has been com-
pleted. The user then has until the start of
NOTE: the next update cycle to complete a read or
1. REGISTERSO-9ARE UNAVAILABLETO BE write operation.
READ OR WRITTEN DURING THIS TIME.
2. UF BIT CLEAREDBY CPU READ OF Power-Up/Down
REGISTER C. Most applications will require the Real Time
Clock to remain active whenever the system
Figure 18. Update Cycle
power is turned off. To accomplish this the
user must provide an alternate source of
During the time that an update is taking power to the 82C206. This alternate source
place, the lower 10 registers are unavailable of power is normally provided by connecting
to the CPU. This is done to prevent the a battery to the Vcc supply pin of the device.
possible corruption of data in the registers A means should be provided to switch from
or the reading of incorrect data. To avoid the system power supply to the battery. A
contention problems between the Real Time circuit such as the one shown in Figure 19
Clock and the CPU, a flag is provided in may be used to eliminate power drain on the
Register A to alert the user of an impending battery when the entire 82C206 is active.
update cycle. This Update In Process Bit The circuit shown here will allow for reliable
(UIP) is asserted 244@ before the actual transitionsbetweensystemand battery pow-
start of the cycle and is maintained until the er without undue battery power drain.

39
The user should also ensure that-the Vin bits affected by PSRSTB) Assertion of
maximum specification is never exceeded PSRSTB disables the generation of inter-
when powering the systemup or down. Fail- rupts and sets a flag indicating that the
ure to observe this specification may result contents of the device may not be valid. A
in damage to the device. recommended circuit for controlling the
PSRSTB input is also shown in Figure 19.

prevent noise on the —.

inactive pins from

PSRSTB

S2C206

the necessarycontrol register bits. (See Pin Figure19. PowerConversionand Reset

Description for a list of the control register circuitry

40
.

..

41
 .

>..

42
t59 ADSTBX Invalid Delav from SCLK 120 120 nsec
t60 XDO-XD7Active Delay from SCLK 110 60 nsec
t61 XDO-XD7Valid Setup
to ADSTBX LOW 80 65 nsec
t62 XDO-XD7Hold Time
from ADSTBX Low 25 25 nsec

43
44
 - PERIPHERAL
WRITECYCLE

COMMANDRECOVERY

XDO-XD7

45
 IOCHRDYOUTPUT

REALTIME CLOCKACCESSCYCLE

REALTIME CLOCKPOWER-UPSEQUENCE
.
47
48
 ,.

49
 .

UNIT(mm)
I

5.0MAX I

OrderingInformation

50
 RegionalSales Offices
1

UnitedStates

ChipsendTednologios,
Inc. PRELIMINARY
 .

Sales Representatives

Ch@smdTedmd@ss,
Inc. ~
 Distributors

NorthAmerica

United
States

,
 .
■ Distributors

Distributors
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International

PRELIMINARY
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 Chips and Technologies, Incorporated
3050 Zanker Road, San Jose, CA 95134408-434-0600 Telex 272929 CHIP UR

IBM, AT XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter, Color
Graphics Adapter,IBM Color Display,IBM Monochrome Display are trademarksof International
BusinessMachines.
Intel, iAPX 388 are trademarksof Intel Corporation.
Motorola is a trademark of Motorola.
Hercules Graphics is a trademark of Hercules Computer Technology.
Lotus is a trademarkof Lotus Corporation.
Microsoft is a trademarkof Microsoft.
CHIPSet, CHIPSpak, CHIPSport, CHIPSLINK, NEAT are trademarksof Chips and Technologies,
Inc.
COPYRIGHT 1988 CHIPS AND TECHNOLOGIES, INC.
THESE DATA SHEETS ARE PROVIDED FOR THE GENERAL INFORMATION OF THE
CUSTOMER. CHIPS AND TECHNOLOGIES, INC. RESERVESTHE RIGHT TO MODIFY THESE
PARAMETERSAS NECESSARY AND CUSTOMER SHOULD ENSURE THAT IT HAS THE MOST
RECENT REVISION OF THE DATASHEET THE CUSTOMER SHOULD BE ON NOTICE THAT
THE FIELD OF PERSONAL COMPUTERS IS THE SUBJECT OF MANY PATENTS HELD BY
DIFFERENT PARTIES. CUSTOMERS SHOULD ENSURE THAT THEY TAKE APPROPRIATE
ACTION SO THAT THEIR USE OF THE PRODUCTS DOES NOT INFRINGE ANY PATENTS.IT IS
THE POLICY OF CHIPS AND TECHNOLOGIES, INC. TO RESPECT THE VALID PATENT
RIGHTS OF THIRD PARTIES AND NOT TO INFRINGE OR ASSIST OTHERS TO INFRINGE
SUCH RIGHTS.