Project #8:
DSP-Slice-Implementation
group_19_111_7
Name ID
Mohamed Ahmed Hassan Aboelnaga V23010261
Mohamed Khaled Alahmady V23010489
Mohamed Niazy Hassanien V23010512
Yara Gooda Ahmed V23009934
Presented to: Dr. Ahmed Saeed
DSP Overview
- As algorithm complexity has increased over the years, traditional processors face
challenges in efficiently running these sophisticated algorithms with high performance.
Addressing this gap necessitates a solution, and the DSP slice solution emerges to meet
these demands.
- In this project we select one of these blocks which is DSP48A1 slice which exist in
Spartan-6 FPGA
Figure 1: Growing DSP Performance Gap
DSP48A1 Capabilities
- DSP48A1 slices typically include features such as multipliers, adders, accumulators, and
other arithmetic functions. They are optimized for parallel processing of data, making
them efficient for DSP applications where high-throughput and low-latency processing
are essential.
- The key point of most of DSP blocks is MAC (Multiply and accumulate), the equation
described in the following:
𝑁−1
𝑌[𝑛] = ∑ 𝐾𝑖 𝑋[𝑛 − 𝑖]
𝑖=0
Figure 2: FIR filter Diagram
High Level Architecture
- The DSP48A1 slices are organized as vertical DSP columns. Within the DSP column, a
single DSP slice is combined with extra logic and routing. The vertical column
configuration is ideal to connect a DSP slice to its two adjacent neighboring slices,
hence cascading those blocks and facilitating the implementation of systolic DSP
algorithms.
- Each DSP48A1 slice has a selectable 18-bit pre-adder/subtracter. The pre-
adder/subtracter is followed by a two-input multiplier, multiplexers, and a two-input
adder/subtracter. The multiplier accepts two 18-bit, two’s complement operands
producing a 36-bit, two’s complement result. The 36-bit output of the multiplier can be
routed directly to the FPGA logic. The result is sign extended to 48 bits and can
optionally be fed to the adder/subtracter.
Figure 3:Simplified DSP48A1 Slice with Pre-Adder
DSP48A1 Ports
Figure 4: DSP48A1 Slice Primitive
DSP48A1 Slice in Details:
- The math portion of the DSP48A1 slice consists of an 18-bit pre-adder followed by
an 18-bit x 18-bit, two’s complement multiplier followed by two 48-bit datapath
multiplexers (with outputs X and Z) followed by a two-input, 48-bit post-
adder/subtracter.
Figure 5: DSP48A1 Slice
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Description of main ports
Signal Direction Size Function
A Input 18 18-bit data input to multiplier, and optionally to
post-adder/subtracter depending on the value of
OPMODE[1:0].
B Input 18 18-bit data input to pre-adder/subtracter, to
multiplier depending on OPMODE[4], or to post-
adder/subtracter depending on OPMODE[1:0]
C Input 48 48-bit data input to post-adder/subtracter.
D Input 18 18-bit data input to pre-adder/subtracter. D[11:0]
are concatenated with A and B and optionally sent
to post-adder/subtracter depending on the value
of OPMODE[1:0].
CARRYIN Input 1 carry input to the post-adder/subtracter
OPMODE Input 8 Control input to select the arithmetic operations
of the DSP48A1 slice.
M Output 36 36-bit buffered multiplier data output, routable to
the FPGA logic. It is either the output of the M
register (MREG = 1) or the direct output of the
multiplier (MREG = 0).
P Output 48 Primary data output from the post-
adder/subtracter. It is either the output of the P
register (PREG = 1) or the direct output of the
postadder/subtracter (PREG = 0).
CARRYOUT Output 1 Cascade carry out signal from post-
adder/subtracter. It can be registered in
(CARRYOUTREG = 1) or unregistered
(CARRYOUTREG = 0). This output is to be
connected only to CARRYIN of adjacent DSP48A1
if multiple DSP blocks are used.
CARRYOUTF Output 1 Carry out signal from post-adder/subtracter for
use in the FPGA logic. It is a copy of the
CARRYOUT signal that can be routed to the user
logic.
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Simulation
- Once the design of each individual block is finished, we proceed to integrate the
entire system and conduct testing. This involves utilizing a self-checking and
randomized testbench for inputs (A, B, C, D, CARRY_IN, OPMOD). The process
includes comparing the expected output of the block with the actual output to
ensure functionality.
Figure 6: Simulation Waveform
Output Sample
- As shown all test cases are passed.
Figure 7: Simulation Output
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Synthesis using Quartus Tool:
- RTL Viewer
Figure 8: Synthesis Output
- Resources Summary
Figure 9: Flow Summary
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Figure 10: Power Consumption
