VIETNAM NATIONAL UNIVERSITY HANOI (VNU)

VNU INFORMATION TECHNOLOGY INSTITUTE (VNU-ITI)

Introduction to Hardware
Description Languages

Xuan-Tu Tran, PhD, Assoc. Prof.

Vietnam National University, Hanoi
Email: [email protected]

Contents

❑ Design methodology

❑ Brief History of VHDL

– VHDL
– Verilog/SystemVerilog
– Language Zoos

❑ VHDL fundamental
– Design entity
– Libraries
– Std_Logic demystify
– Modeling Wires & Buses
– Testbenhes

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1
 RS232 port to
computer
Supply
voltages

CRYPTO_RUNNING_O
SPI_SS_CRYPTO_N

FLL_FREQ_OUT_0
VDD_NOCPERF1
Test FSM & configs

VDD_CRYPTO

VDD_CFG_1
Crypto. kernel

VDDE2
GNDE2

GND3

CLK_I
GND4

VDD4

VDD3
SPI
VDD1 GND7

GND1 VDD7
VDD_CFG4 SPI_MOSI_I

SPI_SCLK_I

VDD_FLL

SPI_SS_ASN_N_I
FLL GNDE1

VDD2

VDD0
RESETN_I

SPI_MISO_O
GND
GND2 GND8

VDD6

SNACk
VDDE1

GND0

VDD_NOCPERF2

VDD_NOCPERF3 VDD_CFG2

VDD9 GND5

GND9 VDD5
GNDBGCON

VDD_ASN
GNDE1

VDD8

VDD_NOCPERF3
VDD

GND

VDD
VDD_CFG3

GND6

Jumper to
measure

FLL output
the current

Ref. clock
Reset, SPI
slave selects
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Design Methodology

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2
 Models

❑Abstract representations of aspects of a system being designed

– Allow us to analyze the system before building it

❑Example: Ohm’s Law

–V=I×R

– Represents electrical aspects of a resistor

– Expressed as a mathematical equation

– Ignores thermal, mechanical, materials aspects

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VHIC Hardware Description Language (VHDL)

❑Hardware Description Language

– A computer language for modeling behavior and structure of digital
systems

❑Electronic Design Automation (EDA) using Verilog/VHDL

– Design entry: alternative to schematics

– Verification: simulation, proof of properties

– Synthesis: automatic generation of circuits

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3
 Entity/Module Ports

❑ Describe input and outputs of a circuit

above_30_0
>30°C temp_bad_0
or_0a
inv_0 or_0b
above_25_0
>25°C
wake_up_0
below_25_0
low_level_0
low level select_mux
0 buzzer
1
buzzer
above_30_1
>30°C temp_bad_1
or_1a
inv_1 or_1b wake_up_1 +V
above_25_1
>25°C
select_vat_1
below_25_1
low_level_1
low level

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Structural Design Definition

library ieee; use ieee.std_logic_1164.all;

entity vat_buzzer is
port ( buzzer : out std_logic;
above_25_0, above_30_0, low_level_0 : in std_logic;
above_25_1, above_30_1, low_level_1 : in std_logic;
select_vat_1 : in std_logic );
end entity vat_buzzer;

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 Structure design implementation

library dld; use dld.gates.all;

architecture struct of vat_buzzer is
signal below_25_0, temp_bad_0, wake_up_0 : std_logic;
signal below_25_1, temp_bad_1, wake_up_1 : std_logic;
begin
-- components for vat 0
inv_0 : inv port map (above_25_0, below_25_0);
or_0a : or2 port map (above_30_0, below_25_0, temp_bad_0);
or_0b : or2 port map (temp_bad_0, low_level_0, wake_up_0);
-- components for vat 1
inv_1 : inv port map (above_25_1, below_25_1);
or_1a : or2 port map (above_30_1, below_25_1, temp_bad_1);
or_1b : or2 port map (temp_bad_1, low_level_1, wake_up_1);

select_mux : mux2 port map (wake_up_0, wake_up_1,

select_vat_1, buzzer);

end architecture struct;

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Behavioral Design Definition

library ieee; use ieee.std_logic_1164.all;

entity vat_buzzer is
port ( buzzer : out std_logic;
above_25_0, above_30_0, low_level_0 : in std_logic;
above_25_1, above_30_1, low_level_1 : in std_logic;
select_vat_1 : in std_logic );
end entity vat_buzzer;
architecture behavior of vat_buzzer is
begin
buzzer <= low_level_1 or (above_30_1 or not above_25_1)
when select_vat_1 = '1' else
low_level_0 or (above_30_0 or not above_25_0);
end architecture behavior;

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 Design Methodology

❑Simple systems can be design by one person using ad hoc

methods
❑Real-world systems are design by teams
– Require a systematic design methodology
❑Specifies
– Tasks to be undertaken
– Information needed and produced
– Relationships between tasks
▪ dependencies, sequences
– EDA tools used

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A Simple Design Methodology

Requirements
and
Constraints

Physical
Design Synthesize Manufacture
Implementation

Functional Post-synthesis Physical

Test
Verification Verification Verification

Y Y Y
OK? OK? OK?

N N N

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 Hierarchical Design

❑Circuits are too complex for us to design all the detail at once

❑Design subsystems for simple functions

❑Compose subsystems to form the system

– Treating subcircuits as “black box” components

– Verify independently, then verify the composition

❑Top-down/bottom-up design

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Hierarchical Design

Architecture
Design

Unit
Design
Design

Unit
Verification
Functional
Verification
N
OK?
Y
Y
OK?
Integration
N
Verification

N
OK?
Y
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 Synthesis

❑ We usually design using register-transfer-level (RTL) Verilog

– Higher level of abstraction than gates
❑ Synthesis tool translates to a circuit of gates that performs the same function
❑ Specify to the tool
– the target implementation fabric
– constraints on timing, area, etc.
❑ Post-synthesis verification
– synthesized circuit meets constraints

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Physical Implementation

❑ Implementation fabrics
– Application-specific ICs (ASICs)
– Field-programmable gate arrays (FPGAs)

❑ Floor-planning: arranging the subsystems

❑ Placement: arranging the gates within subsystems
❑ Routing: joining the gates with wires
❑ Physical verification
– physical circuit still meets constraints
– use better estimates of delays

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 Codesign Methodology

Requirements
and
Constraints

Partitioning

Hardware Software
Requirements Requirements
and Constraints and Constraints

Hardware Software
Design and Design and
Verification Verification

N N
OK? OK?

Manufacture
and Test

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Xuan-Tu Tran 17

Summary

❑ Digital systems use discrete (binary) representations of information

❑ Basic components: gates and flipflops

❑ Combinational and sequential circuits

❑ Real-world constraints
– logic levels, loads, timing, area, etc

❑ Verilog models: structural, behavioral

❑ Design methodology

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 Brief History of VHDL

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VHDL

❑ VHDL is a language for describing digital hardware used by industry worldwide

– VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

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 Genesis of VHDL

State of art circa 1980

– Multiple design entry methods and
hardware description languages in use
– No or limited portability of designs
between CAD tools from different vendors
– Objective: shortening the time from a design concept to implementation from
18 months to 6 months

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A Brief History of VHDL

• June 1981: Woods Hole Workshop

• July 1983: contract awarded to develop VHDL
– Intermetrics
– IBM
– Texas Instruments
• August 1985: VHDL Version 7.2 released
• December 1987:
VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard

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 Four versions of VHDL

❑ VHDL-87

❑ VHDL-93

❑ VHDL-01

❑ VHDL-08

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Verilog/SystemVerilog

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 Verilog/SystemVerilog

• Essentially identical in function to VHDL

▪ No generate statement
• Simpler and syntactically different
▪ C-like
• Gateway Design Automation Co., 1983
• Early de facto standard for ASIC programming
• Open Verilog International standard
• Programming language interface to allow connection to non-Verilog code
• SystemVerilog adds many features for design & verification
▪ Object Oriented Programming
▪ Interfaces
▪ Better design construct
▪ Formal Verification

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VHDL vs. Verilog

Government Developed Commercially Developed

Ada based C based

Strongly Type Cast Mildly Type Cast

Difficult to learn Easier to Learn

More Powerful Less Powerful

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 Language Zoos

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Programming for hadware/software

Constrained Program Clocking Enhanced Scheduling for Cycle Sequence

Random Data Block Domain Testbench and Assertions Delays Events
Generation
Sequential Semaphores Persistent Functional
Queues
Classes, methods Regular events Coverage
Mailboxes
& inheritance Expressions Process Virtual
Interface Temporal Operator Control Interfaces
Specification Properties Packages Overloading
Associative
Dynamic safe pointers & Sparse arrays
Architecture Simple assertions
memory
configuration allocation
User-defined types Void type Further
records/ programming
Dynamic enums structs Unions
multi-D arrays (do while,
hardware
break, continue,
generation Automatic variables Signed numbers Strings ++, --, +=. etc)

Event handling Basic datatypes (bit, int, reg, wire…)

4 state logic Basic programming (for, if, while,..)

Packed structs
and unions
Hardware concurrency Gate level modelling
design entity modularization and timing Coverage & C interface
Assertion
API
Switch level modeling and timing ASIC timing

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 Semantic programming: C

Constrained Program Clocking Enhanced Scheduling for Cycle Sequence

Random Data Block Domain Testbench and Assertions Delays Events
Generation
Sequential Semaphores Persistent Functional
Queues
Classes, methods Regular events Coverage
Mailboxes
& inheritance Expressions Process Virtual
Interface Temporal Operator Control Interfaces
Specification Properties Packages Overloading
Associative
Dynamic safe pointers & Sparse arrays
Architecture Simple assertions
memory
configuration allocation
User-defined types Void type Further
records/ programming
Dynamic enums structs Unions
multi-D arrays (do while,
hardware
break, continue,
generation Automatic variables Signed numbers Strings ++, --, +=. etc)

Event handling Basic datatypes (bit, int, reg, wire…)

4 state logic Basic programming (for, if, while,..)

C has extra programming
Packed structs
and unions
Hardware concurrency Gate level modelling
design entity modularization and timing features
Coverage & but lacks all
C interface
Assertion
API hardware concept
Switch level modeling and timing ASIC timing

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Verilog

Constrained Program Clocking Enhanced Scheduling for Cycle Sequence

Random Data Block Domain Testbench and Assertions Delays Events
Generation
Sequential Semaphores Persistent Functional
Queues
Classes, methods Regular events Coverage
Mailboxes
& inheritance Expressions Process Virtual
Interface Temporal Operator Control Interfaces
Specification Properties Packages Overloading
Associative
Dynamic safe pointers & Sparse arrays
Architecture Simple assertions
memory
configuration allocation
User-defined types Void type Further
records/ programming
Dynamic enums structs Unions
multi-D arrays (do while,
hardware
break, continue,
generation Automatic variables Signed numbers Strings ++, --, +=. etc)

Event handling Basic datatypes (bit, int, reg, wire…)

4 state logic Basic programming (for, if, while,..)

Packed structs
and unions
Hardware concurrency Gate level modelling
design entity modularization and timing Coverage & C interface
Assertion
API
Switch level modeling and timing ASIC timing

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 VHDL

Constrained Program Clocking Enhanced Scheduling for Cycle Sequence

Random Data Block Domain Testbench and Assertions Delays Events
Generation
Sequential Semaphores Persistent Functional
Queues
Classes, methods Regular events Coverage
Mailboxes
& inheritance Expressions Process Virtual
Interface Temporal Operator Control Interfaces
Specification Properties Packages Overloading
Associative
Dynamic safe pointers & Sparse arrays
Architecture Simple assertions
memory
configuration allocation
User-defined types Void type Further
records/ programming
Dynamic enums structs Unions
multi-D arrays (do while,
hardware
break, continue,
generation Automatic variables Signed numbers Strings ++, --, +=. etc)

Event handling Basic datatypes (bit, int, reg, wire…)

4 state logic Basic programming (for, if, while,..)

Packed structs
and unions
Hardware concurrency Gate level modelling
Coverage &
design entity modularization and timing
VHDL has higher level
Assertion
C interface
API
Switch level modeling and timing ASIC timing data types, and
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management functionality 31

SystemVerilog: Enhancements

Constrained Program Clocking Enhanced Scheduling for Cycle Sequence

Random Data Block Domain Testbench and Assertions Delays Events
Generation
Sequential Semaphores Persistent Functional
Queues
Classes, methods Regular events Coverage
Mailboxes
& inheritance Expressions Process Virtual
Interface Temporal Operator Control Interfaces
Specification Properties Packages Overloading
Associative
Dynamic safe pointers & Sparse arrays
Architecture Simple assertions
memory
configuration allocation
User-defined types Void type Further
records/ programming
Dynamic enums structs Unions
multi-D arrays (do while,
hardware
break, continue,
generation Automatic variables Signed numbers Strings ++, --, +=. etc)

Event handling Basic datatypes (bit, int, reg, wire…)

SystemVerilog
4 state logic 3.1
Basic has (for, if, while,..)
programming
Packed structs
advanced verification and
Hardware concurrency Gate level modelling
and unions
Coverage &
design entity modularization C interface
modeling features and timing Assertion
API
Switch level modeling and timing ASIC timing

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 Examples

❑ VHDL Example:
process (clk, rstn)
begin
if (rstn = '0') then
q <= '0';
elseif (clk'event and clk = '1') then
q <= a + b;
end if;
end process;

❑ Verilog Example:
always@(posedge clk or negedge rstn)
begin
if (! rstn)
q <= 1'b0;
else
q <= a + b;
end

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Features of VHDL and Verilog

❑ Technology/vendor independent

❑ Portable

❑ Reusable

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 Other hardware description languages

❑ AHDL: Altera Hardware Description Language

❑ AHPL: A Hardware Programming Language
❑ CDL: Computer Design Language
❑ CONLAN: CONsensus LANguage
❑ IDL: Interactive Design Language
❑ ISPS: Instruction Set Processor Specification
❑ TEGAS: TEst Generation And Simulation
❑ TI-HDL: Texas Instruments Hardware Description Language
❑ Chisel3: Constructing Hardware in Scala Embedded Language

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VHDL for Synthesis

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 VHDL for Specification

VHDL for Simulation

VHDL for Synthesis

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Levels of design description

Algorithmic level
Level of description
Register Transfer Level
most suitable for synthesis
Logic (gate) level

Circuit (transistor) level

Physical (layout) level

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 Register Transfer Logic (RTL) Design Description

Combinational
Logic
Combinational
Logic
…

Registers

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VHDL Fundamentals

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 Naming and Labeling (1)

❑ VHDL is not case sensitive

Example:
Names or labels
databus
Databus
DataBus
DATABUS
are all equivalent

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Naming and Labeling (2)

General rules of thumb (according to VHDL-87)

1. All names should start with an alphabet character (a-z or A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)
3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)
4. Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)
5. All names and labels in a given entity and architecture must be unique

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 Free Format

❑ VHDL is a “free format” language

No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and
carriage return treated the same way.

Example:
if (a=b) then
or
if (a=b) then
or
if (a =
b) then
are all equivalent

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Comments

❑ Comments in VHDL are indicated with

a “double dash”, i.e., “--”
▪ Comment indicator can be placed anywhere in the line
▪ Any text that follows in the same line is treated as
a comment
▪ Carriage return terminates a comment
▪ No method for commenting a block extending over a couple of lines
Examples:
-- main subcircuit
Data_in <= Data_bus; -- reading data from the input FIFO

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 Comments

❑ Explain Function of Module to Other Designers

❑ Explanatory, Not Just Restatement of Code

❑ Locate Close to Code Described

– Put near executable code, not just in a header

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Design Entity

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 Design Entity

design entity

entity declaration Design Entity - most basic

building block of a design.

architecture 1
One entity can have
architecture 2 many different architectures.

architecture 3

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Entity Declaration

• Entity Declaration describes the interface of the component, i.e. input and
output ports.

Entity name Port names Port type

Semicolon

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
No Semicolon
z : OUT STD_LOGIC
);
END nand_gate;

Reserved words Port modes (data flow directions)

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 Entity declaration – simplified syntax

ENTITY entity_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
………….
port_name : signal_mode signal_type);
END entity_name;

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Architecture

• Describes an implementation of a design entity.

• Architecture example:

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

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 Architecture – simplified syntax

ARCHITECTURE architecture_name OF entity_name IS

[ declarations ]
BEGIN
code
END architecture_name;

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Entity Declaration & Architecture

nand_gate.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;
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 Mode In

Port signal Entity

Driver resides
outside the entity

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Mode out

Entity

Port signal

Can’t read out

c within an entity

Driver resides
inside the entity c <= z

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 Mode out with signal

Entity

Port signal

x z

c Signal X can be
read inside the entity

Driver resides z <= x

inside the entity
c <= x

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Mode inout

Port signal Entity

Signal can be
read inside the entity

Driver may reside

both inside and outside
of the entity

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 Mode buffer

Entity

Port signal

c
Port signal Z can be
read inside the entity

Driver resides
c <= z
inside the entity

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Port Modes

The Port Mode of the interface describes the direction in which data travels with respect to the component
❑ In: Data comes in this port and can only be read within the entity. It can appear only on the right side of
a signal or variable assignment.
❑ Out: The value of an output port can only be updated within the entity. It cannot be read. It can only
appear on the left side of a signal assignment.
❑ Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear
on both sides of a signal assignment.
❑ Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the
entity, which means that in an assignment statement the signal can appear on the left and right sides of
the <= operator

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 Libraries

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Library declarations

Library declaration

Use all definitions from the

LIBRARY ieee;
package
USE ieee.std_logic_1164.all; std_logic_1164

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate

IS
BEGIN
z <= a NAND b;
END model;
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 Library declarations - syntax

LIBRARY library_name;
USE library_name.package_name.package_parts;

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Fundamental parts of a library

LIBRARY

PACKAGE 1 PACKAGE 2

TYPES TYPES
CONSTANTS CONSTANTS
FUNCTIONS FUNCTIONS
PROCEDURES PROCEDURES
COMPONENTS COMPONENTS

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 Libraries

• ieee

Specifies multi-level logic system, Need to be explicitly

including STD_LOGIC, and declared
• std STD_LOGIC_VECTOR data types

Specifies pre-defined data types

• work
(BIT, BOOLEAN, INTEGER, REAL,
SIGNED, UNSIGNED, etc.), arithmetic
operations, basic type conversion Visible by default
functions, basic text i/o functions, etc.

Current designs after compilation

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STD_LOGIC Demystified

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 STD_LOGIC

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate

IS
BEGIN
z <= a NAND b;
END model;

What is STD_LOGIC you ask?

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STD_LOGIC type demystified

Value Meaning
‘X’ Forcing (Strong driven) Unknown

‘0’ Forcing (Strong driven) 0

‘1’ Forcing (Strong driven) 1

‘Z’ High Impedance

‘W’ Weak (Weakly driven) Unknown

Weak (Weakly driven) 0.

‘L’
Models a pull down.
Weak (Weakly driven) 1.
‘H’
Models a pull up.

‘-’ Don't Care

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 More on STD_LOGIC Meanings (1)

‘1’
‘X’
Contention on the bus
X

‘0’

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More on STD_LOGIC Meanings (2)

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 More on STD_LOGIC Meanings (3)

VDD

VDD

‘H’
‘1’

‘0’
‘L’

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More on STD_LOGIC Meanings (4)

•Do not care.

•Can be assigned to outputs for the case of invalid
‘-’ inputs (may produce significant improvement in
resource utilization after synthesis).
•Use with caution
‘1’ = ‘-’ give FALSE

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 Resolving logic levels

X 0 1 Z W L H -

X X X X X X X X X
0 X 0 X 0 0 0 0 X
1 X X 1 1 1 1 1 X
Z X 0 1 Z W L H X
W X 0 1 W W W W X
L X 0 1 L W L W X
H X 0 1 H W W H X
- X X X X X X X X

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Modeling Wires and Buses

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 Signals

SIGNAL a : STD_LOGIC;

a
1 wire

SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

b
8 bus

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Standard Logic Vectors

SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);
……….
a <= ‘1’;
b <= ”0000”; -- Binary base assumed by default
c <= B”0000”; -- Binary base explicitly specified
d <= ”0110_0111”; -- You can use ‘_’ to increase readability
e <= X”AF67”; -- Hexadecimal base
f <= O”723”; -- Octal base
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 Vectors and Concatenation

SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= ”0000”;
b <= ”1111”;
c <= a & b; -- c = ”00001111”

d <= ‘0’ & ”0001111”; -- d <= ”00001111”

e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &
‘1’ & ‘1’;
-- e <= ”00001111”

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VHDL Design Styles

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 VHDL Design Styles

VHDL Design
Styles

dataflow structural behavioral

Concurrent Components and Sequential statements

statements interconnects • Registers
• State machines
• Test benches

Subset most suitable for synthesis

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xor3 Example

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 Entity xor3

ENTITY xor3 IS
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
Result : OUT STD_LOGIC
);
end xor3;

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Dataflow Architecture (xor3 gate)

ARCHITECTURE dataflow OF xor3 IS

SIGNAL U1_out: STD_LOGIC;
BEGIN
U1_out <=A XOR B;
Result <=U1_out XOR C;
END dataflow;

U1_out

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 Dataflow Description

• Describes how data moves through the system and the

various processing steps.
• Data Flow uses series of concurrent statements to realize
logic. Concurrent statements are evaluated at the same time;
thus, order of these statements doesn’t matter.
• Data Flow is most useful style when series of Boolean
equations can represent a logic.

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Structural Architecture (xor3 gate)

ARCHITECTURE structural OF xor3 IS

I1
SIGNAL U1_OUT: STD_LOGIC;
Y
COMPONENT xor2 IS I2
PORT(
I1 : IN STD_LOGIC; XOR2
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
); A
END COMPONENT; B XOR3 Result
BEGIN C
U1: xor2 PORT MAP (I1 => A,
I2 => B,
Y => U1_OUT);

U2: xor2 PORT MAP (I1 => U1_OUT, U1_OUT

I2 => C, A
Y => Result);
END structural; B RESULT
C

XOR3
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 Component and Instantiation (1)

• Named association connectivity (recommended)

COMPONENT xor2 IS
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;

U1: xor2 PORT MAP (I1 => A,

I2 => B,
Y => U1_OUT);

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Component and Instantiation (2)

• Positional association connectivity

(not recommended)

COMPONENT xor2 IS
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;

U1: xor2 PORT MAP (A, B, U1_OUT);

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 Structural Description

• Structural design is the simplest to understand. This style is

the closest to schematic capture and utilizes simple building
blocks to compose logic functions.
• Components are interconnected in a hierarchical manner.
• Structural descriptions may connect simple gates or
complex, abstract components.
• Structural style is useful when expressing a design that is
naturally composed of sub-blocks.

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Behavioral Architecture (xor3 gate)

ARCHITECTURE behavioral OF xor3 IS

BEGIN
xor3_behave: PROCESS (A,B,C)
BEGIN
IF ((A XOR B XOR C) = '1') THEN
Result <= '1';
ELSE
Result <= '0';
END IF;
END PROCESS xor3_behave;
END behavioral;

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 Behavioral Description

• It accurately models what happens on the inputs and outputs

of the black box (no matter what is inside and how it works).
• This style uses PROCESS statements in VHDL.

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Testbenches

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 Testbench Block Diagram

Testbench

Processes
Design Under
Generating Test (DUT)
Stimuli

Observed Outputs

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Testbench Defined

❑ Testbench applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies
expected outputs.

❑ The results can be viewed in a waveform window or written to a file.

❑ Since Testbench is written in VHDL, it is not restricted to a single simulation tool (portability).

❑ The same Testbench can be easily adapted to test different implementations (i.e. different
architectures) of the same design.

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 Testbench Anatomy

ENTITY tb IS
--TB entity has no ports
END tb;

ARCHITECTURE arch_tb OF tb IS

--Local signals and constants

COMPONENT TestComp --All Design Under Test component declarations

PORT ( );
END COMPONENT;
-----------------------------------------------------
BEGIN
testSequence: PROCESS
-- Input stimuli
END PROCESS;

DUT:TestComp PORT MAP( -- Instantiations of DUTs

);
END arch_tb;

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Testbench for XOR3 (1)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY xor3_tb IS
END xor3_tb;

ARCHITECTURE xor3_tb_architecture OF xor3_tb IS

-- Component declaration of the tested unit
COMPONENT xor3
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
Result : OUT STD_LOGIC );
END COMPONENT;

-- Stimulus signals - signals mapped to the input and inout ports of tested entity
SIGNAL test_vector: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL test_result : STD_LOGIC;

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 Testbench for XOR3 (2)

BEGIN WAIT FOR 10 ns;

UUT : xor3 test_vector <= "100";
PORT MAP ( WAIT FOR 10 ns;
A => test_vector(0), test_vector <= "101";
B => test_vector(1), WAIT FOR 10 ns;
C => test_vector(2), test_vector <= "110";
Result => test_result); WAIT FOR 10 ns;
); test_vector <= "111";
Testing: PROCESS WAIT FOR 10 ns;
BEGIN END PROCESS;
test_vector <= "000"; END xor3_tb_architecture;
WAIT FOR 10 ns;
test_vector <= "001";
WAIT FOR 10 ns;
test_vector <= "010";
WAIT FOR 10 ns;
test_vector <= "011";

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What is a PROCESS?

– A process is a sequence of instructions referred to as sequential statements.

The keyword PROCESS

• A process can be given a unique name

Testing: PROCESS
using an optional LABEL
BEGIN
• This is followed by the keyword test_vector<=“00”;
PROCESS WAIT FOR 10 ns;
test_vector<=“01”;
• The keyword BEGIN is used to indicate WAIT FOR 10 ns;
the start of the process test_vector<=“10”;
WAIT FOR 10 ns;
• All statements within the process are test_vector<=“11”;
executed SEQUENTIALLY. Hence, WAIT FOR 10 ns;
END PROCESS;
order of statements is important.
• A process must end with the keywords
END PROCESS.

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 Execution of statements in a PROCESS

Testing: PROCESS
BEGIN
test_vector<=“00”;
• The execution of statements continues WAIT FOR 10 ns;
sequentially till the last statement in the test_vector<=“01”;

Order of execution
process. WAIT FOR 10 ns;
test_vector<=“10”;
• After execution of the last statement,
WAIT FOR 10 ns;
the control is again passed to the
test_vector<=“11”;
beginning of the process.
WAIT FOR 10 ns;
END PROCESS;

Program control is passed to the

first statement after BEGIN

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PROCESS with a WAIT Statement

• The last statement in the PROCESS is

Testing: PROCESS
a WAIT instead of WAIT FOR 10 ns. BEGIN
• This will cause the PROCESS to test_vector<=“00”;
suspend indefinitely when the WAIT
WAIT FOR 10 ns;
test_vector<=“01”;
Order of execution

statement is executed.
WAIT FOR 10 ns;
• This form of WAIT can be used in a test_vector<=“10”;
process included in a testbench when WAIT FOR 10 ns;
test_vector<=“11”;
all possible combinations of inputs
WAIT;
have been tested or a non-periodical
END PROCESS;
signal has to be generated.

Program execution stops here

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 WAIT FOR vs. WAIT

WAIT FOR: waveform will keep repeating

itself forever

0 1 2 3 0 1 2 3 …

WAIT : waveform will keep its state after the

last wait instruction.
…
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Loop Statement

• Loop Statement

FOR i IN range LOOP

statements
END LOOP;
• Repeats a Section of VHDL Code
• Example: process every element in an array in the same way

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 Loop Statement – Example (1)

Testing: PROCESS
BEGIN
test_vector<="000";
FOR i IN 0 TO 7 LOOP
WAIT FOR 10 ns;
test_vector<=test_vector+”001";
END LOOP;
END PROCESS;

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Loop Statement – Example (2)

Testing: PROCESS
BEGIN
test_ab<="00";
test_sel<="00";
FOR i IN 0 TO 3 LOOP
FOR j IN 0 TO 3 LOOP
WAIT FOR 10 ns;
test_ab<=test_ab+"01";
END LOOP;
test_sel<=test_sel+"01";
END LOOP;
END PROCESS;

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