LAB 2: NOISE MARGIN, POWER

AND FREQUENCY OF CMOS

CIRCUITS
VLSI LAB2

JANUARY 25, 2024

DEBASHISH KALITA
Procedure

1. The cadence simulator was used to simulate the NMOS inverter circuit by
changing parameters C (LOA CAPACITANCE) and the operating frequency.
2. The following observations were obtained..

Observation

C Analysis

For NMOS transistor of 400nm width with 10k load resistance same C parameters
were obtained in all cases when the load capacitance were changed.

I(leakage) Vil Vih NMil NMih Static Power

16.89285pA 497.332mV 912.125mV 887.875 497.332mV 30.407 pW
 Transient analysis

The transient analysis was done by changing operating frequency and load capacitance.

Operating
frequency
500 Mhz

switching dynamic
capacitance speed power(micro
(ff) tinr(ns) tinf(ns) tor(ns) tof(ns) tphl(ns) tplh(ns) tp(ns) (MHz) watt)
1 4.00503 3.0149 3.0496 4.01054 0.00551 0.0347 0.020105 49738.87093 1.62
10 4.00503 3.0149 3.1125 4.0179 0.01287 0.0976 0.055235 18104.46275 16.2
100 4.00503 3.0149 3.71997 4.02928 0.02425 0.70507 0.36466 2742.28048 162

100Mhz

switching dynamic
capacitance speed power(micro
(ff) tinr(ns) tinf(ns) tor(ns) tof(ns) tphl(ns) tplh(ns) tp(ns) (MHz) watt)
1 10.02509 5.07491 5.1095 10.0326 0.00751 0.03459 0.02105 47505.93824 0.324
10 10.02509 5.07491 5.1697 10.0443 0.01921 0.09479 0.057 17543.85965 3.24
100 10.02509 5.07491 5.77131 10.11665 0.09156 0.6964 0.39398 2538.199909 32.4

Interference from the observation table.

 It was observed that the switching speed decreases with increase in load
capacitance in the NMOS inverter.
 ecrease in switching speed was observed when operating frequency was lowered.
 The static power(in pico watts) was found to much less than that of dynamic
power(in micro watts).
 The switching speed of NMOS inverters was found to be in eci - giga hertz.

PART-B CMOS INVERTERS

Procedure
1. The circuit of CMOS inverter circuit was made on the Cadence simulation
tool and parameters like width , load capacitance , operating frequency
were varied and different parameters like propagation delay , switching
speed and dynamic power were measured and noted down in the
observation table below.
switchin
50 g dynamic
0 Capacitan width( tinr(ns tinf( tour(n touf(n tphl( tplh(n speed( power
Mh
z ce(ff) nm) ) ns) s) s) ns) s) tp(ns) G Hz) (Watts)

3.01 3.051 2.014 0.03 0.009 0.0234 42.70766 0.0000

1 400 2.005 5 85 98 685 98 15 603 0162

3.01 3.1399 2.049 0.124 0.044 0.084 11.8098 0.00001

10 400 2.005 5 3 42 93 42 675 6123 62

3.01 3.987 2.0178 0.972 0.012 0.4928 2.028891 0.00016

100 400 2.005 5 92 4 92 84 8 414 2

3.01 3.0373 2.0219 0.02 0.016 0.0196 50.8646 0.0000

1 800 2.005 5 7 5 237 95 6 999 0162

3.01 3.083 2.052 0.06 0.047 0.0579 17.26668 0.00001

10 800 2.005 5 77 06 877 06 15 393 62

3.01 3.5292 2.2365 0.514 0.2315 0.3729 2.68154 0.00016

100 800 2.005 5 5 9 25 9 2 0277 2

3.01 3.033 2.025 0.01 0.020 0.0194 51.45356 0.0000

1 1200 2.005 5 29 58 829 58 35 316 0162

3.01 3.064 2.055 0.04 0.050 19.9600 0.00001

10 1200 2.005 5 25 95 925 95 0.0501 7984 62

3.01 3.365 2.3227 0.35 0.3177 0.3338 2.99508

1000 1200 2.005 5 05 1 005 1 8 8056 0.00162

100
Mh
z

10.02 5.07 10.04 0.01 0.043 0.0313 31.87759 0.0000

1 400 505 49 5.118 469 964 1 7 005 00324

10.02 5.07 5.205 10.07 0.04 0.090 11.05277 0.0000

10 400 505 49 9 5 995 0.131 475 701 0324

10.02 5.07 6.065 10.374 0.34 0.990 0.670 1.492527 0.0000

100 400 505 49 359 6 955 459 0045 289 324

10.02 5.07 5.1047 10.04 0.02 0.029 0.0259 38.5081 0.0000

1 800 505 49 97 709 204 897 685 9262 00324

10.02 5.07 5.1502 10.077 0.05 0.075 0.0639 15.62976 0.0000

10 800 505 49 91 62 257 391 805 219 0324

10.02 5.07 5.604 10.377 0.352 0.529 0.4410 2.267188 0.0000

100 800 505 49 31 79 74 41 75 12 324

10.02 5.07 5.101 10.05 0.02 0.026 38.75968 0.0000

1 1200 505 49 01 054 549 11 0.0258 992 00324
10.02 5.07 5.1316 10.08 0.05 0.056 0.0563 17.73584 0.0000
10 1200 505 49 76 104 599 776 83 236 0324
 CMOS inverter circuit

C Analysis of CMOS inverter circuit.

Transient Analysis of CMOS circuit

2. In the second step C analysis was done and the observations such as
Noise
margins , Vil , Vih and leakage current were noted and are found below.

NMOS PMOS VOH VOL VIH VIL Vm NMH NML

Width Width High Output Low Output High Low Input Switching Noise Noise
Voltage Voltage Input Voltage Threshold Margin Margin Low
Voltage Voltage High
2u 2u 1.8v 0v 0.860v 0.611v 0.756v 0.94v 0.611v
2u 4u 1.8v 0v 0.949v 0.688v 0.828v 0.851v 0.688v
2u 6u 1.8v 0v 1.003v 0.754v 0.875v 0.797v 0.754v

NMOS PMOS VOH VOL VIH VIL Vm NMH NML

Width Width High Low High Input Low Input Switching Noise Noise Margin
Output Output Voltage Voltage Threshold Margin Low
Voltage Voltage Voltage High
2u 4u 1v 0v 0.527v 0.453v 0.482v 0.473v 0.453v
2u 4u 1.8v 0v 0.949v 0.688v 0.828v 0.851v 0.688v
 Conclusion from C analysis of CMOS Inverter:

1. For CMOS inverter; at constant supply voltage, when we increase the width of PMOS, keeping
NMOS width constant. We observe that NMH decreases but NML increases. This happens as the
PMOS which is a Pull Up transistor becomes stronger than NMOS, and the switching threshold
voltage Vm also increases that it shifts rightwards in the output plot.
2. For CMOS inverter; at constant width of NMOS and PMOS, when we increase the supply voltage.
We observe that NMH and NML both increases. The the switching threshold voltage Vm also
increases.
3. We also conclude that CMOS inverters are better than Resistive Load NMOS inverters as
the CMOS inverters have a much higher NMH and NML. And it’s evident from the transfer
characteristics that CMOS inverters exhibit much better and sharp inversion mechanism than
Resistive Load NMOS inverters.

Conclusion from Transient analysis of Inverters:

1. For CMOS inverter; at constant supply voltage and constant width of transistors, when we increase
the value of load capacitor, we observe that the propagation delay time increases but the switching
frequency(speed) decreases. Similar conclusion we can draw from Resistive Load NMOS inverter.
2. For CMOS inverter; at constant width of transistors and constant load, when we increase the supply
voltage, we observe that the propagation delay time decreases but the switching frequency(speed)
increases. Similar conclusion we can draw from Resistive Load NMOS inverter.
3. For CMOS inverter; at constant supply voltage and constant load, keeping NMOS width constant
when we increase width of PMOS, we observe that the propagation delay time decreases.
4. We also draw a general conclusion that CMOS inverters have higher switching frequency and a lower
propagation delay time than Resistive Load NMOS inverters. Thus, performance of CMOSinverters is
much better Resistive Load NMOS inverters.
5. Overall average power that is dynamic plus static power of CMOS inverters are very less than
Resistive Load NMOS inverters, though their dynamic power values are same but static power
consumption of Resistive Load NMOS inverters is much higher.
6. Increasing width of transistor doesn’t affect dynamic power but increases the static power
consumption.
7. Increasing the supply voltage increases both static and dynamic power consumption.
8. Thus, CMOS inverters are more power efficient than Resistive Load NMOS inverters.
9. Thus, CMOS inverters are widely used to implement digital logics due to the above drawn
conclusions.

PART 2
Solution A

When the input is 0 V, Vgs for the NMOS device is 0V and Vgs for the PMOS is -V . For typical
supply voltages, the current through the PMOS in this case dominates and the output is pulled to V . As
V falls to lower voltages, eventually pushing the PMOS into subthreshold the currents will eventually begin
to approach comparable levels and the simple CMOS inverter will become a ratioed circuit. Using a wider
PMOS would decrease the minimum possible supply voltage since this would increase the strength ofthe PMOS
relative to the NMOS and allow the PMOS current to overpower the NMOS for lower supply volt- ages. FS
would be the worst case process corner, since the PMOS is weakened in comparison to the NMOS and looses
some ability to pull up the output node. So, for a given supply voltage there is a minimum width requirement
on the PMOS to maintain proper operation and the minimum size is largest for the FS corner.

Solution B

In this case, Vgs for the PMOS is 0 V and Vgs for the NMOS is lowered with supply voltage. Using a wider
PMOS would increase the minimum supply voltage since the PMOS would be stronger and have more leak- age
current to pull the output up from its desired value of 0 V. The worst case corner would be SF since this would
also increase the output voltage for a given supply voltage. So for a given supply voltage,there is a maximum
width for the PMOS to maintain proper operation and the maximum width is smallestfor the SF corner.
Comparing the results for parts a and b, it is clear that since one case requires large PMOS and one case
requires small PMOS there must be an optimum PMOS size to operate at the lowest possible supply voltage.

Solution C

Simulation for finding the minimum supply voltage

The minimum supply voltage for CMOS inverter with Wn=2u and Wp=4u to obtain the
desired output characteristics is Vdd=0.1052v.

The switching frequency at this point was found to be 989 MHz..