Introduction

In our previous sections, we learned about combinational circuit and their working.
The combinational circuits have set of outputs, which depends only on the present
combination of inputs. Below is the block diagram of the synchronous logic circuit.

The sequential circuit is a special type of circuit that has a series of inputs and
outputs. The outputs of the sequential circuits depend on both the combination of
present inputs and previous outputs. The previous output is treated as the present
state. So, the sequential circuit contains the combinational circuit and its memory
storage elements. A sequential circuit doesn't need to always contain a
combinational circuit. So, the sequential circuit can contain only the memory
element.

Difference between the combinational circuits and sequential circuits are given
below:

Combinational Circuits Sequential Circuits

1 The outputs of the combinational circuit depend only on the The outputs of the sequential c
) present inputs. state(previous output).

2 The feedback path is not present in the combinational The feedback path is present in
) circuit.

3 In combinational circuits, memory elements are not In the sequential circuit, memo
 ) required.

4 The clock signal is not required for combinational circuits. The clock signal is required for
)

5 The combinational circuit is simple to design. It is not simple to design a sequ

)

Types of Sequential Circuits

Asynchronous sequential circuits
The clock signals are not used by the Asynchronous sequential circuits. The
asynchronous circuit is operated through the pulses. So, the changes in the input can
change the state of the circuit. The asynchronous circuits do not use clock pulses.
The internal state is changed when the input variable is changed. The un-clocked
flip-flops or time-delayed are the memory elements of asynchronous sequential
circuits. The asynchronous sequential circuit is similar to the combinational circuits
with feedback.

Synchronous sequential circuits

In synchronous sequential circuits, synchronization of the memory element's state is
done by the clock signal. The output is stored in either flip-flops or latches(memory
devices). The synchronization of the outputs is done with either only negative edges
of the clock signal or only positive edges.

Clock Signal and Triggering

Clock signal
A clock signal is a periodic signal in which ON time and OFF time need not be the
same. When ON time and OFF time of the clock signal are the same, a square wave is
used to represent the clock signal. Below is a diagram which represents the clock
signal:
A clock signal is considered as the square wave. Sometimes, the signal stays at logic,
either high 5V or low 0V, to an equal amount of time. It repeats with a certain time
period, which will be equal to twice the 'ON time' or 'OFF time'.

Types of Triggering
These are two types of triggering in sequential circuits:

Level triggering
The logic High and logic Low are the two levels in the clock signal. In level triggering,
when the clock pulse is at a particular level, only then the circuit is activated. There
are the following types of level triggering:

Positive level triggering

In a positive level triggering, the signal with Logic High occurs. So, in this triggering,
the circuit is operated with such type of clock signal. Below is the diagram of positive
level triggering:

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Negative level triggering

In negative level triggering, the signal with Logic Low occurs. So, in this triggering,
the circuit is operated with such type of clock signal. Below is the diagram of
Negative level triggering:
Edge triggering
In clock signal of edge triggering, two types of transitions occur, i.e., transition either
from Logic Low to Logic High or Logic High to Logic Low.

Based on the transitions of the clock signal, there are the following types of edge
triggering:

Positive edge triggering

The transition from Logic Low to Logic High occurs in the clock signal of positive
edge triggering. So, in positive edge triggering, the circuit is operated with such type
of clock signal. The diagram of positive edge triggering is given below.

Negative edge triggering

The transition from Logic High to Logic low occurs in the clock signal of negative
edge triggering. So, in negative edge triggering, the circuit is operated with such
type of clock signal. The diagram of negative edge triggering is given below.

Ba
sics of Flip Flop
A circuit that has two stable states is treated as a flip flop. These stable states are
used to store binary data that can be changed by applying varying inputs. The flip
flops are the fundamental building blocks of the digital system. Flip flops and latches
are examples of data storage elements. In the sequential logical circuit, the flip flop is
the basic storage element. The latches and flip flops are the basic storage elements
but different in working. There are the following types of flip flops:

SR Flip Flop
The S-R flip flop is the most common flip flop used in the digital system. In SR flip
flop, when the set input "S" is true, the output Y will be high, and Y' will be low. It is
required that the wiring of the circuit is maintained when the outputs are established.
We maintain the wiring until set or reset input goes high, or power is shutdown.

The S-R flip flop is the simplest and easiest circuit to understand.

Truth Table:
J-K Flip-flop
The JK flip flop is used to remove the drawback of the S-R flip flop, i.e., undefined
states. The JK flip flop is formed by doing modification in the SR flip flop. The S-R flip
flop is improved in order to construct the J-K flip flop. When S and R input is set to
true, the SR flip flop gives an inaccurate result. But in the case of JK flip flop, it gives
the correct output.

In J-K flip flop, if both of its inputs are different, the value of J at the next clock edge
is taken by the output Y. If both of its input is low, then no change occurs, and if high
at the clock edge, then from one state to the other, the output will be toggled. The
JK Flip Flop is a Set or Reset Flip flop in the digital system.

Truth Table:

D Flip Flop
D flip flop is a widely used flip flop in digital systems. The D flip flop is mostly used in
shift-registers, counters, and input synchronization.

Truth Table:

T Flip Flop
Just like JK flip-flop, T flip flop is used. Unlike JK flip flop, in T flip flop, there is only
single input with the clock input. The T flip flop is constructed by connecting both of
the inputs of JK flip flop together as a single input.
The T flip flop is also known as Toggle flip-flop. These T flip-flops are able to find
the complement of its state.

Truth Table:

SR Flip Flop
The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET and RESET.
The SET input 'S' set the device or produce the output 1, and the RESET input 'R' reset the
device or produce the output 0. The SET and RESET inputs are labeled as S and R,
respectively.

The SR flip flop stands for "Set-Reset" flip flop. The reset input is used to get back the flip
flop to its original state from the current state with an output 'Q'. This output depends on the
set and reset conditions, which is either at the logic level "0" or "1".

The NAND gate SR flip flop is a basic flip flop which provides feedback from both of its
outputs back to its opposing input. This circuit is used to store the single data bit in the
memory circuit. So, the SR flip flop has a total of three inputs, i.e., 'S' and 'R', and current
output 'Q'. This output 'Q' is related to the current history or state. The term "flip-flop" relates
to the actual operation of the device, as it can be "flipped" to a logic set state or "flopped"
back to the opposing logic reset state.
The NAND Gate SR Flip-Flop
We can implement the set-reset flip flop by connecting two cross-coupled 2-input NAND
gates together. In the SR flip flop circuit, from each output to one of the other NAND gate
inputs, feedback is connected. So, the device has two inputs, i.e., Set 'S' and Reset 'R' with
two outputs Q and Q' respectively. Below are the block diagram and circuit diagram of the S-
R flip flop.

Block Diagram:

Circuit Diagram:

The Set State

In the above diagram, when the input R is set to false or 0 and the input S is set to true or 1,
the NAND gate Y has an input 0, which will produce the output Q' 1. The value of Q' is faded
to the NAND gate 'X' as input 'A', and now both the inputs of the NAND gate 'X' are
1(S=A=1), which will produce the output 'Q' 0.

Now, if the input R is changed to 1 with 'S' remaining 1, the inputs of NAND gate 'Y' is R=1
and B=0. Here, one of the inputs is also 0, so the output of Q' is 1. So, the flip flop circuit is
set or latched with Q=0 and Q'=1.

Reset State
The output Q' is 0, and output Q is 1 in the second stable state. It is given by R =1 and S = 0.
One of the inputs of NAND gate 'X' is 0, and its output Q is 1. Output Q is faded to NAND
gate Y as input B. So, both the inputs to NAND gate Y are set to 1, therefore, Q' = 0.

Now, if the input S is changed to 0 with 'R' remaining 1, the output Q' will be 0 and there is
no change in state. So, the reset state of the flip flop circuit has been latched, and the set/reset
actions are defined in the following truth table:

From the above truth table, we can see that when set 'S' and reset 'R' inputs are set to 1, the
outputs Q and Q' will be either 1 or 0. These outputs depend on the input state S or R before
the input condition exist. So, when the inputs are 1, the states of the outputs remain
unchanged.

The condition in which both the inputs states are set to 0 is treated as invalid

and must be avoided. JK Flip Flop

The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the following
switching problems:

o When Set 'S' and Reset 'R' inputs are set to 0, this condition is always avoided.
o When the Set or Reset input changes their state while the enable input is 1, the
incorrect latching action occurs.

The JK Flip Flop removes these two drawbacks of SR Flip Flop.

The JK flip flop is one of the most used flip flops in digital circuits. The JK flip flop is a
universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are the
shortened abbreviated letters for Set and Reset, but J and K are not. The J and K are
themselves autonomous letters which are chosen to distinguish the flip flop design
from other types.

The JK flip flop work in the same way as the SR flip flop work. The JK flip flop has 'J'
and 'K' flip flop instead of 'S' and 'R'. The only difference between JK flip flop and SR
flip flop is that when both inputs of SR flip flop is set to 1, the circuit produces the
invalid states as outputs, but in case of JK flip flop, there are no invalid states even if
both 'J' and 'K' flip flops are set to 1.

The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry.
The invalid or illegal output condition occurs when both of the inputs are set to 1
and are prevented by the addition of a clock input circuit. So, the JK flip-flop has four
possible input combinations, i.e., 1, 0, "no change" and "toggle". The symbol of JK flip
flop is the same as SR Bistable Latch except for the addition of a clock input.

Block Diagram:

Circuit Diagram:
In SR flip flop, both the inputs 'S' and 'R' are replaced by two inputs J and K. It means
the J and K input equates to S and R, respectively.

The two 2-input AND gates are replaced by two 3-input NAND gates. The third input
of each gate is connected to the outputs at Q and Q'. The cross-coupling of the SR
flip-flop permits the previous invalid condition of (S = "1", R = "1") to be used to
produce the "toggle action" as the two inputs are now interlocked.

If the circuit is "set", the J input is interrupted from the "0" position of Q' through the
lower NAND gate. If the circuit is "RESET", K input is interrupted from 0 positions of
Q through the upper NAND gate. Since Q and Q' are always different, we can use
them to control the input. When both inputs 'J' and 'K' are set to 1, the JK toggles the
flip flop as per the given truth table.

Truth Table:
When both of the inputs of JK flip flop are set to 1 and clock input is also pulse
"High" then from the SET state to a RESET state, the circuit will be toggled. The JK flip
flop work as a T-type toggle flip flop when both of its inputs are set to 1.

The JK flip flop is an improved clocked SR flip flop. But it still suffers from
the "race" problem. This problem occurs when the state of the output Q is changed
before the clock input's timing pulse has time to go "Off". We have to keep short
timing plus period (T) for avoiding this period.

D Flip Flop
In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0" and
RESET = "0" is forbidden. It is the drawback of the SR flip flop. This state:

1. Override the feedback latching action.

2. Force both outputs to be 1.
3. Lose the control by the input, which first goes to 1, and the other input
remains "0" by which the resulting state of the latch is controlled.

We need an inverter to prevent this from happening. We connect the inverter

between the Set and Reset inputs for producing another type of flip flop circuit
called D flip flop, Delay flip flop, D-type Bistable, D-type flip flop.

The D flip flop is the most important flip flop from other clocked types. It ensures
that at the same time, both the inputs, i.e., S and R, are never equal to 1. The Delay
flip-flop is designed using a gated SR flip-flop with an inverter connected between
the inputs allowing for a single input D(Data).

This single data input, which is labeled as "D" used in place of the "Set" input and for
the complementary "Reset" input, the inverter is used. Thus, the level-sensitive D-
type or D flip flop is constructed from a level-sensitive SR flip flop.

So, here S=D and R= ~D(complement of D)

Block Diagram
Circuit Diagram

We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output and
another to "RESET" the output. By using an inverter, we can set and reset the outputs
with only one input as now the two input signals complement each other. In SR flip
flop, when both the inputs are 0, that state is no longer possible. It is an ambiguity
that is removed by the complement in D-flip flop.

In D flip flop, the single input "D" is referred to as the "Data" input. When the data
input is set to 1, the flip flop would be set, and when it is set to 0, the flip flop would
change and become reset. However, this would be pointless since the output of the
flip flop would always change on every pulse applied to this data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from
the flip flop's latching circuitry. When the clock input is set to true, the D input
condition is only copied to the output Q. This forms the basis of another sequential
device referred to as D Flip Flop.
When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both
set to 1. So it will not change the state and store the data present on its output
before the clock transition occurred. In simple words, the output is "latched" at either
0 or 1.

Truth Table for the D-type Flip Flop

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop assumed
these symbols as edge-triggers.

T Flip Flop
In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a single
input called "Toggle" or "Trigger" input to avoid an intermediate state occurrence.
Now, this flip-flop work as a Toggle switch. The next output state is changed with the
complement of the present state output. This process is known as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T
Flip Flop" has only one input, which is constructed by connecting the input of JK flip
flop. This single input is called T. In simple words, we can construct the "T Flip Flop"
by converting a "JK Flip Flop". Sometimes the "T Flip Flop" is referred to as single
input "JK Flip Flop".

Block diagram of the "T-Flip Flop" is given where T defines the "Toggle input", and
CLK defines the clock signal input.
T Flip Flop Circuit
There are the following two methods which are used to form the "T Flip Flop":

o By connecting the output feedback to the input in "SR Flips Flop".

o We pass the output that we get after performing the XOR operation of T and
QPREV output as the D input in D Flip Flop.

Construction
The "T Flip Flop" is designed by passing the AND gate's output as input to the NOR
gate of the "SR Flip Flop". The inputs of the "AND" gates, the present output state Q,
and its complement Q' are sent back to each AND gate. The toggle input is passed to
the AND gates as input. These gates are connected to the Clock (CLK) signal. In the
"T Flip Flop", a pulse train of narrow triggers are passed as the toggle input, which
changes the flip flop's output state. The circuit diagram of the "T Flip Flop" using "SR
Flip Flop" is given below:
The "T Flip Flop" is formed using the "D Flip Flop". In D flip - flop, the output after
performing the XOR operation of the T input with the output "Q PREV" is passed as the
D input. The logical circuit of the "T-Flip Flop" using the "D Flip Flop" is given below:

The simplest construction of a D Flip Flop is with JK Flip Flop. Both the inputs of the
"JK Flip Flop" are connected as a single input T. Below is the logical circuit of the T
Flip Flop" which is formed from the "JK Flip Flop":
Truth Table of T Flip Flop

The upper NAND gate is enabled, and the lower NAND gate is disabled when the
output Q To is set to 0. make the flip flop in "set state(Q=1)", the trigger passes the S
input in the flip flop.

The upper NAND gate is disabled, and the lower NAND gate is enabled when the
output Q is set to 1. The trigger passes the R input in the flip flop to make the flip
flop in the reset state(Q=0).

Operations of T-Flip Flop

The next sate of the T flip flop is similar to the current state when the T input is set to
false or 0.

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o If toggle input is set to 0 and the present state is also 0, the next state will be
0.
o If toggle input is set to 0 and the present state is 1, the next state will be 1.
The next state of the flip flop is opposite to the current state when the toggle input is
set to 1.

o If toggle input is set to 1 and the present state is 0, the next state will be 1.
o If toggle input is set to 1 and the present state is 1, the next state will be 0.

The "T Flip Flop" is toggled when the set and reset inputs alternatively changed by
the incoming trigger. The "T Flip Flop" requires two triggers to complete a full cycle
of the output waveform. The frequency of the output produced by the "T Flip Flop" is
half of the input frequency. The "T Flip Flop" works as the "Frequency Divider Circuit."

In "T Flip Flop", the state at an applied trigger pulse is defined only when the
previous state is defined. It is the main drawback of the "T Flip Flop".

The "T flip flop" can be designed from "JK Flip Flop", "SR Flip Flop", and "D Flip Flop"
because the "T Flip Flop" is not available as ICs. The block diagram of "T Flip Flop"
using "JK Flip Flop" is given below:

Registers
A Register is a collection of flip flops. A flip flop is used to store single bit digital
data. For storing a large number of bits, the storage capacity is increased by
grouping more than one flip flops. If we want to store an n-bit word, we have to use
an n-bit register containing n number of flip flops.

The register is used to perform different types of operations. For performing the
operations, the CPU use these registers. The faded inputs to the system will store into
the registers. The result returned by the system will store in the registers. There are
the following operations which are performed by the registers:

Fetch:
It is used

o To take the instructions given by the users.

o To fetch the instruction stored into the main memory.

Decode:
The decode operation is used to interpret the instructions. In decode, the operation
performed on the instructions is identified by the CPU. In simple words, the decode
operation is used to decode the instructions.

Execute:
The execution operation is used to store the result produced by the CPU into the
memory. After storing this result, it is displayed on the user screen.

Types of Registers
There are various types of registers which are as follows:

MAR or Memory Address Register

The MAR is a special type of register that contains the memory address of the data
and instruction. The main task of the MAR is to access instruction and data from
memory in the execution phase. The MAR stores the address of the memory location
where the data is to be read or to be stored by the CPU.

Program Counter
The program counter is also called an instruction address register or instruction
pointer. The next memory address of the instruction, which is going to be executed
after completing the execution of current instruction is contained in the program
counter. In simple words, the program counter contains the memory address of the
location of the next instruction.

Accumulator Register
The CPU mostly uses an accumulator register. The accumulator register is used to
store the system result. All the results will be stored in the accumulator register when
the CPU produces some results after processing.

MDR or Memory Data Register

Memory Data Register is a part of the computer's control unit. It contains the data
that we want to store in the computer storage or the data fetched from the
computer storage. The MDR works as a buffer that contains anything for which the
processor is ready to use it. The MDR contains the copied data of the memory for the
processor. Firstly the MDR holds the information, and then it goes to the decoder.

The data which is to be read out or written into the address location is contained in
the Memory Data Register.

The data is written in one direction when it is fetched from memory and placed into
the MDR. In write instruction, the data place into the MDR from another CPU register.
This CPU register writes the data into the memory. Half of the minimal interface
between the computer storage and the microprogram is the memory data address
register, and the other half is the memory data register.

Index Register
The Index Register is the hardware element that holds the number. The number
adds to the computer instruction's address to create an effective address. In CPU, the
index register is a processor register used to modify the operand address during the
running program.

Memory Buffer Register

Memory Buffer Register is mostly called MBR. The MBR contains the Metadata of the
data and instruction written in or read from memory. In simple words, it adds is used
to store the upcoming data/instruction from the memory and going to memory.

Data Register
The data register is used to temporarily store the data. This data transmits to or from
a peripheral device.

Shift Register
A group of flip flops which is used to store multiple bits of data and the data is
moved from one flip flop to another is known as Shift Register. The bits stored in
registers shifted when the clock pulse is applied within and inside or outside the
registers. To form an n-bit shift register, we have to connect n number of flip flops.
So, the number of bits of the binary number is directly proportional to the number of
flip flops. The flip flops are connected in such a way that the first flip flop's output
becomes the input of the other flip flop.

A Shift Register can shift the bits either to the left or to the right. A Shift Register,
which shifts the bit to the left, is known as "Shift left register", and it shifts the bit
to the right, known as "Right left register".

The shift register is classified into the following types:

o Serial In Serial Out

o Serial In Parallel Out
o Parallel In Serial Out
o Parallel In Parallel Out
o Bi-directional Shift Register
o Universal Shift Register

Serial IN Serial OUT

In "Serial Input Serial Output", the data is shifted "IN" or "OUT" serially. In SISO, a
single bit is shifted at a time in either right or left direction under clock control.

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Initially, all the flip-flops are set in "reset" condition i.e. Y 3 = Y2 = Y1 = Y0 = 0. If we

pass the binary number 1111, the LSB bit of the number is applied first to the Din bit.
The D3 input of the third flip flop, i.e., FF-3, is directly connected to the serial data
input D3. The output Y3 is passed to the data input d 2 of the next flip flop. This
process remains the same for the remaining flip flops. The block diagram of
the "Serial IN Serial OUT" is given below.

Block Diagram:

Operation
When the clock signal application is disabled, the outputs Y 3 Y2 Y1 Y0 = 0000. The LSB
bit of the number is passed to the data input D in, i.e., D3. We will apply the clock, and
this time the value of D 3 is 1. The first flip flop, i.e., FF-3, is set, and the word is stored
in the register at the first falling edge of the clock. Now, the stored word is 1000.

The next bit of the binary number, i.e., 1, is passed to the data input D 2. The second
flip flop, i.e., FF-2, is set, and the word is stored when the next negative edge of the
clock hits. The stored word is changed to 1100.
The next bit of the binary number, i.e., 1, is passed to the data input D 1, and the clock
is applied. The third flip flop, i.e., FF-1, is set, and the word is stored when the
negative edge of the clock hits again. The stored word is changed to 1110.

Similarly, the last bit of the binary number, i.e., 1, is passed to the data input D 0, and
the clock is applied. The last flip flop, i.e., FF-0, is set, and the word is stored when the
clock's negative edge arrives. The stored word is changed to 1111.

Truth Table

Waveforms
Serial IN Parallel OUT
In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip
flop, and outputs are fetched in a parallel way. The data is passed bit by bit in the
register, and the output remains disabled until the data is not passed to the data
input. When the data is passed to the register, the outputs are enabled, and the flip
flops contain their return value

Below is the block diagram of the 4-bit serial in the parallel-out shift register. The
circuit having four D flip-flops contains a clear and clock signal to reset these four flip
flops. In SIPO, the input of the second flip flop is the output of the first flip flop, and
so on. The same clock signal is applied to each flip flop since the flip flops
synchronize each other. The parallel outputs are used for communication.

Block Diagram
Parallel IN Serial OUT
In the "Parallel IN Serial OUT" register, the data is entered in a parallel way, and the
outcome comes serially. A four-bit "Parallel IN Serial OUT" register is designed
below. The input of the flip flop is the output of the previous Flip Flop. The input and
outputs are connected through the combinational circuit. Through this
combinational circuit, the binary input B 0, B1, B2, B3 are passed. The shift mode and
the load mode are the two modes in which the "PISO" circuit works.

Load mode
The bits B0, B1, B2, and B3 are passed to the corresponding flip flops when the second,
fourth, and sixth "AND" gates are active. These gates are active when the shift or load
bar line set to 0. The binary inputs B0, B1, B2, and B3 will be loaded into the
respective flip-flops when the edge of the clock is low. Thus, parallel loading occurs.

Shift mode
The second, fourth, and sixth gates are inactive when the load and shift line set to 0.
So, we are not able to load data in a parallel way. At this time, the first, third, and fifth
gates will be activated, and the shifting of the data will be left to the right bit. In this
way, the "Parallel IN Serial OUT" operation occurs.

Block Diagram
Parallel IN Parallel OUT
In "Parallel IN Parallel OUT", the inputs and the outputs come in a parallel way in
the register. The inputs A0, A1, A2, and A3, are directly passed to the data inputs D 0, D1,
D2, and D3 of the respective flip flop. The bits of the binary input is loaded to the flip
flops when the negative clock edge is applied. The clock pulse is required for loading
all the bits. At the output side, the loaded bits appear.

Block Diagram
Bidirectional Shift Register
The binary number after shifting each bit of the number to the left by one position
will be equivalent to the number produced by multiplying the original number by 2.
In the same way, the binary number after shifting each bit of the number to the right
by one position will be equivalent to the number produced by dividing the original
number by 2.

For performing the multiplication and division operation using the shift register, it is
required that the data should be moved in both the direction, i.e., left or right in the
register. Such registers are called the "Bidirectional" shift register.

Below is the diagram of 4-bit "bidirectional" shift register where DR is the "serial
right shift data input", DL is the "left shift data input", and M is the "mode select
input".

Block Diagram
Operations
1) Shift right operation(M=1)

o The first, third, fifth, and seventh AND gates will be enabled, but the second,
fourth, sixth, and eighth AND gates will be disabled.
o The data present on the data input DR is shifted bit by bit from the fourth flip
flop to the first flip flop when the clock pulse is applied. In this way, the shift
right operation occurs.

2) Shift left operation(M=0)

o The second, fourth, sixth and eighth AND gates will be enabled, but the AND
gates first, third, fifth, and seventh will be disabled.
o The data present on the data input DR is shifted bit by bit from the first flip
flop to the fourth flip flop when the clock pulse is applied. In this way, the shift
right operation occurs.

Universal Shift Register

A register where the data is shifted in one direction is known as the "uni-
directional" shift register. A register in which the data is shifted in both the direction
is known as "bi-directional" shift register. A "Universal" shift register is a special
type of register that can load the data in a parallel way and shift that data in both
directions, i.e., right and left.

The input M, i.e., the mode control input, is set to 1 to perform the parallel loading
operation. If this input set to 0, then the serial shifting operation is performed. If we
connect the mode control input with the ground, then the circuit will work as a "bi-
directional" register. The diagram of the universal shift register is given below. When
the input is passed to the serial input, the register performs the "serial left"
operation. When the input is passed to the input D, the register performs the serial
right operation.

Block Diagram