CND 211: Advanced Digital Design

I2C Bus ASIC Implementation

Section #: 8

Submitted by:
Student Name ID
Mohammed Khaled Ali v23010087
Amr Khalid Salah Attia v23010080

Submitted to TA: Eng. Abdulaziz El-safty

Date: 10/5/2024
Synthesis Script

set design i2c_master_top

set_app_var search_path
/home/vlsi/Synopsys/I2C/standardCell/SAED90nm_EDK_100720
17/SAED90_EDK/SAED_EDK90nm/Digital_Standard_cell_Library/
synopsys/models

set_app_var target_library "saed90nm_max_lth.db"

set_app_var link_library "$target_library"
sh rm -rf work
sh mkdir -p work
define_design_lib work -path ./work
analyze -library work -format verilog ../rtl/${design}.v
elaborate $design -lib work
current_design
#start_gui
check_design

source -echo -verbose ./cons/cons.tcl

link
set_fix_multiple_port_nets -all
compile -map_effort medium
check_timing
report_area > ./report/synth_area.rpt
report_cell > ./report/synth_cells.rpt
report_qor > ./report/synth_qor.rpt
report_resources > ./report/synth_resources.rpt
report_timing -max_paths 10 > ./report/synth_timing.rpt
write_sdc output/${design}.sdc
define_name_rules no_case -case_insensitive
change_names -rule no_case -hierarchy
change_names -rule verilog -hierarchy
set verilogout_no_tri true
set verilogout_equation false
write -hierarchy -format verilog -output output/${design}.v
write -f ddc -hierarchy -output output/${design}.ddc

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set_svf -off

Synthesis Screenshot

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Synthesis Area

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Constraints

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Screenshots of some timing paths

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7 | Page
Formal Verification

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 Floorplan Script

cd script
source setup.tcl
open_block /home/vlsi/Synopsys/I2C/pnr/script/counter.dlib:pit_top.design
set_parasitic_parameters -late_spec maxTLU -early_spec minTLU
initialize_floorplan -core_utilization 0.6 -side_ratio {1 1} -core_offset {10}
set_app_options -name place.coarse.fix_hard_macros -value false
set_app_options -name plan.place.auto_create_blockages -value auto
create_placement -floorplan
create_block_pin_constraint -allowed_layers {M3 M4 M5 M6}
set_app_options -name plan.pins.incremental -value false -block [current_block]
place_pins -self
save_block counter.dlib:i2c_master_top.design
set_app_options -name place.coarse.fix_hard_macros -value false

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Floorplan Screenshot

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 Powerplan Script

start_gui
open_block /home/vlsi/Synopsys/I2C/pnr/counter.dlib:pit_top_floorplan.design

# copy block to a new block to work on it

copy_block -from_block counter.dlib:i2c_master_top.design -to_block power_plan
current_block power_plan.design

# remove ignored layer M8

report_ignored_layers
remove_ignored_layers -all -max_routing_layer -min_routing_layer
report_ignored_layers

set_app_option -name plan.pgroute.auto_connect_pg_net -value true

#set_app_option -name plan.pgroute.connect_user_route_shapes -value true
#set_app_option -name plan.pgroute.disable_floating_removal -value true
#set_app_option -name plan.pgroute.disable_trimming -value true

create_net -power VDD

create_net -ground VSS

# hierarchical [include top module + sub modules]

connect_pg_net -net VDD [get_pins -hierarchical "*/VDD"]
connect_pg_net -net VSS [get_pins -hierarchical "*/VSS"]

#PG RING CREATION

create_pg_ring_pattern ring_pattern -horizontal_layer M9 -horizontal_width {5}

-horizontal_spacing {2} -vertical_layer M8 -vertical_width {5} -vertical_spacing

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{2}

set_pg_strategy core_ring -core -pattern \

{{pattern: ring_pattern}{nets: {VDD VSS}}{offset: {0.8 0.8}}} \
-extension {{stop: innermost_ring}}

compile_pg -strategies core_ring

# PG MESH CREATION

create_pg_mesh_pattern pg_mesh1 -parameters {w1 p1 w2 p2 f t} -layers

{{{vertical_layer: M8} {width: @w1} {spacing: interleaving} {pitch: @p1}
{offset: @f} {trim: @t}} {{horizontal_layer: M9 } {width: @w2} {spacing:
interleaving} {pitch: @p2} {offset: @f} {trim: @t}}}

set_pg_strategy s_mesh1 \
-pattern {{pattern: pg_mesh1} {nets: {VDD VSS VSS VDD}} \
{offset_start: 5 5} {parameters: 3 40 3 40 5 false}} \
-core -extension {{stop: outermost_ring}}

compile_pg -strategies s_mesh1

#STANDARD CELL RAIL INSERTION

create_pg_std_cell_conn_pattern std_cell_rail -layers {M1} -rail_width 0.06

set_pg_strategy rail_strat -core \

-pattern {{name: std_cell_rail} {nets: VDD VSS} }

compile_pg -strategies rail_strat

save_block

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Powerplan Screenshot

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 Placement Script

#placement

copy_block -from_block counter.dlib:power_plan.design -to_block placement

current_block placement.design

report_qor -summary
report_design -summary
report_utilization

check_design -checks pre_placement_stage

report_lib saed90nm_max_lth

set_voltage 1.08

set_parasitic_parameters -early_spec maxTLU -late_spec minTLU

# Run 5 stages of placement : .coarse placement .initial_drc-HFS .running initial

optimization .final_place
# . final_optomization
place_opt

#View congestion map

#report_congestion -rerun_global_router

# check legalizaation of all cells [no overlapping cells ....]

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check_legality -verbose

report_utilization

report_qor

save_block

Placement Screenshot

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 Clock Synthesis Script

# CTS

copy_block -from_block counter.dlib:placement.design -to_block CTS1

current_block CTS1.design

report_clock_qor -type structure

derive_clock_cell_references -output cts_leg_set.tcl > /dev/null

set CTS_CELLS [get_lib_cells "*/NBUFFX2 */NBUFFX4 */NBUFFX8 "]

#NDR

set CTS_NDR_MIN_ROUTING_LAYER "M4"

set CTS_NDR_MAX_ROUTING_LAYER "M5"
set CTS_LEAF_NDR_MIN_ROUTING_LAYER "M1"
set CTS_LEAF_NDR_MAX_ROUTING_LAYER "M5"
set CTS_NDR_RULE_NAME "cts_w2_s2_vlg"
#set CTS_LEAF_NDR_RULE_NAME "cts_w1_s2"

create_routing_rule $CTS_NDR_RULE_NAME\
-default_reference_rule \
-taper_distance 0.4 \
-driver_taper_distance 0.4 \
-widths {M3 0.16 M4 0.32 M5 0.32} \

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 -spacings {M3 0.16 M4 0.32 M5 0.32}

set_clock_routing_rules -rules $CTS_NDR_RULE_NAME \

-min_routing_layer $CTS_NDR_MIN_ROUTING_LAYER \
-max_routing_layer $CTS_NDR_MAX_ROUTING_LAYER

report_routing_rules -verbose

report_clock_routing_rules

#Sink pins will not follows NDRs

set_clock_routing_rules -net_type sink -default_rule -min_routing_layer M1
-max_routing_layer M2

#DRC
report_ports -verbose [get_ports *clk*]
set_driving_cell -scenarios [all_scenarios] -lib_cell NBUFFX4 [get_ports *clk*]

set_app_options -name time.remove_clock_reconvergence_pessimism -value true

report_clock_settings

#
set_clock_tree_options -target_skew 0.5 -clock [get_clocks *]
set_clock_tree_options -target_latency 0.1 -clock [get_clocks *]

clock_opt

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Clock Synthesis Screenshot

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Cell Density

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 Routing Script

# 1.routing

copy_block -from_block counter.dlib:CS1.design -to_block routing

current_block routing.design

# check for any issues that might cause problems during routing
report_qor -summary
check_design -checks pre_route_stage

#antenna rules (change the directory according to your project)

source
/home/vlsi/Synopsys/I2C/standardCell/SAED90nm_EDK_10072017/SA
ED90_EDK/SAED_EDK90nm/Digital_Standard_cell_Library/process/as
tro/tech/saed90nm_1p9m_antenna.tcl

## Routing (Performs all routing stages in one step the command

runs global routing, track assignment, and detail routing )

route_auto

# Routing Optimization
route_opt

#Final Check
check_routes

#Routing is Finished

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# 2.Filler Cells Insertion

set FillerCells " SHFILL128 SHFILL64 SHFILL3 SHFILL2 SHFILL1 "

create_stdcell_fillers -lib_cells $FillerCells
connect_pg_net -automatic

remove_stdcell_fillers_with_violation

check_legality

# 3.Checks & Output

# First Create new directory called output in pnr folder

set DESIGN_NAME i2c_top

# Netlist after physical synthesis

write_verilog ./output/${DESIGN_NAME}_for_pt_v.v

#SDC_OUT
write_sdc -output ./output/${DESIGN_NAME}.out.sdc

# SPEF_OUT
write_parasitics -format SPEF -output
./output/${DESIGN_NAME}.out.spef

######DEF_OUT
write_def ./output/${DESIGN_NAME}.out.def

##########GDS_OUT

set GDS_MAP_FILE
/home/vlsi/Synopsys/I2C/standardCell/SAED90nm_EDK_10072017/SA
ED90_EDK/SAED_EDK90nm/Technology_Kit/milkyway/saed90nm.gds
out.map

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set STD_CELL_GDS
/home/vlsi/Synopsys/I2C/standardCell/SAED90nm_EDK_10072017/SA
ED90_EDK/SAED_EDK90nm/Digital_Standard_cell_Library/layout/gds/
saed90nm.gds

write_gds \
-view design \
-lib_cell_view frame \
-output_pin all \
-fill include \
-exclude_empty_block \
-long_names \
-layer_map "$GDS_MAP_FILE" \
-keep_data_type \
-merge_files "$STD_CELL_GDS" \
./output/${DESIGN_NAME}.gds

save_block

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Routing Screenshots

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DRC Checks

Legality checks

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28 | Page
 STA Script

set Design_name i2c_top

set search_path
/home/vlsi/Synopsys/I2C/standardCell/SAED90nm_EDK_10072017/
SAED90_EDK/SAED_EDK90nm

set target_library
$search_path/Digital_Standard_cell_Library/synopsys/models/saed
90nm_max_lth.db

set link_path "* $target_library"

set Netlist_files
/home/vlsi/Synopsys/I2C/pnr/output/i2c_top_for_pt_v.v

set SPEF_files
/home/vlsi/Synopsys/I2C/pnr/output/i2c_top.out.spef.spef_scenario

set constrains_file
/home/vlsi/Synopsys/I2C/pnr/output/i2c_top.out.sdc

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source ./PrimeTimeSetup.tcl

# Netlist Reading from ICC2

read_verilog $Netlist_files
link_design

# Reading parasitics & constrains

read_parasitics $SPEF_files
read_sdc $constrains_file
update_timing

# Checks

report_timing
report_analysis_coverage
report_global_timing
report_clocks

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STA Screenshots

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32 | Page
Whole Design Screenshot

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