DATA FLOW MODELING
Continuous Assignments
• Keyword: assign
• Examples:
• assign out = i1 & i2;
• assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;
• assign C[15:0] = A[15:0] ^ B[15:0];
• LHS can be a scalar or vector net.
• LHS cannot be a register
• Continuous assignments are always active
• operands on the right-hand side can be registers or nets or
function calls
• Delay values can be specified for assignments in terms of
time units.
Implicit Continuous Assignment & Net
Declaration
• //Regular continuous assignment
• wire out;
• assign out = in1 & in2;
• //Same effect is achieved by an implicit continuous
assignment
• wire out = in1 & in2;
• // Continuous assign. out is a net.
• wire i1, i2;
• assign out = i1 & i2;
• //Note that out was not declared as a wire
• //but an implicit wire declaration for out
• //is done by the simulator
Delays
Regular Assignment Delay
• assign #10 out = in1 & in2; // Delay in a continuous
assign
Delays
Implicit Continuous Assignment Delay
• //implicit continuous assignment delay
• wire in1, in2;
• wire #10 out = in1 & in2;
Net Declaration Delay
• //Net Delays
• wire in1, in2;
• wire # 10 out;
• assign out = in1 & in2;
4-to-1 Multiplexer
• module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
• output out;
• input i0, i1, i2, i3, s1, s0;
• //Logic equation for out
• assign out = (~s1 & ~s0 & i0)|
• (~s1 & s0 & i1) |
• (s1 & ~s0 & i2) |
• (s1 & s0 & i3) ;
• endmodule
• // Use nested conditional operator
• assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
Expressions, Operators, and Operands
• a^b
• addr1[20:17] + addr2[20:17]
• !a[0] // ! is an operator on operand a[0]
• B >> 1
Operator Types
Arithmetic Operators
Binary operators
• A + B // Add
• B - A // Subtract
• A * B // Multiply
• D / E // Divide
• E ** F //E to the power F
• 13 % 3 // modulus
Unary operators
• -4 // Negative 4
• +5 // Positive 5
• It is advisable to use negative numbers only of the type
integer or real in expressions
Operator Types contd..
Logical Operators
• A && B //logical-and
• A || B // logical-or
• !A // logical-not
• Ex: A=5, B=0
• A && B = 0
• A || B = 1
• !A = 0
• If ( (a == 2) && (b == 3) )
Operator Types contd..
Relational Operators
• Y < Z // lesser than
• A > B //greater than
• A <= B // less-than-or-equal-to
• Y >= X // greater-than-or-equal-to
• expression returns a logical value of 1 if the expression is
true and 0 if the expression is false.
• Ex: a=1, b=2
• Y = a > b ; Y=0
Operator Types contd..
Equality Operators
•a == b // logical equality
•a != b // logical inequality
•a === b // case equality
•a !== b // case inequality
•Ex: a = 001xz; b=00110; c=001xz
•a==b // result is x
•a === b // result is 0
•a===c // results in 1
Operator Types contd..
Bitwise Operators
• ~X // Negation.
• X & Y // Bitwise and.
• X | Y // Bitwise or.
• X ^ Y // Bitwise xor.
• X ^~ Y // Bitwise xnor
• Ex: a=0011; b=1101; c=0xx1
• ~a // result = 1100 ~c // result = 1xx0
• a & b // result = 0001 c & b // result = 0x01
• a | b // result = 1111 c | b // result = 11x1
• a ^ b // result = 1110 c ^ b // result = 1xx0
• a ^~ b // result = 0001 c ^~ b // result = 0xx1
Operator Types contd..
Reduction Operators
Unary operators
• &X //reduction and
• ~&X //reduction nand
• |X //reduction or
• ~|X //reduction nor
• ^X //reduction xor
• ~^X //reduction xnor
• Reduction operators perform a bitwise operation on a
single vector operand and yield a 1-bit result
• Bit by bit from right to left
• Ex: a = 1011;
• &a //res = 0 |a // res = 1 ^a //res=1 : odd parity
Operator Types contd..
Shift Operators
•X >> 1; //right shift
•X << 1; //left shift
•X >>> 1; //arithmetic right shift
•X <<< 1; //arithmetic left shift
• When the bits are shifted, the vacant bit positions are
filled with zeros.
• Shift operations do not wrap around
• Ex: X = 4'b1100 = 4’d12 Y=-10 = 1111…..11110110
• X >> 1 // res = 0110 = 6 X << 1 // res = 1000 = 8
• Y >>> 1 //res = 111…1011= -5 (2’s compliment)
• Y <<< 1 // res =111…..101100 = -20 (2’s compliment)
Operator Types contd..
Concatenation Operator
•{, } // concatenation operator
•The operands must be sized.
•Unsized operands are not allowed.
•Ex: A = 1'b1, B = 2'b00, C = 2'b10, D = 3'b110
• Y = {B , C} // res = 4'b0010
• Y = {A , B , C , D , 3'b001} // res = 11'b10010110001
• Y = {A , B[0], C[1]} // res = 3'b101
Operator Types contd..
Replication Operator
•{ } //
• Repetitive concatenation of the same number can be
expressed by using a replication constant.
• A replication constant specifies how many times to
replicate the number inside the brackets
• Ex: = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110;
• Y = { 4{A} } // Res= 4'b1111
• Y = { 4{A} , 2{B} } // Res= 8'b11110000
• Y = { 4{A} , 2{B} , C } // Res= 8'b1111000010
Operator Types contd..
Conditional Operator
•(?:) ; // conditional operator : three operands
•condition_expr ? true_expr : false_expr ;
• The action of a conditional operator is similar to a
multiplexer or an if-else expression.
• Ex: model functionality of a 2-to-1 mux
• assign out = S0 ? in1 : in0;
Operator Precedence
4-bit Full Adder
• module fulladd4(sum, c_out, a, b, c_in);
• output [3:0] sum;
• output c_out;
• input [3:0] a, b;
• input c_in;
• // Specify the function of a full adder
• assign {c_out, sum} = a + b + c_in;
• endmodule
4-bit Full Adder
• module fulladd4(sum, c_out, a, b, c_in);
• output [3:0] sum;
• output c_out;
• input [3:0] a, b;
• input c_in;
• wire c0,c1,c2;
• assign sum[0] = a[0]^b[0]^c_in;
• assign sum[1] = a[1]^b[1]^c0;
• assign sum[2] = a[2]^b[2]^c1;
• assign sum[3] = a[3]^b[3]^c2;
• assign c0 = (a[0]&b[0])|(b[0]&c_in)|(c_in&a[0]);
• assign c1 = (a[1]&b[1])|(b[1]&c0)|(c0&a[1]);
• assign c2 = (a[2]&b[2])|(b[2]&c1)|(c1&a[2]);
• assign c_out = (a[3]&b[3])|(b[3]&c2)|(c2&a[3]);
• endmodule
4-bit Full Adder with Carry Lookahead
•Inputs: a[3:0], b[3:0], c_in
•Outputs : sum[3:0], c_out;
•Propogate signals:
•p0= a0 b0 , p1= a1 b1,
•p2= a2 b2, p3= a3 b3
•Generate signals:
•g0=a0bo, g1=a1b1, g2=a2b2, g3=a3b3
•Carry bits:
•c1= g0+po.c_in , c2=g1+p1g0+p1.p0.c_in
•c3=g2+p2g1+p2.p1.g0+p2. p1.p0.c_in
•C4=g3+p3g2+p3.p2.g1+p3. p2.p1.g0+p3.p2. p1.p0.c_in
•Sum and c_out:
•s0= p0 c_in , s1= p1 c1, c_out=c4
•s2= p2 c2, s3= p3 c3
4-bit Full Adder with Carry Lookahead
contd..
• module fulladd4(sum, c_out, a, b, c_in);
• output [3:0] sum;
• output c_out;
• input [3:0] a,b;
• input c_in;
• wire p0,g0, p1,g1, p2,g2, p3,g3;
• wire c4, c3, c2, c1;
• // compute the p for each stage
• assign p0 = a[0] ^ b[0],
• p1 = a[1] ^ b[1],
• p2 = a[2] ^ b[2],
• p3 = a[3] ^ b[3];
• contd…
4-bit Full Adder with Carry Lookahead
contd..
• // compute the g for each stage
• assign g0 = a[0] & b[0],
• g1 = a[1] & b[1],
• g2 = a[2] & b[2],
• g3 = a[3] & b[3];
• // carry lookahead computation
• assign c1 = g0 | (p0 & c_in),
• c2 = g1 | (p1 & g0) | (p1 & p0 & c_in),
• c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 &
p0 & c_in),
• c4 = g3 | (p3 & g2) | (p3 & p2 & g1) |
(p3 & p2 & p1 & g0)|(p3 & p2 & p1 & p0 & c_in);
contd…
4-bit Full Adder with Carry Lookahead
contd..
• // Compute Sum
• assign sum[0] = p0 ^ c_in,
• sum[1] = p1 ^ c1,
• sum[2] = p2 ^ c2,
• sum[3] = p3 ^ c3;
• // Assign carry output
• assign c_out = c4;
• endmodule
2x2 Unsigned Combinational ArrayMultiplier
• Inputs: a[1:0], b[1:0]
• Output: P[3:0]
2x2 Unsigned Combinational ArrayMultiplier
2x2 Unsigned Combinational ArrayMultiplier
module mult_arry (a, b, P);
input [1:0] a, b;
output [3:0] P;
assign P[0] = a[0] & b[0];
assign P[1] = (a[0] & b[1]) ^ (a[1] & b[0]);
assign P[2] = (a[1] & b[1]) ^ ((a[0] & b[1]) & (a[1] & b[0]));
assign P[3] = (a[1] & b[1]) & ((a[0] & b[1])& (a[1] & b[0]));
endmodule
2x2 Magnitude Comparator
•Inputs: X[1:0], Y[1:0]
•Outputs: X>Y (xgty), X=Y (xeqy), X<Y (xlty)
X[1] X[0] Y[1] Y[0] X>Y X<Y X=Y
0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 0 1 0 0 1
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 0 1 1 0 1 0
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 0 1
2x2 Magnitude Comparator
module compr_2 (x, y, xgty, xlty, xeqy);
input [1:0] x, y;
output xgty, xlty, xeqy;
assign xgty = (x[1] & ~ y[1]) | (x[0] & ~ y[1] & ~ y[0]) |
(x[0] & x[1] & ~ y[0]);
assign xlty = (y[1] & ~ x[1] ) | (~ x[0] & y[0] & y[1]) |
(~ x[0] & ~ x[1] & y[0]);
assign xeqy = ~ (xgty | xlty);
endmodule
D-Latch
E D Q Q+
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
D-Latch DataFlow Modelling
module D_latch (D, E, Q, Qbar);
input D, E;
output Q, Qbar;
assign #2 Qbar = ~((E & D) | (~E & Q));
assign #1 Q = ~ Qbar;
endmodule
D-Latch GateLevel Modelling
module D_latch (D, E, Q, Qbar);
input D, E;
output Q, Qbar;
Wire Ebar, s1, s2;
not (Ebar, E);
and (s1, D, E);
and (s2, Q, Ebar);
nor (Qbar, s1, s2);
not (Q, Qbar);
endmodule
Edge triggered D Flip-Flop
Positive Edge triggering
Positive Edge triggered D Flip-Flop
module D_ff (D, Clk, Q, Qbar);
input D, Clk;
output Q, Qbar;
wire a, abar;
//Instantiate D_latch two times
D_latch D1(D, ~Clk, a, abar);
D_latch D2(a, Clk, Q, Qbar);
endmodule
Edge-Triggered D-flip-flop Working
Edge triggered D Flip-Flop Working
The operation of the circuit is as follows. When E = 0, the
outputs of gates 2 and 3 are high (0 NAND x
= 1). Thus n2 = n3 = 1, which maintains the output latch,
comprising gates 5 and 6, in its current state. At the same
time n4 = D' since one input to gate 4 is n3 which is a 1 (1 NAND
x = x'). Similarly, n1 = D. When E changes to 1, n2
will be equal to n1' = D', while n3 will be equal to D. So if D = 0,
then n3 will be 0, thus asserting R' and resetting the
output latch Q to 0. On the other hand, if D = 1, then n2 will be
0, thus asserting S' and setting the output latch Q to 1.
Once E = 1, changing D will not change n2 or n3, so Q will
remain stable during the remaining time that E is asserted.
Negative Edge-Triggered D-flipflop
Edge-Triggered D-flipflop Dataflow
module edge_dff(q, qbar, d, clk, clear);
output q,qbar;
input d, clk, clear;
wire s, sbar, r, rbar,cbar;
assign cbar = ~clear;
//An edge-sensitive flip-flop is implemented by using 3 SR latches.
assign sbar = ~(rbar & s),
s = ~(sbar & cbar & ~clk),
r = ~(rbar & ~clk & s),
rbar = ~(r & cbar & d);
// Output latch
assign q = ~(s & qbar),
qbar = ~(q & r & cbar);
endmodule
Edge-Triggered D-flipflop Gatelevel
module edge_dff(q, qbar, d, clk, clear);
output q,qbar;
input d, clk, clear;
wire s, sbar, r, rbar,cbar, clkbar;
//Instantiate 2 not gates and 6 nor gates
not (cbar, clear);
not (clkbar, clk);
nand ( sbar, s, rbar);
nand ( s, sbar, cbar, clkbar);
nand ( r, s, clkbar, rbar);
nand ( rbar, r, cbar, d);
nand ( q, s, qbar);
nand ( qbar, cbar, r, q);
endmodule
Question?
• Find the value of y, if
• y = ((A+B) && (|C)) + (A<<<2);
• A=1101, B=1010 and C=0111.
• Ans: Y=0101
Question?
Find the value of Y
Y = ((&A) | (B>>2) | (A ^ B)),
if A = 1011 and B = 1111.
• Ans: Y = 0111
Question?
Analyze the following Verilog description code, fill the values of
s1 and s2 into the table; T is time in nanoseconds.
▫ module p1(a,b,s1,s2);
▫ input a,b;
▫ output s1,s2;
▫ assign #10 s1 = a ^ b;
▫ assign #10 s2 = a | s1;
▫ endmodule
T=100 T=150 T=165 T=200 T=250 T=300
a 1 0 0 1 0 1
b 1 1 1 0 0 1
s1 0
s2 0
Question
Answer:
T=100 T=150 T=165 T=200 T=250 T=300
a 1 0 0 1 0 1
b 1 1 1 0 0 1
s1 0 0 1 1 1 0
s2 0 1 0 1 1 0
Question?
• module TEST1(A,B,C,G,Y);
• input A,B,C,G;
• output Y;
• wire S1,S2,S3,S4,S5;
• assign #7 Y=S4 | S5;
• assign #7 S4= A&S2&S1;
• assign #7 S5= B&S3&S1;
• assign #7 S2=~C;
• assign #7 S3 = ~S2;
• assign #7 S1=~G;
• endmodule
Question?
• Initial values A=1, B=0, C=0, and G=0
• A changes from 1 to 0 and B changes from 0 to 1 at
time T0.
• C changes from 0 to 1 at T1 .
• G changes from 0 to 1 at T2.
• given T0 = 100ns : T1 =200ns : T2 = 300ns.
• Y will have changes @ T0+Δ1 ,T1+Δ2,T2+Δ3.
• Find Δ1, Δ2, Δ3 in terms of ns;
• Ans: Δ1 = 14ns
• Δ2 = 28ns
• Δ3=21ns
