LEADING UNIVERSITY, SYLHET
Dept. of Computer Science & Engineering
LAB Report
Spring-2023
Course Code: EEE-4128
Course Title: VLSI I Sessional
Submitted To:
Tanbinul Hoque
Lecturer
Department of EEE
Leading University, Sylhet
Submitted By:
Name : Koushik Roy
ID : 2012020173
Department of CSE, LU
Batch 53rd , D Section
23.05.2023
Title : NMOS Inverter with Resistive Load.
Theory : The N-MOS inverter with a resistive load is a common configuration in
digital integrated circuits. It consists of an N-MOS transistor, a resistive load, and a
voltage source. The input signal is applied to the transistor's gate terminal, and the
output is taken from the connection between the transistor and the load resistor.
When the input signal is LOW, the N-MOS transistor is OFF, and the output
voltage is pulled up to the HIGH supply voltage (VDD) through the load resistor,
resulting in a logic HIGH output. Conversely, when the input signal is HIGH
(VDD), the transistor is turned ON, pulling down the output voltage to near ground
potential, resulting in a logic LOW output.
Methodology :
Circuit Setup:
1. Launch Proteus 8 and open a new schematic.
2. Place an N-MOS transistor,load resistor,ground, DC voltmeter, DC power
source and logicstate on the workspace.
3. Connect the drain to VDD, the source to ground, and the gate to the logic
state and connect the resistive load between the drain and the output node.
4. Connect a DC voltmeter between output and ground.
5. Specify values for VDD and load resistor.
Figure :
Fig : NMOS Inverter with Resistive Load
Simulation :
When we provide logic level LOW in the input, we see a logic level HIGH in the
output through the DC Voltmeter.
Fig : Logic level 1 on input 0
When we provide logic level HIGH in the input, we see a logic level LOW in the
output through the DC Voltmeter.
Fig : Logic level 0 on input 1
Conclusion:
In this experiment, we simulated an N-MOS inverter with a resistive load using
Proteus Simulation software. By analyzing the output we gained insights into the
circuit's performance. Proteus proved to be a useful tool for circuit simulation,
enabling us to study the behavior of digital circuits with resistive loads.
Title : NMOS inverter with enhancement type load.
Theory : The N-MOS inverter with an enhancement-type load is a common
configuration in digital integrated circuits. It consists of an N-MOS transistor, an
enhancement-type load transistor, and a voltage source. The input signal is applied
to the gate of the N-MOS transistor, while the enhancement-type load transistor is
connected between the N-MOS transistor's drain and the voltage source.
When the input signal is low , the N-MOS transistor is off, and the enhancement-
type load transistor is also off due to the absence of gate-source voltage. As a
result, the output voltage is pulled up to the high supply voltage (VDD) through a
weak pull-up resistor, resulting in a logic high output.
Conversely, when the input signal is high (VDD), the N-MOS transistor turns on,
allowing current to flow through it. This turns on the enhancement-type load
transistor as well, providing a low resistance path to ground. As a result, the output
voltage is pulled down to near ground potential, resulting in a logic low output.
Methodology :
Circuit Setup:
1. Launch Proteus 8 and open a new schematic.
2. Place two N-MOS transistor, a ground, a DC voltmeter, DC power source
and a logicstate on the workspace.
3. Connect the drain of the N-MOS transistor to VDD, the source to ground,
and the gate to the input signal.
4. Connect the drain of the enhancement-type load transistor to the output node
and the source to VDD.Connect a DC voltmeter between output and ground.
5. Specify values for VDD.
Figure :
Fig : NMOS Inverter with Enhancement type
Simulation :
When we provide logic level LOW in the input, we see a logic level HIGH in the
output through the DC Voltmeter.
Fig : Logic level 0 on input 1
When we provide logic level HIGH in the input, we see a logic level LOW in the
output through the DC Voltmeter.
Fig : Logic level 1 on input 0
Conclusion:
In this experiment, we simulated an N-MOS inverter with an enhancement-type
load using Proteus . By analyzing the output we gained valuable insights into the
circuit's performance. The use of an enhancement-type load transistor allows for
improved noise margin and reduced power consumption compared to a resistive
load. Proteus proved to be a reliable tool for circuit simulation, enabling us to
study the behavior of digital circuits.
Title : CMOS inverter.
Theory : The CMOS inverter is a fundamental building block in digital integrated
circuits. It consists of both a P-MOS and an N-MOS transistor connected in series
between a voltage source and ground. The input signal is applied to the gate of
both transistors, and the output is taken from the connection between them.
When the input signal is low , the P-MOS transistor is in the on state while the N-
MOS transistor is off . This allows the voltage at the output node to be pulled up to
the high supply voltage, resulting in a logic high output.
Conversely, when the input signal is high , the P-MOS transistor is off and the N-
MOS transistor is on. This pulls the output voltage down to near ground potential,
resulting in a logic low output.
Methodology :
Circuit Setup:
1. Launch Proteus 8 and open a new schematic.
2. Place one N-MOS and one PMOS transistor, a ground,a capaciter, DC
power source, a DC voltmeter and a logicstate on the workspace.
3. Connect the P-MOS transistor's source to VDD and its drain to the output
node and Connect the N-MOS transistor's source to the output node and its
drain to ground.
4. Connect the input signal to the gate of both transistors.
5. Connect a capacitor and a DC voltmeter between output and ground.
6. Specify values for VDD and capacitor.
Figure :
Fig : C-MOS Inverter
Simulation :
When we provide logic level LOW in the input, we see a logic level HIGH in the output through
the DC Voltmeter.
Fig : Logic level 0 on input 1
When we provide logic level HIGH in the input, we see a logic level LOW in the output through
the DC Voltmeter.
Fig : Logic level 1 on input 0
Conclusion:
In this experiment, we simulated the behavior of a CMOS inverter using Proteus.
By analyzing the output we gained insights into the CMOS circuit's performance.
Proteus 8 proved to be an effective tool for circuit simulation, enabling us to study
the behavior of CMOS inverters.
