ADC, Voltage Comparator and Voltage
Reference Modules
ADC Module
Description
The PIC16F877 has a 10-bit ADC with up to 8 input channels.
The pins that are used as ADC input channels are RA0/AN0; RA1/AN1; RA2/AN2/VREF-/CVREF;
RA3/AN3/VREF+; RA5/AN4/SS/C2OUT; RE0/RD/AN5; RE1/WR/AN6 and RE2/CS/AN7. The input
channel currently being converted is selectable in software.
The low voltage reference is provided by the voltage on pin VSS or RA2/AN2/VREF-/CVREF. The high
voltage reference is provided by the voltage on pin VDD or RA3/AN3/VREF+. The combination of
pins that are used as voltage references is selectable in software.
The ADC clock is derived from the main clock or from an internal RC oscillator and is selectable in
software.
Figure 8.1 shows the block diagram of the ADC module.
Figure 8.1
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Associated SFRs
ADRESL (address 9Eh) and ADRESH (address 1Eh)
These two registers are used to store the result of A/D conversion. ADRESL holds the lower bits whilst
ADRESH holds the higher bits. The ADC result can be left or right justified. When left justified, ADRESH holds
the upper 8 bits and ADRESL holds the lowest 2 bits. When right justified, ADRESH holds the highest 8 bits
and ADRESL holds the lowest 8 bits. The unused bits read as ‘0’s. Figure 8.2 illustrates A/D result justification
formats.
Figure 8.2
ADCON0 (address 1Fh)
It is used to configure and control the operation of the ADC module.
ADCS1:ADCS0 – A/D conversion clock select bits. Together with the bit ADCS2 located in ADCON1
they select the conversion frequency as follows:
o 000 – FOSC/2
o 001 – FOSC /8
o 010 – FOSC /32
o 011 – FRC (clock derived from the internal A/D RC oscillator)
o 100 – FOSC/4
o 101 – FOSC/16
o 110 – FOSC/64
o 111 – FRC (clock derived from the internal A/D RC oscillator)
The maximum conversion frequency is 0.625MHz. Clock selections must be chosen to ensure the
maximum frequency is not exceeded.
CHS2:CHS0 – Analog channel select bits
o 000 – Channel 0 (AN0)
o 001 – Channel 1 (AN1)
o 010 – Channel 2 (AN2)
o 011 – Channel 3 (AN3)
o 100 – Channel 4 (AN4)
o 101 – Channel 5 (AN5)
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o 110 – Channel 6 (AN6)
o 111 – Channel 7 (AN7)
GO/DONE – A/D conversion start/status bit. Setting the bit starts A/D conversion. The bit is
automatically cleared in hardware when the A/D conversion is complete. During the conversion
process, the bit indicates whether an A/D conversion is progress (when set) or has completed (when
cleared). Clearing the bit during a conversion process aborts the conversion process.
Bit 1 is not implemented.
ADON – A/D on bit
o 1 – puts on the A/D converter module
o 0 – puts off the A/D converter module
ADCON1 (address 9Fh)
It is used to configure A/D pins and to select the format of the A/D result.
ADFM – A/D result format select bit
o 1 – selects right justified format of A/D result.
o 0 – selects left justified format of A/D result.
ADCS2 – A/D conversion clock select bit. It is used together with ADCS1 and ADCS0 in ADCON0.
Bits 5-4 are not implemented.
PCFG3:PCFG0 – A/D port configuration control bits. The bits are used to assign functions to A/D pins
as shown in the table.
TRISA (address 85h) and TRISE (address 89h)
The register is used to configure directions for A/D pins. A pin that is assigned as an analog input or
reference input must be set as an input pin.
Interrupt Control Registers
PIE1 contains the interrupt enable bit, ADIE for the ADC module.
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PIR1 contains the interrupt flag, ADIF for the ADC module.
INTCON contains the global interrupt enable bit GIE and the peripheral interrupt enable bit PEIE.
Running an ADC module
1. Assign and configure pins as desired using ADCON1, TRISA and TRISE – that is assign pins to be used
as analog inputs, voltage references pins and digital I/O pins.
2. Select the A/D input channel, A/D conversion clock and turn on the A/D module using ADCON0.
3. If desired, enable the A/D interrupt.
4. Wait for a period equal to the acquisition time. Nominally, acquisition time is 20µs. Acquisition time
is the time required by the module to fully acquire the analog voltage.
5. Start the conversion by setting the GO/DONE bit.
6. Wait for A/D conversion to complete by either polling the GO/DONE bit or waiting for the A/D
interrupt.
7. Read A/D result from the register pair (ADRESH:ADRESL).
8. Clear bit ADIF if required.
Comparator Module
Description
The PIC 16F877 has two analog voltage comparators. Each module compares analog input voltages on two
input pins VIN+ and VIN-. When the analog input at VIN+ is less than the analog input at VIN-, the output of the
comparator is set to logic level ‘0’. When the analog input at VIN+ is greater than the analog input at VIN-, the
output of the comparator is set to logic level ‘1’. The comparator module may also be configured in software
to give the result as an inverted version. Figure 8.3 illustrates the operation of the comparator. Shaded
portions on the output represent regions in which output state is not certain.
Figure 8.3
The inputs to the comparators are provided through the pins RA0/AN0, RA1/AN1, RA2/AN2/VREF-/CVREF
and RA3/AN3/VREF+. The pins that are connected to VIN+ and VIN of each comparator are selectable in
software. The result is stored as a bit state held in an SFR. The result may also be sent to an output pin. For
comparator 1, the output pin is on pin RA4/TOCKI/C1OUT. For comparator 2, the output pin is on pin
RA5/AN4/SS/C2OUT. The analog comparator is capable of raising an interrupt when there is a change of the
output state.
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Figure 8.4 Comparator block diagram
Associated SFRs
CMCON (address 9h)
It controls the operation of the analog comparator module.
C2OUT – Comparator 2 output bit
o It stores the result of comparison on comparator2
C1OUT: Comparator 1 output bit
o It stores the result of comparison on comparator 1
C2INV: Comparator 2 output inversion bit
o 1 – inverts C2OUT
o 0 – C2OUT is in true state.
C1INV: Comparator 1 output inversion bit
o 1 – inverts C1OUT
o 0 – C1OUT is in true state
CIS: Comparator input switch bit – valid only when CM2:CM0 = 110
o 1 – C1 VIN- connects to RA3/AN3, C2 VIN- connects to RA2/AN2
o 0 – C1 VIN- connects to RA0/AN0, C2 VIN- connects to RA1/AN1
CM2:CM0: Comparator Mode bits. Figure 8.4 shows the comparator modes as functions of the
settings on bits CM2:CM0.
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Figure 8.4
ADCON1 (address 9Fh)
The register is used to assign pins as analog or digital pins. A pin that is used as an input in the analog
comparator must be set as an analog pin. A pin that is used as an output in the analog comparator must be
set as a digital output pin.
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TRISA (address 85h)
The register is used to configure directions for the comparator pins. A pin that is assigned as a comparator
input must be set as an input pin. A pin that is assigned as a comparator output pin must be set as an output
pin.
Interrupt Control Registers
PIE2 contains the interrupt enable bit, CMIE for the comparator module.
PIR2 contains the interrupt flag, CMIF for the comparator module.
INTCON contains the global interrupt enable bit GIE and the peripheral interrupt enable bit PEIE.
Running the Comparator Module
1. Assign and configure pin uses as desired using ADCON1 and TRISA.
2. Configure comparator mode, comparator switch and inversion bit using CMCON.
3. If desired, enable the comparator interrupt.
4. Result is reflected in the output bit or on the output pin.
5. Interrupt may be used to respond to changes in the output state.
Reference Voltage Generator
The PIC16F877 has one reference voltage generator. The voltage generator is 16-tap resistor ladder that
gives as output 16 possible voltage levels. The output voltage level is selectable in software using a 4-bit
value. Figure 8.6 shows the structure of the reference voltage generator.
Figure 8.6
The output of the generator may be used for any of the following:
As an internal reference for the comparator module when it is operating in mode given by CM2:CM0
= 110 in CMCON (4 inputs multiplexed to 2 comparators).
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As a reference voltage output on pin RA2/AN2/VREF-/CVREF.
As a simple 4-bit DAC if a high impedance load is connected.
Associated SFRs
CVRCON (address 9Dh)
It controls the operation of the reference voltage generator.
CVREN – comparator voltage reference enable bit
o 1 – puts on the CVREF circuit
o 0 – puts off the CVREF circuit
CVROE: Comparator VREF output enable bit
o 1 – outputs CVREF voltage level on RA2/AN2/VREF-/CVREF pin
o 0 – CVREF voltage level is not outputted on the RA2/AN2/VREF-/CVREF pin
CVRR: Comparator VREF range selection bit
o 1 – selects output in the range 0 - 0.75 of CVRSRC, with a step size of CVRSRC/24
o 0 – selects an output in the range 0.25 - 0.75 of CVRSRC with a step size of CVRSRC/32
o CVRSRSC is the generator reference voltage and is directly connected and equal to VDD.
Bit 4 is not implemented.
CVR3:CVR0: Comparator VREF value selection bits. Bits give values of <VR3:VR0> in the range 0 - 15.
(𝑉𝑅<3:0>
o When CVRR = 1, 𝐶𝑉𝑅𝐸𝐹 = × 𝐶𝑉𝑅𝑆𝑅𝐶
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1 (𝑉𝑅<3:0>
o When CVRR = 0, 𝐶𝑉𝑅𝐸𝐹 = × 𝐶𝑉𝑅𝑆𝑅𝑆𝑐 + × 𝐶𝑉𝑅𝑆𝑅𝐶
4 32
o The formulae derive directly from the ladder network in figure 8.6.
Running the Reference Voltage Generator
1. Assign and configure pin uses as desired.
2. Configure the required operation mode and the required reference voltage value using the CVRCON
register.
Tutorial Exercises
1. A PIC16F877 is required to have 3 ADC input channels. The reference voltages are required to be the
supply voltage lines. The result is required to be left justified.
a) Develop a C program to configure the ADC module as required.
b) Develop a C routine to run the ADC so that it converts the signal on one of the channels. The
results are to be send to be written to R2 and R3.
2. Write a C program to run an analog comparator.
3. Write a C program to run a reference voltage generator.
4. Develop C program routines to:
a) Configure the ADC module as required.
b) Run the ADC so that it converts the signal on one of the channels. The results are to be written
to R2 and R3.
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