EAST WEST UNIVERSITY
Department of Electrical & Electronic Engineering
EEE306: Fundamentals of Embedded Systems
Semester: Spring 2024
Section: 1
Experiment No. 4
Introduction to Xilinx ISE for FPGA programming
Submitted by,
Name: MD Ahsanul Habib
ID: 2021-3-80-013
Submitted to,
Course instructor: Dr. Muhammed Mazharul Islam
Assistant Professor, EEE
Date of submission: 21/03/24
Objective:
The objective of this lab is to learn how to program and FPGA using Xilinx ISE.
Ans To. The Qun. No:01
Verilog module for simulating a 3 input OR gate
CODE:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:34:53 03/20/2024
// Design Name:
// Module Name: not_4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module not_4(
input a,
input b,
input c,
output y
);
assign y = a | b | c ;
endmodule
Figure1: RTL Schematic
Figure2: Technology Schematic
Figure3: Truth Table
Test bench CODE:
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:13:59 03/20/2024
// Design Name: lab_4
// Module Name: /home/habib/EEE_Lab_4/lab_4_tb.v
// Project Name: EEE_Lab_4
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: lab_4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module lab_4_tb;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
lab_4 uut (
.a(a),
.b(b),
.c(c),
.y(y)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#100;
a = 0;
b = 0;
c = 1;
#100;
a = 0;
b = 1;
c = 0;
#100;
a = 0;
b = 1;
c = 1;
#100;
a = 1;
b = 0;
c = 0;
#100;
a = 1;
b = 0;
c = 1;
#100;
a = 1;
b = 1;
c = 0;
#100;
a = 1;
b = 1;
c = 1;
// Add stimulus here
end
endmodule
Figure4: Timing diagram
Ans To. The Qun. No:02
Verilog module for simulating a NOT gate
CODE:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:34:53 03/20/2024
// Design Name:
// Module Name: not_4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module not_4(
input x,
output y
);
assign y = ~x;
endmodule
Figure1: RTL Schematic
Figure2: Technology Schematic
Figure3: Truth Table
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:41:26 03/20/2024
// Design Name: not_4
// Module Name: /home/habib/NOT_4/NOT_4_tb.v
// Project Name: NOT_4
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: not_4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module NOT_4_tb;
// Inputs
reg x;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
not_4 uut (
.x(x),
.y(y)
);
initial begin
// Initialize Inputs
x = 0;
// Wait 100 ns for global reset to finish
#100;
x=1;
#100;
x=0;
// Add stimulus here
end
endmodule
Figure4: Timing diagram
Discussion:
we can see that, Verilog module for simulating a NOT and OR gate view RTL
Schematic and view technology schematic seen truth table simulating test bench
code for timing diagram for verify the truth table. Learn how to program and
FPGA using Xilinx ISE.
