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Package Diagrams[edit]

Approximate dimensions of the "Summit Ridge" (≤ 8C, Zen, 14 nm, Feb. 2017) and "Pinnacle Ridge" (≤
8C, Zen+, 12 nm, April 2018) package. All dimensions in millimeters.
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Approximate dimensions of the "Raven Ridge" desktop package (≤ 4C/11CU, Zen, 14 nm, Oct. 2017).
Mobile and embedded versions are available in a FP5 package. All dimensions in millimeters.

Approximate dimensions of the "Matisse" package (≤ 16C, Zen 2, 7/14 nm, July 2019). The left CCD is
unpopulated in ≤ 8C models. All dimensions in millimeters.

Socket Diagrams
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No data available. The diagram shows the dimensions of Foxconn Interconnect Technology Part No.
PZ1331A-51ZZ*-1H. All dimensions in millimeters.

Pin Description

Signal Description

MA/MB_ACT_L DRAM Channel A/B Activation Command

MA/MB_ADD[13:0] DRAM Column/Row Address

MA/MB_ADD_17 DRAM Column/Row Address 17

MA/MB_ALERT_L DRAM Alert (CRC error and Command/Address parity error)

MA/MB_BANK[1:0] DRAM Bank Address

MA/MB_BG[1:0] DRAM Bank Group

MA/MB_CAS_L_ADD[15] DRAM Column Address Strobe or Column/Row Address 15

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MA/MB_CHECK[7:0] DRAM ECC Check Bits

MA/MB_DATA[63:0] DRAM Data Bus

MA/MB_DM[8:0] DRAM Data Mask

MA/MB_DQS_H/L[8:0] DRAM Differential Data Strobe

MA/MB_EVENT_L DRAM Thermal Event Status

MA/MB_PAROUT DRAM Command/Address Parity

MA/MB_RAS_L_ADD[16] DRAM Row Address Strobe or Column/Row Address 16

MA/MB_RESET_L DRAM Reset

MA/MB_WE_L_ADD[14] DRAM Write Enable or Column/Row Address 14

MA/MB_ZVDDIO_MEM_S3

DRAM Interface Drive-Strength Auto-Compensation Resistor to

MA/MB_ZVSS
VSS

MA0/MA1/MB0/MB1_CKE[1:0] DRAM Channel A/B DIMM 0/1 Clock Enable

MA0/MA1/MB0/MB1_CLK_H/L[3:0] DRAM Channel A/B DIMM 0/1 Differential Clock

MA0/MA1/MB0/MB1_CS_L[1:0] DRAM Channel A/B DIMM 0/1 Chip Select

DRAM Channel A/B DIMM 0/1 Enable Pin for On Die

MA0/MA1/MB0/MB1_ODT[1:0]
Termination

P_GFX_RXP/RXN[15:0] PCIe GFX Receive Data Differential Pairs

P_GFX_TXP/TXN[15:0] PCIe GFX Transmit Data Differential Pairs

P_GPP_RXP/RXN[3:0] PCIe GPP Receive Data Differential Pairs

P_GPP_TXP/RXN[3:0] PCIe GPP Transmit Data Differential Pairs

P_HUB_RXP/RXN[3:0] PCIe Hub (chipset) Receive Data Differential Pairs

P_HUB_TXP/TXN[3:0] PCIe Hub Transmit Data Differential Pairs

PCIE_RST_L Reset signal for PCIe devices

P_ZVDDP

P_ZVSS

P0A/P0B_ZVSS PCIe Drive-Strength Auto-Compensation Resistor to VSS

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SATA Receive Data Differential Pairs (alt. func. of P_GPP[2],

SATA_RX(0-1)P/N
P_GPP[3])

SATA_TX(0-1)P/N SATA Transmit Data Differential Pairs

SATA_ACT_L SATA Channel Active (HD LED)

SGPIO0_CLK SGPIO Interface CLK Output; SGPIO supported on Socket AM4?

SGPIO0_DATAIN SGPIO DATA Input

SGPIO0_DATAOUT SGPIO DATA Output

SGPIO0_LOAD SGPIO LOAD Output

SATA_IS(0-1)_L

SATA_ZP(0-1)_L Zero Power SATA ODD

SATA_ZVDDP

SATA_ZVSS

DP0-DP2_TXP/TXN[3:0] DisplayPort 0-2 Main Link Differential Transmitter Lane 0-3

DP0-DP2_AUXP/AUXN DisplayPort 0-2 Auxiliary Channel

DP0-DP2_HPD DisplayPort 0-2 Hot Plug Detect Input

DP_BLON Display Panel Backlight Enable

DP_DIGON Display Panel Power Enable

DP_VARY_BL Display Backlight Brightness Control

DP_STEREOSYNC StereoSync output for shutter glasses

DP_AUX_ZVSS

DP_ZVSS

USB_HSD(0-3)P/N USB Port 0-3 High Speed I/O Differential Pairs

USB_SS_(0-3)RXP/RXN USB Port 0-3 Super Speed Receive Differential Pairs

USB_SS_(0-3)TXP/TXN USB Port 0-3 Super Speed Transmit Differential Pairs

USB_OC(0-3)_L USB Port 0-3 Over Current signal from USB connector

USB_SS_ZVDDP
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USB_SS_ZVSS

USB_ZVSS

USB(0-3)_ZVSS USB Port 0-3 Drive-Strength Auto-Compensation Resistor to VSS

AZ_BITCLK Azalia HD Audio Interface Bit Clock

AZ_RST_L HDA Reset

AZ_SDIN(0-2) HDA Serial Data Input from Codec 0-2

AZ_SDOUT HDA Serial Data Output to Codec

AZ_SYNC HDA Sync Signal to Codec

SPKR PC speaker/beeper PWM output

SPI_CLK SPI Clock

SPI_DO SPI Data Out or Data 0 for multi-I/O SPI/eSPI device

SPI_DI SPI Data In or Data 1

SPI_WP_L SPI Write Protect or Data 2

SPI Hold Signal (asserted low to hold the SPI transaction) or

SPI_HOLD_L
Data 3

SPI_TPM_CS_L SPI Chip Select for TPM

SPI_CS1/CS2_L SPI Chip Select

ESPI_CLK ESPI Clock (alt. func. of SPI_CLK)

ESPI Data[0], Data[1:0], Data[3:0] (alt. func. of

ESPI_DAT(0-3)
SPI_DO/DI/WP_L/HOLD_L)

ESPI_CS_L ESPI Chip Select (SPI_CS2_L)

ESPI_ALERT_L ESPI Alert Input (LDRQ0_L)

ESPI_RESET_L ESPI Reset (KBRST_L)

LAD(0-3) LPC Command/Address/Data

LDRQ0_L Encoded DMA/Bus Master Request 0

LFRAME_L LPC Bus Frame

LPCCLK(0-1) LPC 33 MHz Clock

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LPC_CLKRUN_L LPC CLKRUN Signal

LPC_PD_L LPC Power Down

LPC_PME_L LPC Power Management Event

LPC_RST_L LPC Reset

SERIRQ Serial IRQ for DMA

I2C(2-3)_SCL I2C Port 2-3 Clock

I2C(2-3)_SDA I2C Port 2-3 Data

SCL0 SMBus Port 0 Clock (alt. func. of I2C2)

SDA0 SMBus Port 0 Data

SCL1 SMBus Port 1 Clock (alt. func. of I2C3)

SDA1 SMBus Port 1 Data

AGPIO* Advanced GPIO pin for interrupt, wake, or I/O

EGPIO* Enhanced GPIO for I/O only

GENINT(1-2)_L Generic Interrupt Request

GFX_CLKP/N PCIe GFX 100 MHz Differential Reference Clock

GPP_CLK0(0-3)P/N PCIe GPP 100 MHz Differential Reference Clock

CLK_REQG_L PCIe GFX Clock Request

CLK_REQ(0-3)_L PCIe GPP Clock Request

OSCIN 14 MHz Clock Input

X32K_X1/X2 32768 Hz Clock XTAL for the integrated RTC

X48M_X1/X2 48 MHz Clock XTAL for the integrated clock generator

32768 Hz Real Time Clock output, for a device requiring an RTC

RTCCLK
clock

48 MHz clock output for devices requiring a single-ended OSC

X48M_OSC
input

KBRST_L Keyboard Controller Reset Input (warm reset)

PWR_BTN_L Power Button; Requests sleep state or causes wake event

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Power Good Input; Asserted when all voltages and clock inputs
PWR_GOOD
are within specification

Power OK; Asserted by the processor after all power planes are
PWROK active, the system clock generators are powered up and run
stably

Bidirectional signal that resets the processor when asserted;

RESET_L Normally controlled by an internal state machine but can also
be asserted by a second external source

Resume Reset from motherboard; Asserted on power up,

RSMRST_L
deasserted when S5 power supplies are within specification

S0A3_GPIO S0A3 Indicator

SLP_S3/S5_L S3/S5 Sleep State Power Plane Control Signal

SYS_RESET_L System Reset Input (reset button)

WAKE_L PCIe WAKE_L signal, wake system out of sleep state

BLINK Blink LED S-state Indicator

FANIN0 Fan tachometer input

FANOUT0 Fan PWM output

Programmable pin that can indicate different events, including

ALERT_L
a SB-TSI interrupt

PROCHOT_L Asserted to force the processor into HTC-active state

SIC Sideband Interface (SB-TSI) Clock

SID Sideband Interface Data

THERMTRIP_L Temperature Trip Input/Output

DBREQ_L Debug Request input to JTAG controller

DBRDY

TCK JTAG Clock

TDI JTAG Data Input

TDO JTAG Data Output

TMS JTAG Mode Select

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TRST_L JTAG Reset

TEST* Test Pins

SVC Serial VID Interface Clock

SVD Serial VID Interface Data

SVT Serial VID Interface Telemetry

VDDIO_AUDIO Azalia HD Audio power supply

VDDBT_RTC_G Integrated Real Time Clock battery power supply

VDDCR_CPU Core power supply

VDDCR_CPU_SENSE VDDCR_CPU voltage monitor pin

VDDCR_SOC Supply voltage for the Northbridge

VDDCR_SOC_SENSE VDDCR_SOC voltage monitor pin

VDDCR_SOC_S5 Always on SOC power supply

VDDIO_MEM_S3 1.2 V DRAM supply voltage

VDDIO_MEM_S3_SENSE VDDIO_MEM_S3 voltage monitor pin

VDDP

VDDP_SENSE VDDP voltage monitor pin

VDDP_S5

VDD_18 1.8 V supply voltage

VDD_18_S5 Always on 1.8 V supply voltage

VDD_33 3.3 V supply voltage

VDD_33_S5 Always on 3.3 V supply voltage

VSS Ground

VSS_SENSE_A VSS sense pin for voltage regulator

VSS_SENSE_B VSS sense pin for voltage regulator

CORETYPE[1:0] Processor Core Type Indicator

AM4R1 Processor Family Revision Identifier

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RSVD Reserved