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Lecture 2 2 2021

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0% found this document useful (0 votes)
19 views27 pages

Lecture 2 2 2021

Uploaded by

Saeed Abdullah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ECE 449

Microdevices and Micromachining


Technology

1
MEMS Microfabrication Process
• Successive (selective) material deposition and removal steps
• Photolithography a central element in the fabrication process
– Photostep defines the features to be etched or deposited

Metrology

Doping
Deposition Photo Etching R. Strip

• Frontend: Photolithography
– Wafer cleaning
• Backend:
– Release, dicing, testing, and integration, packaging 2
Photolithography
• Using light to define features in the material to be removed
• Consists of photo exposure and etching steps.
– Projection photolithography
– Contact photolithography

Mask

Mask Aligner
3
Photolithography
• The photomask (mask):
– Rectangular glass plate with chrome on it
– Contains the pattern that will be transferred to the currently processed layer on the
wafer via the process of photolithography
– Needs to be larger than the wafer, in general by one inch.
• E.g., 3 “ diameter wafer → 4” rectangular mask
– Can be negative or positive

4
Positive Photolithography

A
mask

A
wafer

Chrome on mask denotes the presence of photoresist, and thus presence of


structural layer after etch
5
Negative Photolithography

A
mask

A
wafer

Chrome on mask denotes the absence of photoresist, and thus absence of


structural layer after etch
6
Etching
• Removing area selectively patterned by Photoresist
• Important parameters:
– Etch rate: how fast is material etched ( nm/min, A/s etc.)
– Selectivity: speed of etching vs. photoresist or etch-stop material
etch(x times, say 100x)
– Etch-stop: An underlying layer that causes the etch to stop (because
of high etch selectivity)
– Isotropic: Etches equally in all directions

– Anisotropic: Etches preferentially along certain crystalline planes.


• Si vs. SiO2 are etched by mutually exclusive etches.
7
Wet Etching
• Selected Wet Etchants:

• KOH Anisotropic Etch:


– High selectivity between
[100] and [111] planes

8
Dry Etching
• Plasma Assisted Etching:
– Plasma is used to remove material
– Direct mechanical impact: Ion Milling
• Zero or low selectivity
– Reactive species in plasma: Reactive Ion Etching (RIE)
• Different gaseous species etch different materials:

– Anisotropic, since ions impact the surface more than the sidewalls
Remove resist at the end

<Etch rates II> 9


Dry Etching
• Deep Reactive Ion Etching (DRIE)
– Includes an interleaved etch and protection step
• Silicon etch SF6
• Polymer deposition C4F8
– Vertical sidewalls (Bosh process)

• Vapor Etching

<Etch rates II> 10


Pros. and Cons.
• Wet etching:
– Tends to be faster
– KOH
– Photoresist selectivity good
• Dry etching:
– Avoid liquid phase
– RIE more anisotropic
– Lower selectivity
– Slower
– Difficult to etch oxide

11
Etching

12
Specially MEMS: Release Etch
• Final stage of the micromachining process (usually surface)
• Removal of interlayer sacrificial material
– Usually oxide in a polysilicon process
• Creates mechanically suspended structures
• Can be dry or wet
– HF plasma vs. wet HF
• Isotropic

13
14
Etch Release Holes
• During release etch we are primarily concerned about rate of undercut
• Etch release holes are placed to ensure complete release of large flat
structures

Silicon
Silicon Dioxide
Silicon

15
Etch Release Holes
• During release etch we are primarily concerned about rate of undercut
• Etch release holes are placed to ensure complete release of large flat
structures

Silicon
Silicon Dioxide
Silicon

HF

16
Etch Release Holes
• During release etch we are primarily concerned about rate of undercut
• Etch release holes are placed to ensure complete release of large flat
structures

Silicon
Silicon Dioxide
Silicon

HF

17
Etch Release Holes
• During release etch we are primarily concerned about rate of undercut
• Etch release holes are placed to ensure complete release of large flat
structures

Silicon
Silicon Dioxide
Silicon

HF

Incomplete release

18
Etch Release Holes
• During release etch we are primarily concerned about rate of undercut
• Etch release holes are placed to ensure complete release of large flat
structures

Silicon
Silicon Dioxide
Silicon

HF

Complete release

19
Etch Release Holes
• What decides on the maximum distance a between the etch realease
holes ?
• Time to undercut tuc :
1 a
tuc =
2 Re

• Re is the etch rate of the sacrificial layer


• Re varies
2 Rete
a=

• te is (acceptable) release etch time,  is the safety factor
Supercritical Drying
• Prevent released (suspended structures) to stick together during transition
from wet to dry (drying)
• Liquid to gas transition is omitted altogether by traversing across a “critical
point”, where boundary between gas and liquid seizes to exist
• Usually using liquid CO2 at high pressure
• Supercritical fluid, liquid indistinguishable from gas

21
Project Fabrication Process
• UIC-SOI Fabrication Process:
– Mimics single-layer surface micromachining
– SOI: 2 or 3 m device layer
– Two (2) mask layers

(Lab 0) Safety, safety quiz


(Lab 1) Wafer clean
(Lab 2) Deposition of Cr/Au Chrome/Gold (50/200 nm)

Device layer
2 m
Buried Oxide (BOX) 0.5 - 2 m

500 m
Handle wafer

22
Project Fabrication Process
• UIC-SOI Fabrication Process:
– Mimics single-layer surface micromachining
– SOI: 2 or 3 m device layer
– Two (2) mask layers

(Lab 2) Deposition of Cr/Au


(Lab 3) MASK 1 Pattern Cr/Au

2 m
0.5 - 2 m

500 m

23
Project Fabrication Process
• UIC-SOI Fabrication Process:
– Mimics single-layer surface micromachining
– SOI: 2 or 3 m device layer
– Two (2) mask layers

(Lab 2) Deposition of Cr/Au


(Lab 3) MASK 1 Pattern Cr/Au
(Lab 4,5) MASK 2 Pattern Device L.
(Lab 6) DRIE Pattern Device L. + + 2 m
0.5 - 2 m

500 m

24
Project Fabrication Process
• UIC-SOI Fabrication Process:
– Mimics single-layer surface micromachining
– SOI: 2 or 3 m device layer
– Two (2) mask layers

(Lab 2) Deposition of Cr/Au


(Lab 3) MASK 1 Pattern Cr/Au
(Lab 4,5) MASK 2 Pattern Device
L. 6) DRIE Pattern Device L. 2 m
(Lab 0.5 - 2 m
(Lab 8) HF Release 500 m

25
Project Fabrication Process
• UIC-SOI Fabrication Process:
– Mimics single-layer surface micromachining
– SOI: 2 or 3 m device layer
– Two (2) mask layers

(Lab 2) Deposition of Cr/Au


(Lab 3) MASK 1 Pattern Cr/Au
(Lab 4,5) MASK 2 Pattern Device
L. 6) DRIE Pattern Device L. 2 m
(Lab 0.5 - 2 m
(Lab 8) HF Release 500 m
(Lab 9) Critical Point Drying
(Lab 10) Scanning Electron Microscopy

26
Project Fabrication Process
• UIC-SOI Fabrication Process:
– Simple – only two (2) mask layers
– What can we make ??
2 m
0.5 - 2 m

A LOT !! 500 m

Thermal Electrostatic
Resonators Switches
actuators actuators

27

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