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CS501 Quiz-2 By Vu Topper RM

Advance Computer Architecture (Virtual University of Pakistan)

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CS-501 Advanced Computer Architecture

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In Falcon-A processor, the size of each I/O port is .

A. 8 bits
B. 16 bits
C. 256 bytes
D. 8 bytes

Total number of data registers in Motorola 68000 processor are

.
A. 8
B. 12
C. 24
D. 32

Which notation do we use to name different fields of a register in RTL?

A. +
B. <-
C. :=
D. ()

In EAGLE, the maximum number of operands allowed in an

instruction are .
A. 2
B. 4 Page 120
C. 6
D. 8

Which of the following instruction is considered most important in a

pipelined EAGLE architecture?
A. INIT
B. NOP
C. HALT
D. RESET

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The size of data bus of MC68000 processor is .

A. 8 bits
B. 16 bits
C. 32 bits
D. 64 bits

In Type-1 instruction, bits are reserved for the op-code.

A. bits 1 through 5 Page 91
B. bits 0 through 4
C. bits 0 through 8
D. bits 11 through 15

Which of the given below measure(s) is/are used for comparison of

performance of various machines?
A. MIPS
B. MFLOPS
C. Execution time
D. All of the these

Which field of the machine language instruction is the "type of

operation” that is to be performed?
A. Op-code Page 33
B. I/O locations
C. Memory cells
D. CPU registers

Which of the following bits of SRC instruction are used to hold an

operand, an address index, or a branch target register?
A. The bits 16 through 0
B. The bits 17 through 0
C. The bits 26 through 22
D. The bits 21 through 17

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Program counter (PC) holds the memory address of _ ?

Next instruction Page 104

For the type instructions, we require a register to hold the

data that is to be loaded from the memory, or stored back to the
memory
A. Jump
B. Branch
C. Control
D. load/store Page 89

To implement an N-bit barrel shifter in form of a combinational

circuit, we require N .
A. Selectors
B. Multiplexers
C. Demultiplexers
D. Tri-state buffers

Which type of instructions help in changing the flow of the program as

and when required?
A. Control Page 137
B. Arithmetic
C. Data transfer
D. Floating point

In a register-based machine having 64 registers, a field is

required in instruction to identify a register.
A. 6 bits Page 22
B. 16 bits
C. 32 bits
D. 64 bits

What is the instruction length of the FALCON-E processor?

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A. 6 bits
B. 16 bits
C. 32 bits
D. 64 bits

Which one of the following is a bi-stable device, capable of storing one

bit of Information?
A. Diplexer
B. Decoder
C. Flip-flop Page 76
D. Multiplexer

The SPARC architecture defines a that allows

for multiple address spaces.
A. Memory Logic Unit (MLU)
B. Memory Shifting Unit (MSU)
C. Memory Mapping Unit (MMU)
D. Memory Arithmetic Unit (MAU)

Motorola MC68000 is an example of microprocessor.

A. SRC
B. RISC
C. CISC Page 150
D. FALCON

In Type C instruction of SRC, bits are allocated for constant

value.
A. 22
B. 17
C. 21
D. 16

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Which of the following is NOT an advantage of using register-to-register

data transfers?
A. La
B. Idr
C. Le
D. Lar

Which of the instruction is used to load register from memory using a

relative address?
A. ld instruction
B. str instruction
C. lar instruction
D. ldr instruction Page 47

In "Jump [8]" instruction, the size of the constant field is

bits.
A. 8
B. 16
C. 32
D. 64

A collection of all possible machine language commands that

a computer can understand and execute is called .
A. Opcodes
B. Bytecodes
C. Mnemonics
D. Instruction Set Page 23

In a simple RISC computer, the size of each register is .

A. 32 bits
B. 16 bits
C. 24 bits
D. 64 bits

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Which of the following is NOT related to the architecture of a computer?

A. Instruction set
B. Control signals
C. I/O mechanisms
D. Memory addressing modes

The instruction "Load R1, [R3 + 20]" is an example of which of the

following addressing modes?
A. Direct
B. Register
C. Immediate
D. Displacement

In SRC, the effective address is computed at run-time by adding

a constant to value of register.
A. PC
B. IP
C. RA
D. Flags

The syntax of the instruction ‘branch and link if zero’ is

A. brlzr ra, rb, rc Page 170
B. brzr ra, rb, rc
C. brnz ra, rb, rc
D. brinz ra, rb, rc

The control signal enables the input to the register C for writing
the incremented value of PC onto it.
A. LC Page 159
B. LPC
C. INC4
D. PCout

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Which one of the following register holds the instruction that is being
executed?
A. Accumulator
B. Address Mask
C. Program Counter
D. Instruction Register Page 152

is defined as the number of instructions processed per second.

A. Latency
B. Throughput Page 187
C. ALU operation
D. Memory access

In pipe-lined processor, there should be a port register file so that

if the register write and register read stages overlap they can be
performed in parallel.
A. Four
B. Two
C. One
D. Three Page 188

is a register which takes input from the ALSU as memory

address to be accessed and transfer the memory contents on that
location onto the memory sub-system.
A. PC
B. IR
C. MAR Page 140
D. MBR

“Finite-state machine” concepts are usually used to represent the

control unit where every state corresponds to clock cycles(s).
A. 1 Page 172

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B. 2
C. 4
D. 16

control signal allows the contents of the Program Counter

register to be written onto the internal processor bus.
A. LC
B. LPC
C. INC4
D. PCout Page 159

Which one of the following control signals causes the data from the bus
to be read into the register MAR.
A. MARout
B. MARin
C. LMAR Page 154
D. None of the given

operation is required to change the processor‟s state to a

known, defined value.
A. Change
B. Reset Page 208
C. Update
D. None of the given

There are types of reset operations in SRC

A. Two Page 195
B. Four
C. Five
D. Three

Which one of the following registers stores a previously calculated value

or a value loaded from the main memory?

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A. Accumulator
B. Address Mask
C. Program Counter
D. Instruction Register

In CPU design, creates or forms the interface between the

data path and control unit.
A. ALU
B. Cache
C. Buses
D. Control signal Page 153

is defined as the time required to process a single instruction.

A. Latency Page 217
B. Throughput
C. ALU operation
D. Memory access

Upon receiving the signals, the SRC should perform a hard reset.
A. Rst
B. Con
C. Strt Page 209
D. Stop

The MAR is connected directly to the

A. LIC
B. MBR
C. CPU Internal bus Page 186+187
D. CPU external bus

In the case of a constant, variable, an address or (label-PC) the jump

ranges
A. From-64 to 63

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B. From -128 to 127 Page 171

C. From -256 to 255
D. From -32768 to 32767

In MC68000, register is used as stack pointer:

A. A0
B. A7
C. D0
D. D7

During the RESET operation of processor, control step counter is

set to
A. 1
B. 0 Page 115
C. 2
D. -1

In a processor, is responsible for the synchronization of

internal as well external events.
A. Data Unit
B. Control Unit Page 198
C. Memory Unit
D. Arithmetic & Logic Unit

CISC Stands for?

A. Complex internal system computer
B. Computer instruction set compiler
C. Complex instruction system compiler
D. Complex Instruction Set Computers Page 10

SPARC uses a simple set of instruction format.

A. 64-bit

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B. 12-bit
C. 16-bit
D. 32-bit

FALCON-A processor bus has 16 lines or is 16-bits wide while that of

SRC wide.
8-bits
16-bits
32-bits Page 157
64-bits
For any of the instructions that are a part of the instruction set of the
SRC, there are cerain required; which may be used to
select the appropriate function for the ALU to be performed, to select
the appropriate registers, or the appropriate memory location.
Register
Control signals (Page 171)
Memory
None of the given
What is the instruction length of the FALCON-A processor?
8-bits
16-bits (Page 134)
32-bits

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64-bits
control signals enable the input to the PC for receiving
a value that is currently on the internal processor bus.
LPC (Page 172)
INC4
LC
I

Which instruction is used to store register to memory using relative

address?
ld instruction
ldr instruction
lar instruction
str instruction (Page 48)

The instruction will load the register R3 with the

contenets of the m\emory location M [PC+56]
Add R3, 56
lar R3, 56
ldr R3, 56 (Page 56)
str R3, 56

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Which one of the following registers holds the address of the next
instruction to be executed?
Accumulator
Address Mask
Instruction Register
Program Counter (Page 151)
Which one of the following is the memory organization of EAGLE
processor?
8-bits (Page 112)
16-bits
32-bit
64-bits
Type A of SRC has which of the following instructions? A) andi,
instruction b) No operation or nop instruction c) lar instruction d) ldr
instruction e) Stop operation or stop instruction
& (b)
(b) & (c)
& (e)
(b) & (e) (Page 47)
What is the instruction length of the SRC processor?

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8 bits
16 bits
32 bits (Page 134)
64 bits
Which one of the following is the memory organization of FALCON-E
processor?
28 * 8 bits
216 * 8 bits
232 * 8 bits (Page 124)
264 * 8 bits
----------are faster than cache memory

CPU registers (Page 33)

I/O devices

ROM

Accumulator register
P: R3 ¬ R5 MAR ¬ IR These two are instructions written using RTL .If
these two operations is to occur simultaneously then which symbol will
we use to separate them so that it becomes a correct statement with the
condition that two operations occur simultaneously?
Arrow ¬
Colon :

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Comma , (Page 69)

Parentheses ()
Prefetching can be considered a primitive form of-------------

Multi-processing

Self-execution

Exception

Pipelining (Page 42)

Which one of the following circuit design levels is called the gate level?

Circuit Level

Mask Level
None of the given

Logic Design Level (Page 22)

controller controls the sequence of the flow

of microinstructions.
Multiplexer
Microprogram (Page 225)
ALU
None of the given
The code size of 2-address instruction is .

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5 bytes
7 bytes (Page 36)
3 bytes
2 bytes
Register-register instructions use memory operands out
of a total of 3 operands
1
3
0 (Page 37)
2
Flip-flop is a device, capable of storing one bit
of Information
Bi-stable (Page 76)
Unit-stable
Stable
Storage
Execution time of a program with respect to the processor is calculated
as:
Execution Time = IC x CPI x MIPS
Execution Time = IC x CPI x T (Page 254)
Execution Time = CPI x T x MFLOPS

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Execution Time = IC x T
An “assembler” that runs on one processor and translates an assembly
language program written for another processor into the machine
language of the other processor is called a ----------------
compiler
cross assembler (Page 26)
debugger
linker
What functionality is performed by the instruction “lar R3, 36” of SRC?
It will load the register R3 with the contents of the memory location M
[PC+36]
It will load the register R3 with the relative address itself (PC+36).
(Page 48)
It will store the register R3 contents to the memory location M [PC+36]
No operation
Which operator is used to „name‟ registers, or part of registers, in the
Register Transfer Language? Select correct option
:= (Page 66)
&
%
©

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What is the working of Processor Status Word (PSW)?

To hold the current status of the processor. (Page
28) To hold the address of the current process
To hold the instruction that the computer is currently processing
To hold the address of the next instruction in memory that is to be
executed
Almost every commercial computer has its own particular ----------
language
3GL
English language
Higher level language
assembly language (Page 25)
In which of the following instructions the data move between a register
in the processor and a memory location (or another register) and are
also called data movement?
Arithmetic/logic
Load/store (Page 141)
Test/branch
None of the given
What functionality is performed by the instruction “str R8, 34” of SRC?

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It will load the register R8 with the contents of the memory location M
[PC+34]
It will load the register R8 with the relative address itself (PC+34).
It will store the register R8 contents to the memory location M
[PC+34] (Page 48)
No operation

What does the instruction “ldr R3, 58” of SRC do?

It will load the register R3 with the contents of the memory location
M [PC+58] (Page 47)
It will load the register R3 with the relative address itself (PC+58).
It will store the register R3 contents to the memory location M [PC+58]
No operation
Which one of the following is the highest level of abstraction in digital
design in which the computer architect views the system for the
description of system components and their interconnections?
Processor-Memory-Switch level (PMS level) (Page 22)
Instruction Set Level
Register Transfer Level
None of the given

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What is the size of the memory space that is available to FALCON-A

processor?
2^8 bytes
2^16 bytes (Page 90)
2^32 bytes
2^64 bytes
How can we refer to an instruction register (IR), of 16 bits (numbered 0
to 15) using RTL?
IR<16..0>
IR<15..0> (Page 105)
IR<16..1>
IR <15..1>
Which one of the following portions of an instruction represents the
operation to be performed?
Address
Instruction code
Opcode
Operand (Page 134)
Identify the opcode, destination register (DR), source registers (SA and
SB i/e source register A and source register B) from the following
example. ADD R1, R2, R3

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Opcode= R1, DR=ADD, SA=R2, SB=R3

Opcode= ADD, DR=R1, SA=R2, SB=R3 (Page 34)
Opcode= R2, DR=ADD, SA=R1, SB=R3
Opcode= ADD, DR=R3, SA=R2, SB=R1
Which one of the following is the code size and the Number of memory
bytes respectively for a 2-address instruction?
4 bytes, 7 bytes
7 bytes, 16 bytes (Page 36)
10 bytes, 19 bytes
13 bytes, 22 bytes

The external interface of FALCON-A consists of a data bus.

8-bit
16-bit (Page 167)
24-bit
32-bit
Which one of the following register(s) that is/are programmer invisible
and is/are required to hold an operand or result value while the bus is
busy transmitting some other value?
Instruction Register
Memory address register

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Memory Buffer Register

Registers A and C (Page 152)

While executing the RTL instruction A ← R3, which of the given

below control signals will be activated?

The multiplexer------------is used to decide which value is transferred to

be written back to the register file.
MP2
MP3
MP4
MP5
Which of the following condition is evaluated when executing the
branch instruction “brzr R2, R1”?
If(R2==0) •
If( R1 >0 )
If( R1==0)
If( R1 < 0)
In case of SRC processor, bits---------of IR (instruction register) are
reserved for the opcode.
0 to 4
11 to 15

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27 to 31
59 to 63
Which of the given RTL description is used to represent “load
instruction register” (ldr) instruction?
(op=6): R[ra] rel
(op=2): R[ra] M [rel]
(op=2): M[disp] R [ra]
(op=2): M[rel] R [ra]
-------- Instruction is used to divide a register value by immediate value
in FALCON-E processor.
div
idiv
divi
divim
Which field of machine language instruction is the “type of operation”
that is to be performed.
Op-code(or the operation code)
CPU register
Memory Cells
I/O Location

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Which of the following control signal is NOT activated during

instruction fetch operation?
PCout
LC
LMAR
Cout
In case of FALCON-A------------ instruction are present which are not
present in SRC processor.
create and destroy
in and out
open and close
read and write

---------- provides a temporary storage for the address of memory

location to be accessed.
MAR
MBR
PC
LPC
Which of the following register is used to enable the tri-stable buffers
with the MBR?

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MBRout
MARout
LMBR
INC4
Program Counter(PC) holds the memory address of:
Previous Instruction
Current Instruction
Next Instruction
Previous and Current Instruction
mul is the example of a(n)------------operation.
Logic
Shift
Arithmetic
Data transfer
Control Signal for RTL “IR< ---MBR” will be---------
MBRout,LIR
PC< --C
PC< --MBR
PC< --IR

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The status register of the 68000 has -------- condition codes.

2
3
5
8
Which of the instruction is used to load register from memory using
relative address?
ld instruction
ldr instruction
lar instruction
str instruction
For the ------ type instruction, we require a register to hold the data that
is to be loaded from the memory, or stored back to the memory.
Jump
Control
load/store
Branch

--------- control signal allow the content of the program counter register
to be written onto the internal processor bus.
INC4

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LPC
PCout
LC
In ---------- instruction format of EAGLE processor, there is no field
reserved for the operands.
Type V
Type Y
Type X
Type Z
A general purpose digital computer has --------- main components.
2
3
4
5
The instruction ---------- will load the register R3 with the contents of the
memory location M[PC+56].
lar R3,M[56]
ldr R3,M[56]
ldr R3,56
lr R3,[56]

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In FALCON-A instruction format of Type-2 constants and variable

should be in the range of.
-132 to +131
-164 to + 163
-32 to + 31
-128 to + 127
In a FALCON-A assembly program, labels are used to implement--------
--- jump.
Direct
Indirect
Relative
Displacement
In “Jump [8]” instruction, the size of the constant fields is---------bits.
4
5
8
16

Which of the following registers is used as an implicit operand in

MUL/DIV instruction of FALCON-A?
R0

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PC
IR
SP
To set the value of micro-PC from branch address, the value of 4 to 1
multiplexer is------------
00
01
10
11
The instruction “PUSH A” is an example of ------------
0-address instruction
1-address instruction
2-address instruction
3-address instruction
Which of the following branch instruction has a condition which is
always executed?
JZ
JUMP
JPL
JMI

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----------- hazard occurs when attempting to access same resource in

different ways at the same time.
Branch
Data
Structural
Instruction
------------ is an example of Miscellaneous instruction.
Shift
Store
Halt
Call
Which type of instructions enables mathematical computations?
Arithmetic
Control
Data transfer
Numeric
VLIW Stands for-------------
Variable Length Instruction Word
Very Long Instruction Word
Very Long Instruction Width

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Variable Length Instruction Width

In SRC, the general-purpose register file includes--------------registers,
each 32 bit wide.
6 Registers R0 to R15
24 Registers R0 to R23
32 Registers R0 to
R31 64 Registers R0 to
R63
The CPU includes three types of instructions, which have different
operands and will need different representations. Which one of the
instructions requires two source registers?
Jump and branch format instructions
Immediate format instructions
Register format instructions
All of the above
What does the word ‘D’ in the ‘D-flip-Flop’ stands for?
Data
Digital
Dynamic
Double
The instruction ---------------will load the register R3 with the contents of
the memory location M [PC+56]
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Add R3, 56
lar R3, 56
ldr R3, 56
str R3, 56
Which one of the following portions of an instruction represents the
operation to be performed?
Address
Instruction code
Opcode
Operand
Which operator is used to ‘name’ registers, or part of registers, in the
Register Transfer Language?
:=
&
%
©
Which of the following can be defined as an address of the operand in a
computer type instruction or the target address in a branch type
instruction?
Base address
Binary address

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Effective address
All of the given
Which of the following statements is/are true about RISC processors’
claimed advantages over CISC processors? (a) Keeping regularly
accessed variables in registers as opposed to keeping them in memory
facilitates faster execution. (b) RISC CPUs outperform CISC CPU’s in
procedural programming environments. (c) Instruction pipelining has
helped RISC CPU’s to attain a target of 1 cycle per instruction. (d) It
is easier to maintain the “family concept” in RISC CPU.
(a), (b) &(c)
(b), (c) & (e)
(c), (d) & (e)
(a), (c) & (d)
In which one of the following techniques, the time a processor spends
waiting for instructions to be fetched from memory is minimize
Perfecting
Pipelining
Superscalar operation
Speedup
The processor must have a way of saving information about its state or
context so that it can be restored upon return from the -------------
Exception

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Function
Thread
Stack
-----------is the ability of application software to operate on models of
equipment newer than the model for which it was originally developed.
Backward compatibility
Data migration
Reverse engineering
Upward compatibility

Computer system performance is usually measured by the ---------------

Time to execute a program or program mix
The speed with which it executes programs
Processor’s utilization in solving the problems
Instructions that can be carried out simultaneously
The external interface of FALCON-A consists of a address
bus and a data bus.
8-bit , 8-bit
16-bit , 16-bit
16-bit , 24-bit
• 16- bit , 32-bit

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Which one of the following register(s) contain(s) the address of the place
the CPU wants to work with in the main memory and is/are directly
connected to the RAM chips on the motherboard?
Instruction Register
Memory address register
Memory Buffer Register
Registers A and C
Among the two approaches available to design a control unit, hardware
approach is relatively---------- as compared to micro-programming.
Slow
Fast
Average
Better

Which of the following is not a part of processor

state? IR
PC
Stacks
Registers
----------------- form the branch control field in the micro instruction.
C Bits

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M Bits
B BITS
M Bits

In FALCON-A ISA, which of the following opcodes is used to perform

“No Operation”?
20
21
22
23
To apply two shifts to an input number using the barrel shifter,
the control signals S1 and S0 of the shifter should be------------.
S1 = 1 and S0 = 1
S1 = 0 and S0 = 1
S1 = 1 and S0 = 0
S1 = 2 and S0 = 0

Which one of the following operations is NOT performed by using

miscellaneous instructions?
Clearing all registers
Stopping the processor

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NOP
Returning from a procedure

RISC stands for?

Registers internal system cache
Reduced instruction set computer
Registers instruction set computer
Reduced internal system computers
Which of the followings is not an example of super-scalar processors?
PowerPC601
IAPX88
Intel P6
DEC Alpha 21164
What does the instruction “idr R3, 58” of SRC do?
It will load register R3 with the contents of the memory
location M[PC+58]
It will load register R3 with the relative address itself (PC+58)
It will store register R3 contents to the memory location M[PC+58]
It will store the value of register R3 at the relative address itself (PC+58)

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For a processor having 32 general purpose register,---------------bits are

required for each register field in the instruction:
32
3
8
5
Which of the following registers is/are programmer invisible and
is/are required to hold an operand or result value while the bus is busy
transmitting some other value?
Instruction register
Memory address register
Memory Buffer Register
Registers A and C
In SRC which of the following is a notation which is used to repeat 32-
bit memory word stored at address starting from 56?
M[56]<31..0>:=M[56]M[57]M[58]M[59]
M[56]<o..31>:=M[56]M[57]M[58]M[59]
M[56]<0..31>:=M[59]M[58]M[57]M[56]
M[56]<0.31..>:=M[59]M[58]M[57]M[56]
Which of the following branch instruction has a condition which is
always executed?
JZ

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JUMP
JPL
JMI
Which of the following EAGLE instruction is used to initialize all
the registers by setting them to 0?
NOP
HALT
INIT
RESET
The ALSU function “INC2” increments the ------------ by 2 and the
output is stored in the buffer register
.PC,A
IR,A
PC,C
IR,C
Which temporary register is loaded with either a register value from
the register file or a constant from the instruction?
Y3
X3
Z4
Z5

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------------ instruction is used to load a register with an immediate value.

la
lar
ld
ldr
A computer belongs to which of the following subset of the
systems? Mechanical system
Electrical system
Optical system
Magnetic system
Which of the following code size and the number of memory bytes
respectively for a 2-address instruction.
4 bytes, 7 bytes
7 bytes ,16 bytes
10 bytes , 19 bytes
13 bytes, 19 bytes
Which of the the given below measures is/are used for comparison of
performance of various machine?
Execution time
MFLOPS

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MIPS
All of the given
There are ------------- type of RESET operation in SRC.
Three
Four
Two
five
Type checking allows the -------------- to determine memory for
variables
Compiler
Debugger
Linker
loader
In FALCON-A processor, memory word size is----------------
1 byte
4 bytes
8 bytes
2 bytes
To connect together five (5) m-bit registers in a point-to-point scheme,
connections are required.
25

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30
20
24
Almost every commercial computer has its own particular
language.
3 GL
English Language
High Level Language
Asseembly Language
Which of the given RTL description is used to represent store
register relative (str) instruction? (op<4..0>=4):M[rel]<-R[ra]
Which of the given RTL description is used to represent load
displacement address (Ia) instruction? (op<4..0>=5):R[ra]<-disp
Which of the given RTL description is used to represent load
relative address (Iar) instruction? (op<4..0=6):R[ra]<-rel
Which of the given RTL description is used to represent conditional
branch (br) instruction?
(op<4..0>=8): (cond : PC<- R[rb]),
Which of the given RTL description is used to represent branch
and bank (brl) instruction?
Cond : (PC <- R [rb]))

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Which of the given RTL description is used to represent store

register (st) instruction?
(op<4..0>=3):M[disp]<-R[ra]
Which of the given RTL description is used to represent load
register relative (Idr) instruction?
(op<4..0>=2) : R[ra] <- M[rel]
Which of the given RTL description is used to represent load
register (Id) instruction?
(op<4.00>=1):R[ra]<-M[disp]
In a simple RISC computer the size of each register is .
32 bits
A is a device that provides a shared data path to a number of
devices that are connected to it.
Bus
instruction is used to store register contents to memory
St
Which type of instructions load data from memory into register or store
data from register into memory and transfer into memory and transfer
data between different kinds of special-purpose registers?
Data transfer…
A stack based machine is also called .
0-address machine

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Which of the following bits of SRC instruction are used to hold the
instruction register, used to hold the current instruction
The bits 31 through 0
Which of the following bits of SRC instruction are used to hold
program counter(it holds the memory address of next instruction to be
executed)?]
The bits 31 through 0……confirm
Which of the following bits of SRC instruction are used to hold short
displacement or immediate field? The bits 16 through 0
Which of the following bits of SRC instruction are used to hold count or
modifier field?
The bits 16 through 0
Which of the following bits of SRC instruction are used to hold a second
operand, conditional test, or a shift count register?
The bits 16 through 12
Which of the following bits of SRC instruction are used to hold long
displacement field?
The bits 21 thorugh 0
Which of the following is example of direct indirect addressing mode?
M[[R5] + [R5]]
Which of the following RTL description is used to represent the
target register of Falcon-A instruction Ra<2..0>:=IR<10..8>

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Which of the following RTL description is used to represent the

operation code of Falcon-A instruction Op<4..0>:= IR<15..11>:
Which of the following RTL description is used to represent the
operand or address index of Falcon-A instruction
Rb<2..0>:=IR<7..5>:
Which of the following RTL description is used to represent the
second operand of Falcon-A instruction Rc<2..0>:=IR<4.2>
Which of the following RTL description is used to represent the
short displacement field of Falcon-A instruction
C1<4..0>:=IR<4..0>
Which of the following RTL description is used to represent the
long displacement or the immediate field of Falcon-A instruction
C2<7..0>:=IR<7..0>:
. The instruction Load R1, [R3 + 20] is an example of which of the
following addressing modes?
Register
In SRC, the op-code for NOP operation is .
0
Which of the following RTL description is used to represent all
general purpose register of SRC? R[0..31]<31..0>;
instruction is used to push the contents of a specified
general purpose register to the stack in FALCON-E processor

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Push
instruction is used to pop the value that is at the top of the
stack in FALCON-E processor Pop
instruction is used to branch if source operand is less than
target address in FALCON-E processor
Bl
. instruction is used to branch if source operand is greater
than target address in FALCON-E processor
Bg
instruction is used to multiply an immediate value with a
value stored in a register in FALCON-E processor
Muli
instruction is used to evaluate logical exclusive or in
FALCON-E processor
Xor, xori
Which of the following measure can be best used for calculating the
performance of computation intensive application
MFLOPS
All of the below given processors employ Little-Endian storage format
except .
Falcon-A

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he instruction shifti R1, R2, 20 is an example of which of the following

addressing modes?
Immediate

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