INA185 Current-Sensor
INA185 Current-Sensor
INA185
SBOS378 – MARCH 2019
RSENS E
Loa d
INA185 VS
Microco ntr oller
IN±
± OUT
ADC
+
IN+ REF
GND
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA185
SBOS378 – MARCH 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 17
2 Applications ........................................................... 1 8.1 Application Information............................................ 17
3 Description ............................................................. 1 8.2 Typical Application .................................................. 21
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 23
5 Pin Configuration and Functions ......................... 3 9.1 Common-Mode Transients Greater Than 26 V ...... 23
6 Specifications......................................................... 4 10 Layout................................................................... 24
6.1 Absolute Maximum Ratings ..................................... 4 10.1 Layout Guidelines ................................................. 24
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 24
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 25
6.4 Thermal Information .................................................. 4 11.1 Device Support...................................................... 25
6.5 Electrical Characteristics........................................... 5 11.2 Documentation Support ........................................ 25
6.6 Typical Characteristics .............................................. 6 11.3 Receiving Notification of Documentation Updates 25
7 Detailed Description ............................................ 12 11.4 Community Resources.......................................... 25
7.1 Overview ................................................................. 12 11.5 Trademarks ........................................................... 25
7.2 Functional Block Diagrams ..................................... 12 11.6 Electrostatic Discharge Caution ............................ 25
7.3 Feature Description................................................. 12 11.7 Glossary ................................................................ 25
7.4 Device Functional Modes........................................ 14 12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
OUT 1 6 VS
GND 2 5 REF
IN+ 3 4 IN±
Not to scale
Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
GND 2 Analog Ground
Current-sense amplifier negative input. For high-side applications, connect to load
IN– 4 Analog input side of sense resistor. For low-side applications, connect to ground side of sense
resistor.
Current-sense amplifier positive input. For high-side applications, connect to bus-
IN+ 3 Analog input voltage side of sense resistor. For low-side applications, connect to load side of
sense resistor.
OUT 1 Analog output Output voltage
REF 5 Analog input Reference input
VS 6 Analog Power supply, 2.7 V to 5.5 V
6 Specifications
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VIN+ and VIN– are the voltages at the IN+ and IN– pins, respectively.
(3) Input voltage at any pin can exceed the voltage shown if the current at that pin is limited to 5 mA.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Population
Population
-170
-155
-140
-125
-110
-95
-80
-65
-50
-35
-20
100
115
130
145
-5
10
25
40
55
70
85
40
80
0
-440
-400
-360
-320
-280
-240
-200
-160
-120
-80
-40
120
160
200
240
280
320
360
400 D001 D002
Input Offset Voltage (PV) Input Offset Voltage (PV)
Figure 1. Input Offset Voltage Production Distribution A1 Figure 2. Input Offset Voltage Production Distribution A2
Population
Population
-195
-180
-165
-150
-135
-120
-105
-130
-120
-110
-100
-90
-75
-60
-45
-30
-15
105
120
-90
-80
-70
-60
-50
-40
-30
-20
-10
15
30
45
60
75
90
10
20
30
40
50
60
70
80
0
D003 D004
Input Offset Voltage (PV) Input Offset Voltage (PV)
Figure 3. Input Offset Voltage Production Distribution A3 Figure 4. Input Offset Voltage Production Distribution A4
100
A1
A2
A3
50 A4
Offset Voltage ( PV)
Population
-50
-100
-50 -25 0 25 50 75 100 125 150
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
10
15
20
25
30
35
40
45
50
0
5
Population
-20
-18
-16
-14
-12
-10
-11
-10
-8
-6
-4
-2
10
12
14
16
18
20
22
-9
-8
-7
-6
-5
-4
-3
-2
-1
10
0
2
4
6
8
0
1
2
3
4
5
6
7
8
9
D007 D008
Common-Mode Rejection Ratio (PV/V) Common-Mode Rejection Ratio (PV/V)
Figure 7. Common-Mode Rejection Production Distribution Figure 8. Common-Mode Rejection Production Distribution
A2 A3
10
A1
Common-Mode Rejection Ratio (PV/V)
8 A2
6 A3
A4
4
2
Population
0
-2
-4
-6
-8
-10
-50 -25 0 25 50 75 100 125 150
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
10
11
0
1
2
3
4
5
6
7
8
9
Figure 9. Common-Mode Rejection Production Distribution Figure 10. Common-Mode Rejection Ratio vs Temperature
A4
Population
Population
-0.145
-0.115
-0.085
-0.055
-0.025
-0.16
-0.13
-0.1
-0.07
-0.04
-0.01
0.005
0.02
0.035
0.05
0.065
0.08
0.095
0.11
0.125
0.14
0.155
-0.14
-0.13
-0.12
-0.11
-0.1
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0
D011 D012
Gain Error (%) Gain Error (%)
Figure 11. Gain Error Production Distribution A1 Figure 12. Gain Error Production Distribution A2
Population
-0.155
-0.125
-0.095
-0.065
-0.035
-0.005
-0.265
-0.215
-0.165
-0.115
-0.065
-0.015
-0.17
-0.14
-0.11
-0.08
-0.05
-0.02
0.01
0.025
0.04
0.055
0.07
0.085
0.115
0.13
0.145
-0.29
-0.24
-0.19
-0.14
-0.09
-0.04
0.01
0.035
0.06
0.085
0.11
0.135
0.16
0.185
0.21
0.235
0.1
D013 D014
Gain Error (%) Gain Error (%)
Figure 13. Gain Error Production Distribution A3 Figure 14. Gain Error Production Distribution A4
0.4 50
A1 A1
0.3 A2 A2
A3 40 A3
0.2 A4 A4
30
Gain Error (%)
0.1
Gain (dB)
0 20
-0.1
10
-0.2
0
-0.3
-0.4 -10
-50 -25 0 25 50 75 100 125 150 10 100 1k 10k 100k 1M 10M
Temperature (qC) D015
Frequency (Hz) D016
A2
Power-Supply Rejection Ratio (dB)
100 120
A3
A4
100
80
80
60
60
40
40
20 20
0 0
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D017
Frequency (Hz) D018
Figure 17. Power-Supply Rejection Ratio vs Frequency Figure 18. Common-Mode Rejection Ratio vs Frequency
VS – 2
60
40
GND + 2
20
GND + 1
0
GND -20
0 5 10 15 20 25 30 35 40 45 50 55 60 -5 0 5 10 15 20 25 30
Output Current (mA) D019
Common-Mode Voltage (V) D020
Supply voltage = 5 V
Figure 19. Output Voltage Swing vs Output Current Figure 20. Input Bias Current vs Common-Mode Voltage
120 80
79
100
78
Input Bias Current (PA)
80 77
76
60
75
40
74
20 73
72
0
71
-20 70
-5 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 150
Common-Mode Voltage (V) D021
Temperature (qC) D022
Supply voltage = 0 V
Figure 21. Input Bias Current vs Common-Mode Voltage Figure 22. Input Bias Current vs Temperature
(Both Inputs, Shutdown)
210 400
205
350
Quiescent Current (PA)
200
300
195
250
190
200
185
180 150
-50 -25 0 25 50 75 100 125 150 -5 0 5 10 15 20 25 30
Temperature (qC) D023
Common-Mode Voltage (V) D031
80
70
Referred-to-Input
40
30
20
10
10 100 1k 10k 100k 1M Time (1 s/div)
Frequency (Hz) D024 D025
Figure 25. Input-Referred Voltage Noise vs Frequency Figure 26. 0.1-Hz to 10-Hz Voltage Noise (Referred-to-Input)
(A3 Devices)
VCM
Output Voltage
Figure 27. Step Response Figure 28. Common-Mode Voltage Transient Response
0V 0V
Figure 29. Inverting Differential Input Overload Figure 30. Noninverting Differential Input Overload
Voltage (1 V/div)
Voltage (1 V/div)
0V
0V
Time (10 Ps/div) Time (100 Ps/div)
D030 D032
50
20
10
5
2
1
0.5
0.2
0.1
10 100 1k 10k 100k 1M 10M
Frequency (Hz) D033
7 Detailed Description
7.1 Overview
The INA185 is a 26-V common-mode current-sensing amplifier used in both low-side and high-side
configurations. This specially-designed, current-sensing amplifier accurately measures voltages developed
across current-sensing resistors on common-mode voltages that far exceed the supply voltage powering the
device. Current can be measured on input voltage rails as high as 26 V, and the device can be powered from
supply voltages as low as 2.7 V.
VS
INA185
IN±
±
OUT
+
IN+ REF
GND
where
• ILOAD is the load current to be monitored.
• RSENSE is the current-sense resistor.
• GAIN is the gain option of the selected device.
• VREF is the voltage applied to the REF pin. (1)
Direction of Positive
IN+
Current Flow
High-Side Sensing
RSENSE Common-mode voltage (VCM)
is bus-voltage dependent.
IN±
LOAD
IN±
INA185 VS
IN±
OUT
±
Output
+
IN+ REF
GND
The linear range of the output stage is limited by how close the output voltage can approach ground under zero
input conditions. In unidirectional applications where measuring very low input currents is desirable, bias the REF
pin to a convenient value above 50 mV to get the output into the linear range of the device. To limit common-
mode rejection errors, buffer the reference voltage connected to the REF pin.
A less-frequently used output biasing method is to connect the REF pin to the power-supply voltage, VS. This
method results in the output voltage saturating at 25 mV less than the supply voltage when no differential input
signal is present. This method is similar to the output saturated low condition with no input signal when the REF
pin is connected to ground. The output voltage in this configuration only responds to negative currents that
develop negative differential input voltage relative to the device IN– pin. Under these conditions, when the
differential input signal increases negatively, the output voltage moves downward from the saturated supply
voltage. The voltage applied to the REF pin must not exceed VS.
INA185 VS
IN± Reference
Voltage
± OUT
Output
+
IN+ REF
+
GND ±
The ability to measure this current flowing in both directions is enabled by applying a voltage to the REF pin, as
shown in Figure 36. The voltage applied to REF (VREF) sets the output state that corresponds to the zero-input
level state. The output then responds by increasing above VREF for positive differential signals (relative to the IN–
pin) and responds by decreasing below VREF for negative differential signals. This reference voltage applied to
the REF pin can be set anywhere between 0 V to VS. For bidirectional applications, VREF is typically set at mid-
scale for equal signal range in both current directions. In some cases, however, VREF is set at a voltage other
than midscale when the bidirectional current and corresponding output signal do not need to be symmetrical.
RPULL-UP
10 k
Bus Voltage
±0.2 V to +26 V Shutdown
RSENSE
Load
CBYPASS
0.1 µF
INA185 VS
IN±
OUT
± Output
+
IN+ REF
GND
Figure 37. Basic Circuit to Shut Down the INA185 With a Grounded Reference
There is typically more than 500 kΩ of impedance (from the combination of 500-kΩ feedback and
input gain set resistors) from each input of the INA185 to the OUT pin and to the REF pin. The amount of current
flowing through these pins depends on the voltage at the connection. For example, if the REF pin is grounded,
the calculation of the effect of the 500 kΩ impedance from the shunt to ground is straightforward. However, if the
reference is powered while the INA185 is in shutdown mode, instead of assuming 500 kΩ to ground, assume
500 kΩ to the reference voltage.
Regarding the 500-kΩ path to the output pin, the output stage of a disabled INA185 does constitute a good path
to ground. Consequently, this current is directly proportional to a shunt common-mode voltage present across a
500-kΩ resistor.
As a final note, as long as the shunt common-mode voltage is greater than VS when the device is powered up,
there is an additional and well-matched 55-µA typical current that flows in each of the inputs. If less than VS, the
common-mode input currents are negligible, and the only current effects are the result of the 500-kΩ resistors.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
INA185 VS
IN± Microcontroller
OUT
±
ADC
+
IN+ REF
GND
NOTE: To help eliminate ground offset errors between the device and the analog-to-digital converter (ADC), connect
the REF pin to the ADC reference input and then to ground. For best performance, use an RC filter between the
output of the INA185 and the ADC. See the Closed-Loop Analysis of Load-Induced Amplifier Stability Issues Using
ZOUT section for more details.
A power-supply bypass capacitor of at least 0.1 µF is required for proper operation. Applications with noisy or
high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.
Connect bypass capacitors close to the device pins.
RSENSE
Load VS
2.7 V to 5.5 V
1 INA185 VS
f 3dB
2S(RF RF )CF RF < 10 RINT
IN±
f±3dB
CF ± OUT VOUT
Bias
+
The addition of external series resistance creates an additional error in the measurement; therefore, the value of
these series resistors must be kept to 10 Ω (or less, if possible) to reduce impact to accuracy. The internal bias
network shown in Figure 39 present at the input pins creates a mismatch in input bias currents when a
differential voltage is applied between the input pins. If additional external series filter resistors are added to the
circuit, the mismatch in bias currents results in a mismatch of voltage drops across the filter resistors. This
mismatch creates a differential error voltage that subtracts from the voltage developed across the shunt resistor.
This error results in a voltage at the device input pins that is different than the voltage developed across the
shunt resistor. Without the additional series resistance, the mismatch in input bias currents has little effect on
device operation. The amount of error these external filter resistors add to the measurement can be calculated
using Equation 6, where the gain error factor is calculated using Equation 5.
The amount of variance in the differential voltage present at the device input relative to the voltage developed at
the shunt resistor is based both on the external series resistance (RF) value as well as the internal input resistor
RINT, as shown in Figure 39. The reduction of the shunt voltage reaching the device input pins appears as a gain
error when comparing the output voltage relative to the voltage across the shunt resistor. A factor can be
calculated to determine the amount of gain error that is introduced by the addition of external series resistance.
Calculate the expected deviation from the shunt voltage to what is measured at the device input pins is given
using Equation 5:
1250 u RINT
Gain Error Factor
(1250 u RF ) (1250 u RINT ) (RF u RINT )
where:
• RINT is the internal input resistor.
• RF is the external series resistance. (5)
The gain error that can be expected from the addition of the external series resistors can then be calculated
based on Equation 6:
Gain Error (%) = 100 - (100 ´ Gain Error Factor) (6)
For example, using an INA185A2 and the corresponding gain error equation from Table 2, a series resistance of
10 Ω results in a gain error factor of 0.991. The corresponding gain error is then calculated using Equation 6,
resulting in an additional gain error of approximately 0.89% solely because of the external 10-Ω series resistors.
INA185 VS
IN± Reference
Voltage
± OUT
Output
+
IN+ REF
+
GND ±
V, the maximum current-sense gain calculated to avoid the positive swing-to-rail limitations on the output is
122.5. Likewise, using Equation 4 for the negative-swing limitation results in a maximum gain of 124.75.
Selecting the gain-of-100 device maximizes the output range while staying within the output swing range. If the
maximum calculated gains are slightly less than 100, the value of the current-sense resistor can be reduced to
keep the output from hitting the output-swing limitations.
To calculate the accuracy at peak current, the two factors that must be determined are the gain error and the
offset error. The gain error of the INA185A3 is specified to be a maximum of 0.2%. The error due to the offset is
constant, and is specified to be 130 µV (maximum) for the conditions where VCM = 12 V and VS = 5 V. Using
Equation 7, the percentage error contribution of the offset voltage is calculated to be 0.65%, with total offset error
= 130 µV, RSENSE = 1 mΩ, and ISENSE = 20 A.
Total Offset Error (V)
Total Offset Error (%) = u 100%
ISENSE u RSENSE (7)
One method of calculating the total error is to add the gain error to the percentage contribution of the offset error.
However, in this case, the gain error and the offset error do not have an influence or correlation to each other. A
more statistically accurate method of calculating the total error is to use the RSS sum of the errors, as shown in
Equation 8:
Total Error (%) = Total Gain Error (%)2 + Total Offset Error (%)2 (8)
After applying Equation 8, the total current sense error at maximum current is calculated to be 0.68%, which is
less than the design example requirement of 1%.
The INA185A3 (gain = 100) also has a bandwidth of 150 kHz that meets the small-signal bandwidth requirement
of 100 kHz. If higher bandwidth is required, lower-gain devices can be used at the expense of either reduced
output voltage range or an increased value of RSENSE.
VOUT
0V VREF
Time (500 µs/div)
C002
IN±
±
RPROTECT OUT
Output
< 10 +
REF
IN+
GND
In the event that low-power Zener diodes do not have sufficient transient absorption capability, a higher-power
transzorb must be used. The most package-efficient solution involves using a single transzorb and back-to-back
diodes between the device inputs, as shown in Figure 43. The most space-efficient solutions are dual, series-
connected diodes in a single SOT-523 or SOD-523 package. In either of the examples shown in Figure 42 and
Figure 43, the total board area required by the INA185 with all protective components is less than that of an SO-
8 package, and only slightly greater than that of an MSOP-8 package.
VS
Bus Supply 2.7 V to 5.5 V CBYPASS
±0.2 V to +26 V 0.1 µF
RSENSE
Load
INA185 VS
< 10
IN±
±
Transorb OUT
Output
+
< 10
REF
IN+
GND
Figure 43. Transient Protection Using a Single Transzorb and Input Clamps
For more information, see Current Shunt Monitor With Transient Robustness Reference Design.
10 Layout
Bus Voltage:
±0.2V to +26 V
RSHUNT
IN± 4 3 IN+
Connect REF to low
impedance voltage reference REF 5 2 GND
or to GND pin if not used.
Current
VS 6 1 OUT
Sense
VIA to Ground
Plane
CBYPASS
Power-Supply, VS
2.7 V to 5.5 V
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 23-Mar-2019
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Mar-2019
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0006A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1 A
ID AREA
1
6
4X 0.5
1.7
1.5
2X 1 NOTE 3
4
3
0.6 MAX
C
SEATING PLANE
0.18
6X 0.05 C
0.08 SYMM
SYMM
0.27
6X
0.15
0.1 C A B
0.4
6X 0.05
0.2
4223266/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
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EXAMPLE BOARD LAYOUT
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6X (0.3) 6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDERMASK DETAILS
4223266/C 12/2021
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6X (0.3) 6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
4223266/C 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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