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SEMICONDUCTOR TECHNICAL DATA by MCM69P618C/D

MCM69P618C
64K x 18 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM69P618C is a 1M–bit synchronous fast static RAM designed to pro-
vide a burstable, high performance, secondary cache for the 68K Family,
PowerPC, 486, i960, and Pentium microprocessors. It is organized as 64K TQ PACKAGE

C.
words of 18 bits each. This device integrates input registers, an output register, TQFP

IN
a 2–bit address counter, and high speed SRAM onto a single monolithic circuit CASE 983A–01

R,
for reduced parts count in cache data RAM applications. Synchronous design
allows precise cycle control with the use of an external clock (K). BiCMOS cir-
O
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cuitry reduces the overall power consumption of the integrated functions for
greater reliability. U
ND
Freescale Semiconductor, Inc...

Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and Linear Burst Order (LBO) are clock (K) controlled throughO
IC
positive–edge–triggered noninverting registers.
E M
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent
Ssequence
burst
addresses can be generated internally by the MCM69P618C (burst E
L of LBO) and
operates in linear or interleaved mode dependent upon the A state
controlled by the burst address advance (ADV) input pin.
S C
Write cycles are internally self–timed and initiated E
E by the rising edge of the
FR signals.
clock (K) input. This feature eliminates complex off–chip write pulse generation

BY global write (SGW), and syn-

and provides increased timing flexibility for incoming
D
Synchronous byte write (SBx), synchronous
E to allow writes to either individual bytes
Vdesignated
chronous write enable SW are provided
or to both bytes. The two bytes are I
H bytes are written
as “a” and “b”. SBa controls DQa
C
ARbytes are written if either SGW is asserted or if both
and SBb controls DQb. Individual if the selected byte writes SBx
are asserted with SW. Both
SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM69P618C operates from a single 3.3 V power supply and all inputs
and outputs are LVTTL compatible and 5 V tolerant.
• MCM69P618C–4 = 4 ns Access / 7.5 ns Cycle
MCM69P618C–4.5 = 4.5 ns Access / 8 ns Cycle
MCM69P618C–5 = 5 ns Access / 10 ns Cycle
MCM69P618C–6 = 6 ns Access / 12 ns Cycle
MCM69P618C–7 = 7 ns Access / 13.3 ns Cycle
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Single–Cycle Deselect Timing
• 5 V Tolerant on all Pins (Inputs and I/Os)
• 100–Pin TQFP Package

The PowerPC name is a trademark of IBM Corp., used under license therefrom.
i960 and Pentium are trademarks of Intel Corp.

REV 2
2/16/98


MOTOROLA FAST SRAM
Motorola, Inc. 1998 For More Information On This Product, MCM69P618C
Go to: www.freescale.com 1
 Freescale Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
LBO

ADV
K
BURST 2 16
COUNTER 64K x 18 ARRAY
ADSC
K2
ADSP CLR

2
SA
ADDRESS 16 14
SA1
SA0 REGISTER

C .
IN
R,
SGW

O
CT
SW 18 18
WRITE
U
ND
REGISTER
Freescale Semiconductor, Inc...

O
a
SBa
IC
EM
2
S DATA–IN DATA–0UT

LE
WRITE REGISTER REGISTER
A
REGISTER K

SC
b

EE
SBb

F R
BY K2 K

VED
I
SE1
SE2
RCH ENABLE ENABLE
SE3 A REGISTER REGISTER

G
DQa, DQb

MCM69P618C For More Information On This Product, MOTOROLA FAST SRAM

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 Freescale Semiconductor, Inc.
PIN ASSIGNMENT

ADSC
ADSP
SGW
VDD

ADV
VSS
SE1
SE2

SBb
SBa
SE3

SW
NC
NC
SA
SA

SA
SA
G
K
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC 1 80 SA
NC 2 79 NC
NC 3 78 NC
VDD 4 77 VDD
VSS 5 76 VSS
NC 6 75 NC
NC 7 74 DQa
DQb 8 73 DQa
DQb 9 72 DQa
C .
IN
VSS 10 71 VSS

R,
VDD 11 70 VDD
DQb 12
O 69 DQa
CT
DQb 13 68 DQa
NC 14 U VSS

ND
67
Freescale Semiconductor, Inc...

VDD 15 66 NC
O
IC
NC 16 65 VDD
VSS
EM
17 64 NC
DQb 18
S
63 DQa

LE
DQb 19 62 DQa
VDD 20
A
61 VDD

SC
VSS 21 60 VSS

EE
DQb 22 59 DQa
R
DQb 23 58 DQa
DQb 24 F 57 NC
NC 25
BY 56 NC

ED
VSS 26 55 VSS

V
VDD VDD
I
27 54

CH
NC 28 53 NC

R
NC 29 52 NC
A NC 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
51 NC
SA1
SA
SA
SA
SA

VSS

SA
SA
SA
SA
SA
SA0
LBO

NC
NC

VDD
NC
NC

NC
NC

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PIN DESCRIPTIONS
Pin Locations Symbol Type Description
85 ADSC Input Synchronous Address Status Controller: Initiates READ, WRITE, or
chip deselect cycle.
84 ADSP Input Synchronous Address Status Processor: Initiates READ, WRITE, or
chip deselect cycle (exception — chip deselect does not occur when
ADSP is asserted and SE1 is high).
83 ADV Input Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74 DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24 (byte a, b).
86 G Input Asynchronous Output Enable Input:
C .
Low — enables output buffers (DQx pins).
IN
R,
High — DQx pins are high impedance.
O
CT
89 K Input Clock: This signal registers the address, data in, and all control signals
except G and LBO.
U
NDThis pin must remain in steady state (this
Freescale Semiconductor, Inc...

O
31 LBO Input Linear Burst Order Input:

IC counter (68K/PowerPC).
signal not registered or latched). It must be tied high or low.
M
Low — linear burst
SE
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46, SA Input
A LE
Synchronous Address Inputs: These inputs are registered and must

SC Synchronous Address Inputs: These pins must be wired to the two

47, 48, 80, 81, 82, 99, 100 meet setup and hold times.
36, 37 SA1,SA0
E E
Input

FR
LSBs of the address bus for proper burst operation. These inputs are

Y
registered and must meet setup and hold times.
BSBx
ED
93, 94 Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

V
(a) (b) a, b). SGW overrides SBx.
I
CH
98 SE1 Input Synchronous Chip Enable: Active low to enable chip.

AR Negated high–blocks ADSP or deselects chip when ADSC is asserted.

97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87 SW Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
4, 11, 15, 20, 27, 41, 54, VDD Supply Power Supply: 3.3 V + 10%, – 5%.
61, 65, 70, 77, 91
5, 10, 17, 21, 26, 40, 55, VSS Supply Ground.
60, 67, 71, 76, 90
64 NC Input No Connection: There is no connection to the chip. For compatibility
reasons, it is recommended that this pin be tied low for system designs
that do not have a sleep mode associated with the cache/memory
controller. Other vendors’ RAMs may have implemented the Sleep
Mode (ZZ) feature.
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, NC — No Connection: There is no connection to the chip.
38, 39, 42, 43, 49, 50, 51, 52,
53, 56, 57, 66, 75, 78, 79, 95, 96

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 Freescale Semiconductor, Inc.
TRUTH TABLE (See Notes 1 through 4)
Address
Next Cycle Used SE1 SE2 SE3 ADSP ADSC ADV G3 DQx Write 2, 4
Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X X High–Z READ
Begin Read External 0 1 0 1 0 X X High–Z READ

C.
Continue Read Next X X X 1 1 0 1 High–Z READ

N
Continue Read Next X X X 1 1 0 0 DQ READ
1 , I High–Z
O0R
Continue Read Next 1 X X X 1 0 READ

T
Continue Read Next 1 X X X 1 0 DQ READ
1 C
U
Suspend Read Current X X X 1 1 1 High–Z READ

ND 1
Freescale Semiconductor, Inc...

Suspend Read Current X X X 1 1 0 DQ READ

O
IC
Suspend Read Current 1 X X X 1 1 1 High–Z READ

EM
Suspend Read Current 1 X X X 1 1 0 DQ READ
S
LEX
Begin Write Current X X X 1 1 1 X High–Z WRITE

A
Begin Write Current 1 X X 1 1 X High–Z WRITE
Begin Write External 0 1
S0C 1 0 X X High–Z WRITE
Continue Write Next X X EE X 1 1 0 X High–Z WRITE
Continue Write Next 1 FX R X X 1 0 X High–Z WRITE
Suspend Write Current X BY X X 1 1 1 X High–Z WRITE
Suspend Write Current
VED
1 X X X 1 1 X High–Z WRITE
I
CH
NOTES:

R
1. X = Don’t Care. 1 = logic high. 0 = logic low.
A
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G
must also remain negated at the completion of the write cycle to ensure proper write data hold times.

LINEAR BURST ADDRESS TABLE (LBO = VSS)

1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10

INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)

1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00

WRITE TRUTH TABLE

Cycle Type SGW SW SBa SBb
Read H H X X
Read H L H H
Write Byte a H L L H
Write Byte b H L H L
Write All Bytes H L L L
Write All Bytes L X X X

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ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Symbol Value Unit This device contains circuitry to protect the
inputs against damage due to high static volt-
Power Supply Voltage VDD – 0.5 to + 4.6 V ages or electric fields; however, it is advised
that normal precautions be taken to avoid
Voltage Relative to VSS for Any Vin, Vout – 0.5 to 6.0 V
application of any voltage higher than maxi-
Pin Except VDD
mum rated voltages to this high–impedance
Output Current (per I/O) Iout ± 20 mA circuit.

Package Power Dissipation (See Note 2) PD 1.6 W

Temperature Under Bias Tbias – 10 to 85 °C
Storage Temperature Tstg – 55 to 125 °C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
C .
exceeded. Functional operation should be restricted to RECOMMENDED OPER–
IN
R,
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
O
CT
periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use
U
ND
environment. See Package Thermal Characteristics.
Freescale Semiconductor, Inc...

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IC
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PACKAGE THERMAL CHARACTERISTICS
Rating
S Symbol Max Unit Notes

L E °C/W
A Four–Layer Board
Thermal Resistance Junction to Ambient (@ 200 lfm) Single–Layer Board RθJA 40 1, 2

S C 25
Thermal Resistance Junction to Board (Bottom)
REE RθJB 17 °C/W 1, 3
Thermal Resistance Junction to Case (Top) F RθJC 9 °C/W 1, 4
NOTES: BY
ED
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
V
I
temperature, air flow, board population, and board thermal resistance.

CH
2. Per SEMI G38–87.

AR
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method
1012.1).

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 Freescale Semiconductor, Inc.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)

Parameter Symbol Min Typ Max Unit
Supply Voltage VDD 3.135 3.3 3.6 V
Input Low Voltage VIL – 0.5* — 0.8 V
Input High Voltage VIH 2 — 5.5** V
* VIL ≥ – 2 V for t ≤ tKHKH/2.
** VIH ≤ 6 V for t ≤ tKHKH/2.

DC CHARACTERISTICS AND SUPPLY CURRENTS

N C.
I Max
R,
Parameter Symbol Min Unit Notes
Input Leakage Current (0 V ≤ Vin ≤ VDD) (Excluding LBO) Ilkg(I)
TO
— ±1 µA
Output Leakage Current (0 V ≤ Vin ≤ VDD) Ilkg(O) UC — ±1 µA
ND
Freescale Semiconductor, Inc...

O
AC Supply Current (Device Selected, All Outputs Open, MCM69P618C–4 IDDA — 300 mA 1, 2, 3
MCM69P618C–4.5 C
MCM69P618C–5MI
Cycle Time ≥ tKHKH min) 295

SE
275
MCM69P618C–6 260
E
AL
MCM69P618C–7 255
CMOS Standby Supply Current (Deselected, Clock (K)
S C
MCM69P618C–4 ISB1 — 160 mA 4

EE MCM69P618C–5
Cycle Time ≥ tKHKH, All Inputs Toggling at CMOS MCM69P618C–4.5 155
Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
R
130
F MCM69P618C–6 110

B Y MCM69P618C–7 105

Cycle Time ≥ tKHKH, All Other InputsV EDtoClock

Clock Running Supply Current (Deselected, (K) MCM69P618C–4 ISB2 — 50 mA 4

or I≥ VDD – 0.2 V)
Held Static MCM69P618C–4.5 50
CMOS Levels Vin ≤ VSS + 0.2 V H
C
MCM69P618C–5 45

AR
MCM69P618C–6 40
MCM69P618C–7 40
Output Low Voltage (IOL = 8 mA) VOL — 0.4 V
Output High Voltage (IOH = – 4 mA) VOH 2.4 — V
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing.
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
4. Device in Deselected mode as defined by the Truth Table.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter Symbol Min Typ Max Unit
Input Capacitance Cin — 4 6 pF
Input/Output Capacitance CI/O — 7 9 pF

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 Freescale Semiconductor, Inc.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)

READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)

69P618C–4 69P618C–4.5 69P618C–5 69P618C–6 69P618C–7
P
Parameter S b l
Symbol Min Max Min Max Min Max Min Max Min Max U i
Unit N
Notes
Cycle Time tKHKH 7.5 — 8 — 10 — 12 — 13.3 — ns

C.
Clock High Pulse Width tKHKL 3 — 3 — 3 — 4 — 4.5 — ns

IN
Clock Low Pulse Width tKLKH 3 — 3 — 3 — 4 — 4.5 — ns
Clock Access Time tKHQV — 4 — 4.5 — 5 — 6R, — 7 ns
O
— T 5
Output Enable to Output Valid tGLQV — 4 — 4.5 — 5
U C — 6 ns
Clock High to Output Active tKHQX1 1.5 — 1.5 — 0 — D 0 — 0 — ns 4
N
Freescale Semiconductor, Inc...

O—
IC —
Clock High to Output Change tKHQX2 1.5 — 1.5 — 2 2 — 2 — ns 4

EM
Output Enable to Output tGLQX 0 — 0 — 0 0 — 0 — ns 4
Active
S
L E4.5
A
Output Disable to Q High–Z tGHQZ — 4 — — 5 — 5 — 5 ns 4, 5
Clock High to Q High–Z tKHQZ 2 4
SC2 4.5 2 5 2 5 2 5 ns 4, 5
Setup Times: Address tADKH 2
REE
— 2.5 — 2.5 — 2.5 — 2.5 — ns
ADSP, ADSC, ADV tADSKH F
Data In tDVKH
BY
ED
Write tWVKH

V
Chip Enable tEVKH
I
Hold Times: Address
RCH tKHAX 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

A
ADSP, ADSC, ADV tKHADSX
Data In tKHDX
Write tKHWX
Chip Enable tKHEX
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.

OUTPUT
Z0 = 50 Ω RL = 50 Ω

VT = 1.5 V

Figure 1. AC Test Load

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READ/WRITE CYCLES

tKHKH tKHKL tKLKH

A
SA A B C D

MOTOROLA FAST SRAM

CH
I
ADSP

VED
ADSC

BY
F R
ADV

EE
SC
SE1 ALE
S

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O

Go to: www.freescale.com
ND

t KHQV
U

BURST WRAPS AROUND

G

For More Information On This Product,

CT
Freescale Semiconductor, Inc.

t KHQV
R,

DQx Q(n) Q(A) Q(B) Q(B+1) Q(B+2) Q(B+3) Q(B) D(C) D(C+1) D(C+2) D(C+3) Q(D)
IN

tKHQZ tKHQX1 tKHQX2 tGHQZ ADSP, SA tGLQX

.C

SE2, SE3
IGNORED
DESELECTED SINGLE READ BURST READ BURST WRITE SINGLE READ

NOTE: E low = SE2 high and SE3 low.

W low = SGW low and/or SW and SBx low.

9
MCM69P618C
 Freescale Semiconductor, Inc.
APPLICATION INFORMATION

The MCM69P618C BurstRAM is a high speed synchro- Since most L2 caches are tied to the processor bus and
nous SRAM that is intended for use primarily in secondary or bus speeds continue to increase over time, pipelined (R/R)
level two (L2) cache memory applications. L2 caches are BurstRAMs are the best choice in achieving zero–wait state
found in a variety of classes of computers — from the desk- L2 cache performance. At bus speeds ranging from 66 MHz
top personal computer to the high–end servers and trans- to 100 MHz, pipelined BurstRAMs are able to provide fast
action processing machines. For simplicity, the majority of L2 clock to valid data times required of these high speed buses.
caches today are direct mapped and are single bank imple-
mentations. These caches tend to be designed for bus NON–BURST SYNCHRONOUS OPERATION
speeds in the range of 33 to 66 MHz. At these bus rates,
non–pipelined (flow–through) BurstRAMs can be used since Although this BurstRAM has been designed for 68K–,
their access times meet the speed requirements for a mini- PowerPC–, 486–, i960–, and Pentium–based systems,
mum–latency, zero–wait state L2 cache interface. Latency is these SRAMs can be used in other high
C. speed L2 cache or
memory applications that do notNrequire the burst address
, I with a synchronous inter-
a measure (time) of “dead” time the memory system exhibits
as a result of a memory request. feature. Most L2 caches designed
R
face can make use of theOMCM69P618C. The burst counter
CTcan be disabled, and the SRAM can
For those applications that demand bus operation at great-
U
er than 66 MHz or multi–bank L2 caches at 66 MHz, the pipe- feature of the BurstRAM
be configured toD act upon a continuous stream of addresses.
See Figure 2.N
lined (register/register) version of the 64K x 18 BurstRAM
Freescale Semiconductor, Inc...

(MCM69P618C) allows the user to configure the RAM to O

support such designs. Multiple banks of BurstRAMs create CONTROL IC PIN TIE VALUES EXAMPLE (H ≥ VIH, L ≤ VIL)
M
SENon–Burst ADSP ADSC ADV SE1 SE2 LBO
additional bus loading and can cause the system to other-

to–valid–data) of a pipelined BurstRAM is inherently faster LE Sync Non–Burst,

wise miss its timing requirements. The access time (clock–
H L H L H X
A
SC
than a non–pipelined device by a few nanoseconds. This Pipelined SRAM
does not come without cost. The cost is latency — E
RE
“dead” NOTE: Although X is specified in the table as a don’t care, the pin
time.
F
must be tied either high or low.

BY
VED
I
K
RCH
A
ADDR A B C D E F G H

SE3

DQ Q(A) Q(B) Q(C) Q(D) D(E) D(F) D(G) D(H)

READS WRITES

Figure 2. Example Configuration as Non–Burst Synchronous SRAM

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ORDERING INFORMATION
(Order by Full Part Number)

MCM 69P618C XX X X
Motorola Memory Prefix Blank = Trays, R = Tape and Reel
Part Number Speed (4 = 4 ns, 4.5 = 4.5 ns, 5 = 5 ns,
6 = 6 ns, 7 = 7 ns)
Package (TQ = TQFP)

Full Part Numbers — MCM69P618CTQ4 MCM69P618CTQ4R

MCM69P618CTQ4.5 MCM69P618CTQ4.5R
MCM69P618CTQ5 MCM69P618CTQ5R
MCM69P618CTQ6 MCM69P618CTQ6R
MCM69P618CTQ7 MCM69P618CTQ7R
C .
IN
O R,
U CT
ND
Freescale Semiconductor, Inc...

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ALE
SC
REE
F
BY
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A

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

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 Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
TQ PACKAGE
TQFP
CASE 983A–01
4X e
0.20 (0.008) H A–B D
2X 30 TIPS e/2
0.20 (0.008) C A–B D
–D–
80 51
B
81 50
–X–
E/2 B
X=A, B, OR D
–A– –B– VIEW Y
C .
IN
BASE
E1 E
R,
METAL PLATING

O b1

CT c
ÉÉÉÉ
ÇÇÇÇ
E1/2

U
ND ÇÇÇÇ
ÉÉÉÉ
100 31 c1
Freescale Semiconductor, Inc...

O
IC
1 30
b

EM
D1/2 D/2
S 0.13 (0.005) C A–B D
M S S
D1
D
ALE SECTION B–B

SC
2X 20 TIPS NOTES:

EE
1. DIMENSIONING AND TOLERANCING PER ANSI
0.20 (0.008) C A–B D Y14.5M, 1982.

F R 2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF

BY
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
A

ED
q 2 THE BOTTOM OF THE PARTING LINE.
0.10 (0.004) C 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED

V
–H–
I
AT DATUM PLANE –H–.

CH
5. DIMENSIONS D AND E TO BE DETERMINED AT
–C– SEATING PLANE –C–.

R
SEATING 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
3
A
q PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
PLANE
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
VIEW AB INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
0.05 (0.002) S PROTRUSION. DAMBAR PROTRUSION SHALL
S NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
q 1 MILLIMETERS INCHES
0.25 (0.010) DIM MIN MAX MIN MAX
GAGE PLANE A ––– 1.60 ––– 0.063
A2 R2 A1 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057
b 0.22 0.38 0.009 0.015
b1 0.22 0.33 0.009 0.013
c 0.09 0.20 0.004 0.008
A1 R1 L2 c1 0.09 0.16 0.004 0.006
L q D 22.00 BSC 0.866 BSC
D1 20.00 BSC 0.787 BSC
L1 E 16.00 BSC 0.630 BSC
E1 14.00 BSC 0.551 BSC
VIEW AB e 0.65 BSC 0.026 BSC
L 0.45 0.75 0.018 0.030
L1 1.00 REF 0.039 REF
L2 0.50 REF 0.020 REF
S 0.20 ––– 0.008 –––
R1 0.08 ––– 0.003 –––
R2 0.08 0.20 0.003 0.008
q 0_ 7_ 0_ 7_
q 1 0_ ––– 0_ –––
q 2 11 _ 13 _ 11 _ 13 _
q 3 11 _ 13 _ 11 _ 13 _

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How to reach us:
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P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
Mfax : [email protected] – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
– http://sps.motorola.com /mfax /
HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274

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