XB16: 16-Channel CMOS Crossbar

Fouad Kiamilev

SOUT

IN15
IN0
CLK
CLR
SIN

.
.
.
.
.
.
Fanout Buffers

Fanin Mux #0 out0

64-Bit Shift-Register to Store Crossbar Configuration

Fanin Mux #1 out1

Fanin Mux #2 out2

Fanin Mux #3 out3

Fanin Mux #4 out4

Fanin Mux #5 out5

Fanin Mux #6 out6

Fanin Mux #7 out7

Fanin Mux #8 out8

Fanin Mux #9 out9

Fanin Mux #10 out10

Fanin Mux #11 out11

Fanin Mux #12 out12

Fanin Mux #13 out13

Fanin Mux #14 out14

Fanin Mux #15 out15

FEATURES:
• 0.5 micron Scalable CMOS layout (λ=0.35µm) [Metal3 is not used! ]
• 1.2mm x 0.6mm area
• 5V Supply voltage
• 4,600 MOS transistors
• 1,000Mbit/s per channel (16 input and 16 output channels)
• Synchronous Serial configuration
• Buffered input and output for high speed
• Cascadable to larger systems
• CMOS compatible inputs and outputs
• Can be configured for any 1-1 and/or 1-many connection pattern
• Full custom layout to ensure minimum skew between output ports

XB16 User Guide (Document # XB16-001) 1

Overview

The XB16 is a 16x16 crosspoint switch megacell intended for high-speed (up to 1,000Mb/s)
digital data communication applications. It is ideally suited for high-speed digital data switching
applications including technology demonstrators, telecommunications, compter network and
multiprocessor switching, and test equipment. This megacell has 16 data inputs and 16 data
outputs. Any input can be multiplexed to any, some or all outputs. High speed digital data up to
1,000Mb/s can be switched with 1 nanosecond latency. The megacell requires a 5v power
supply.

The crossbar connection pattern is stored in 64 on-chip registers. A separate serial interface
(composed of four wires) is used to configure the crossbar connection pattern. Using this
interface, the crossbar can be reprogrammed to a new connection pattern in 64 clock cycles.
Finally, multiple XB16 megacells can be combined to form a larger crosspoint switch.

SOUT

IN15
IN0
CLK
CLR
SIN

.
.
.
.
.
.
Fanout Buffers

Fanin Mux #0 out0

64-Bit Shift-Register to Store Crossbar Configuration

Fanin Mux #1 out1

Fanin Mux #2 out2

Fanin Mux #3 out3

Fanin Mux #4 out4

Fanin Mux #5 out5

Fanin Mux #6 out6

Fanin Mux #7 out7

Fanin Mux #8 out8

Fanin Mux #9 out9

Fanin Mux #10 out10

Fanin Mux #11 out11

Fanin Mux #12 out12

Fanin Mux #13 out13

Fanin Mux #14 out14

Fanin Mux #15 out15

Figure 1. Layout and floorplan for the XB16 megacell. Full-custom layout is used to ensure that
all input-output paths see the same delay due to logic and wiring parasitics. Power rails are sized
to ensure adequate current supply during high-speed operation of the circuitry.

XB16 User Guide (Document # XB16-001) 2

 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

S0
S1
S2
S3
2 1
3
4 7
5
6

FEK_MUX4

2 1
3
4 7
5
6

FEK_MUX4
2 1
2 1 3
3 4 7
4 7 5 OUT0
5 6
6
FEK_MUX4
FEK_MUX4

2 1
3
4 7
5
6

FEK_MUX4
S4
S5
S6
S7
2 1
3
4 7
5
6

FEK_MUX4

2 1
3
4 7
5
6

FEK_MUX4
2 1
2 1 3
3 4 7
4 7 5 OUT1
5 6
6
FEK_MUX4
FEK_MUX4

2 1
3
4 7
5
6

FEK_MUX4

Figure 2. Logic schematic for the XB16 megacell. To simplify the drawing, only two of the
sixteen output channels are shown. Each output channel is built using 5 four-input multiplexor
cells. All inputs are buffered for high-speed drive of large input capacitance.

XB16 User Guide (Document # XB16-001) 3

 1 D Q 4
SHIFT_IN S0
2 CLK Q 5
R
CLOCK
3
DFFR
CLEAR

1 D Q 4 S1
2 CLK Q 5
R
3 DFFR

1 D Q 4 S2
2 CLK Q 5
R
3 DFFR

1 D Q 4 S3
2 CLK Q 5
R
3 DFFR

1 D Q 4 S4
2 CLK Q 5
R
3
DFFR

1 D Q 4 S5
2 CLK Q 5
R
3 DFFR

1 D Q 4 S6
2 CLK Q 5
R
3 DFFR

1 D Q 4 S7
2 CLK Q 5
R
3 DFFR

Figure 3. Logic schematic for the 64-bit shift register used to store the crossbar connection
pattern. To simplify the drawing, only the first 8 registers are shown. Refer to figure 2 to see how
the outputs of the registers control the crossbar connection configuration.

XB16 User Guide (Document # XB16-001) 4

 S1 (1) S0 (2) IN3 (3) IN2 (4) IN1 (5) IN4 (6) Y (7)
0 0 X X X 0 0
0 0 X X X 1 1
0 1 X X 0 X 0
0 1 X X 1 X 1
1 0 X 0 X X 0
1 0 X 1 X X 1
1 1 0 X X X 0
1 1 1 X X X 1

Figure 4. Symbol and logic function for the 4-input multiplexor cell used in XB16.

Pin Description

Name Description
IN0- INPUT-CMOS. The 16 input channels.
IN15
OUT0- OUTPUT-CMOS. The 16 output channels.
OUT15
VDD Connected to 3.3 volts.
GND Connect to ground.
CLR INPUT-CMOS. Asynchronous clear signal. Normally this input is set HIGH.
When this input is driven LOW, the 64 registers that store the crossbar connection
pattern are reset to 0. Note that having all registers set to 0 corresponds to a
crossbar connection pattern where input channel #0 is broadcast to all the output
channels.
CLK INPUT-CMOS. On the rising edge of CLK, the input on SIN is shifted in.
SIN INPUT-CMOS. Connects to the input of the 1st register in the 64-bit chain.
SOUT OUTPUT-CMOS. Connects to the output of the last register in the 64-bit chain.
This output can be used to readout the current connection configuration for the
crossbar.

XB16 User Guide (Document # XB16-001) 5

Chip Operation
To operate the chip, the desired crossbar connection pattern is first loaded into the 64-bit shift-
register file. This step requires 64 clock cycles. Then, the input channels are asynchronously
connected to the appropriate output channels.

Simulation Results
Extensive spice-level simulation of the entire XB16 megacell was performed. The simulation
deck was created by extracting the entire chip with layout parasitic parameters such as wire
capacitance and diffusion capacitance for MOSFET devices. Some of the results are shown
below:

XB16 User Guide (Document # XB16-001) 6

Figure 5. In this simulation, the CLR line was held low to establish a connection pattern where
input channel #0 is broadcast to all the output channels. The top graph shows the input signal on
channel #0 with a 1 Gbit/sec “101010…” data stream. The bottom two curves show the outputs
from channels #0 and #15 respectively. Minimal skew is seen to exist between the output
channels. The input-output asynchrounous delay is approximately 1ns. Also, about 20% pulse
width distortion is introduced by the crossbar logic circuitry. Both the delay and pulse-width
distortion will vary as function of process variations encountered during a particular fabrication
run.

XB16 User Guide (Document # XB16-001) 7

List of Files
This section documents the files enclosed with this documentation. All the files were created
using the Tanner L-Edit and T-Spice layout and simulation software.

File Name Description

Xb16.pdf This file in pdf 3.0 format.

Xb16.doc This file in word 97 format.

Xb16.tdb Layout of the CLDA chip in Tanner L-Edit format. The L-Edit tool is layout
editor from Tanner Research that was used to layout the CLDA chip. The
layout uses Mosis scalable rules with lambda=0.35 micron. The DRC deck and
layer assignments are taken from Tanner distribution and use the Mosis 7.2
revision of the scalable MOS design rules.

Xb16.spc Extracted file containing the entire xb16 cell (this file is approx. 1Mbyte!)

Xb16.sp Command file used by tspice to simulate the xb16 cell.

Xb16.out Spice output file with simulation results. Tspice was used to produce this.

N71s.md Mosis level3 models for a particular 0.5micron CMOS run that was used to
simulate the xb16 cell.

XB16 User Guide (Document # XB16-001) 8