Chip Design
Professor: Sci.D., Professor
Vazgen Melikyan
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Chip Design
Lecture - 2
1 Developed By: Vazgen Melikyan
Course Overview
Introduction to Chip Design Physical Data Preparation
1 lecture 3 lectures
IC Manufacturing Process Liberty Format
1 lecture 2 lectures
Phases of IC Design Liberty NCX Introduction
1 lecture 1 lecture
Cell-Level Digital Design Flow Transistor level description
2 lectures 1 lecture
Digital Design Flow Physical Design Formats
2 lectures 2 lectures
Library/IP design Functional Description
1 lecture 2 lectures
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Chip Design
Lecture - 2
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IC Manufacturing Process
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Chip Design
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Largest IC Foundries
TSMC Taiwan Semiconductor Manufacturing Corporation
UMC United Microelectronics Corporation
CSM Chartered Semiconductor Manufacturing
IBM IBM Foundry Services
MXIC Micronics Foundry Services
TS Tower Semiconductor
SMIC Semiconductor Manufacturing International Corporation
LSI LSI Logic Foundry Services
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Evaluation of Technological
Processes
Technological processes are defined by the minimum length (L) of transistor channel
90nm technology – Lmin=90nm
45nm technology – Lmin=45nm
22nm technology – Lmin=22nm
14nm technology – Lmin=14nm
7nm technology – Lmin=7nm
Examples of technological processes:
TSMC 90nm G Logic 1.0V/3.3V G – generic
SMIC 90nm LL Logic 1.2V/3.3V LL – low leakage
SMIC 130nm LV Logic 1.0V/3.3V LV – low voltage
Samsung 32nm LP Logic 1.2V/3.3V LP – low power
UMC 32nm LL Logic 1.2V/2.5V
UMC 14nm LL Logic 0.8V/1.8V
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Chip Design
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IC Fabrication at a Glance
1. Growing of a giant crystal of silicon
2. Slicing it up into round wafers and polish them
3. Coating of a wafer with a photographic chemical
that hardens when exposed to light
4. Taking a picture of a pattern to embed in the silicon
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Chip Design
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IC Fabrication at a Glance (2)
10. Connection of chip parts to the pins
of the package with tiny gold wires
11. Putting of the chip on a tester machine and test
running
12. Assembly of different kinds of chips onto a board
13. Installation of the board into a phone, computer...
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Examples of Devices Used During IC
Fabrication
Photolithography stepper Gas cabinet
Wire bonder system Wafer probe Wafer Dicing, Sawing
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Steps of Photolithography
Photoresist coating
Photoresist
Etching
SiO 2
Substrate
Exposure Substrate
Mask
Exposed Photoresist removal
Unexposed
Substrate
Substrate
Development
Substrate
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Chip Design
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Design Rules, Necessity
Interface between the circuit designer and
process engineer
Guidelines for constructing process masks
Rules constructed to ensure that design
works even when small fabrication errors
occur
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Design Rules Example (1)
Resolution
min. width rule
min. spacing
Alignment min. poly width
min. poly overlap of diffusion
exact contact size
min. contact overlap
min. gate to contact spacing
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Design Rules , Example (2)
Minimum enclosure in the result of combination of dopant or
overhead layers (a)
Minimum spaces between objects on the same layer to ensure they
will not short after fabrication (b)
Provision of minimum overlap of layers (c)
Minimum dimensions of objects on each layer to maintain that object
after fabrication (d)
d
b c
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Design Rules , Example (3)
N Well
c
h P Well
f N+ Active
b
e P+ Active
a g Deep N Well
d
a – minimum width
b, e, g, h – minimum spacing
c, f – minimum enclosure
d – minimum overlap
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Design Rules, Transistor
Layout
Transistor
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Design Rules, Vias and Contacts
Metal to DIFF Contact Metal to Poly Contact Metal1 to Metal2 Via
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No Image = No Product
Layout 0.25µ 0.18µ
0.13µ 90nm 65nm
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Lithography: Printability Issues
180nm 130nm 90nm and Below
Design
OPC PSM
0°
Mask
180° 0°
OPC 180°
Wafer
Wavelength: 193nm
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Optical Proximity Correction (OPC)
Conventional (no
OPC) Silicon image without OPC
Original layout
0.18 m
OPC layout Silicon image with OPC
Optimal proximity correction (OPC) is a corrective technique that adds small
objects to photomask that will not print frequently by enlarging corners or
adding bias lines to the edge of a feature
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